440GX Application Note

Transcription

1 DDR Memory and the PowerPC 440GP/GX DDR SRAM Controller January 22, 2008 Abstract DDR (double data rate) memory is very similar to existing SDRAM (synchronous dynamic random access memory) in many ways, including control structure, burst architecture, and command interface, but there are important differences between the two memory architectures. One key difference is the data transfer method. In SDRAM, one addressed unit of data is transferred on each rising edge of the memory clock signal. The memory clock is the main synchronizing signal in the SDRAM memory system. DDR memory, on the other hand, is burst-oriented and transfers data in units of two with a configurable burst size of 2, 4, or 8 units. The first unit of data is associated with the rising edge of the memory clock signal and the second unit of data is associated with the falling edge. The transfer rate effectively doubles that of older SDRAM memories. A second important feature of the DDR memory system is its use of the source-synchronous data strobe signal. The AMCC PowerPC 440GP and PowerPC 440GX both have an x8 organization to their memory interfaces. Each byte of the DDR interface has its own data strobe, DQSx. The PowerPC 440GP/GX generates the strobe signal during data write operations. The memory system generates the strobe signal during data reads. The memory system can operate with Error Checking and Correcting (ECC) where single bit errors are corrected and double bit errors are detected. The ECC function can be used with either bit-width of the memory system. This application note provides an overview of the DDR SDRAM interface for the PowerPC 440GP/GX, including discussions of memory write and memory read operations. This note also discusses ECC operations, and it provides suggestions for setting the read data path as well as general suggestions. Overview of the PowerPC 440GP/GX DDR SDRAM Interface The DDR SDRAM interface on the PowerPC 440GP/GX supports x8 DDR SDRAM in either a point-to-point or DIMM-based memory system. The DDR SDRAM interface consists of a processor local bus (PLB) slave interface and a device control register (DCR) interface. It provides a 32-bit or 64-bit interface with optional ECC. The DDR controller can support up to four 512-MB logical banks in limited configurations, providing memory up to 2 GB. Global memory timings, address and bank sizes, and memory addressing modes are programmable. The DDR SDRAM can be relocated in the memory address range, but relocation is generally not needed. Note: Placing the DDR SDRAM controller in sleep or self-refresh mode (or both) can reduce system power. In some respects, the DDR SDRAM interface can be broken down into three basic functional blocks: Configuration Write operations Read operations The configuration block controls the overall functionality of the memory controller interface. Registers control all of the configurable parameters of the DDR interface. The register values depend upon the type of memory system used and the parameters of the memory components. Because of the high signal-switching speeds, a detailed timing analysis of the memory system must be derived. Memory write operations are the least difficult to set up and perform correctly. See DDR SDRAM Memory Write Operations on page 2. Memory read transactions are more difficult to configure. The DDR SDRAM controller can alter the timing of various signals in relation to each other to allow fine-tuning of the memory system timings. See DDR SDRAM Memory Read Operations on page 2. Revision 1.01 Application Note (Proprietary) AN2008

2 DDR SDRAM Memory Write Operations When performing a memory write operation, the JEDEC DDR specification (JES79) states that the data strobe signal should appear in the middle of the associated data unit. The rising edge of the strobe signal should appear in the middle of the first unit of data and the falling edge of the strobe signal should appear in the second data unit. See Figure 1. Figure 1: Typical DDR Data Write Burst Operation, CAS 1 Device 1 When reviewing the timing information available for the DDR interface used in the PowerPC 440GP/GX, the end user will find that the data, strobe lines, and MemClkOut0 are skewed from this perfect alignment. In short, MemClkOut0 is out of alignment with the data and data strobe signals. This skewing is due to the internal routing of the signal lines, and it can generally be corrected using the timing registers in the interface. If the end user advances the MemClkOut0 signal by 90, most of the skew will be removed and the timings should appear close to ideal (MemClkOut0, data, and the strobe bits are roughly 625 ps out of alignment). Note: DDR memory devices have a data acceptance window for accepting a data write that is nearly a half-clock cycle wide, centered around the edges of the MemClkOut0 signal. This window is usually expressed as tdqss min and max. With a good layout, and by advancing MemClkOut0 by 90, DDR writes should always work. The timing can be further positioned using the SDRAM0_CLKTR register. Refer to the PowerPC 440GP User's Manual for more details and explanations. 2 Application Note (Proprietary) Revision 1.01

3 DDR SDRAM Memory Read Operations When performing memory reads, the JEDEC DDR specification states that data is launched coincidentally with the data strobe signal (see Figure 2). This means that the leading edge of data and the leading edge of the data strobe are sent in sync with each other from the DDR memory devices. Figure 2: Typical DDR Data Read Burst Operation, CAS 2 Device When data and strobe signals arrive at the input to the PowerPC 440GP/GX simultaneously, there is not adequate setup time for the arriving data to be latched into the read data path. To overcome this timing problem, all strobe signals are delayed by one-quarter of a memory clock cycle. The internals of the DDR memory controller found inside of the 440GP/GX generate the one-quarter of a cycle delay automatically. Unless the there is a problem with the PC Board layout, data should always be captured in the input stage of the read data path. The read data path stages are discussed on page 4. Revision 1.01 Application Note (Proprietary) 3

4 Read Data Path The read data path (see Figure 3) is key to synchronizing the data that arrives from the memory system with its time domain and realigning the data to the internal PowerPC 440GP/GX time domain. As shown in Figure 3 on page 4, the PLB must eventually pick up all memory system reads. Figure 3: Typical DDR Data Read Burst Operation, CAS 2 Device There are three stages to the read data path: Stage 1. Capture incoming data from the memory system. Stage 2. Realign the incoming data and its memory system time domain to the internal (PLB) time domain using the programmable delay settings. Stage 3. Insert an addition delay in case Stage 2 does not allow enough time to move the data to the PLB or perform ECC calculation logic (or both). The end user selects the path that data travels by way of a detailed timing budget analysis. The PowerPC 440GP User's Manual discusses the details of selecting the proper stages to use depending upon the structure of the memory system. The Read Sample Point setting is used to coordinate the collection of data from the read data path with the time that the data is placed on the PLB. This coordination is fairly straightforward. The SDRAM0_TR1[RDSS] setting determines the clock cycle relative to the DDR read command, during which the internal logic should sample the read data and move it to the PLB. This value is relative to the CAS latency of the memory system and the stages through which the data flows. Basically, the more stages that data passes through in the read data path, the later the data is sampled and deposited on the PLB. Refer to the PowerPC 440GP User's Manual for rules for determining which sample point to select. Note: The major consideration when tuning the read data path should be the results of a timing budget calculation. The end user must calculate the total delays associated with read data and the effects of board layout. The timing budget calculations are beyond the scope of this document, but keep in mind the time it takes to generate ECC value and the time it takes to flow through the read data path. 4 Application Note (Proprietary) Revision 1.01

5 ECC Operations The DDR SDRAM controller in the PowerPC 440GP/GX has the ability to detect and correct single bit errors and detect double bit errors in the data being read from the memory system. In order to perform this function, an additional dedicated byte-wide DDR SDRAM device is added to the memory system. The additional memory device is used to hold the ECC values. Performing the ECC function on read data takes 4.0 ns. When enabling the ECC function, the timing budget calculations must include this value. This extra time can affect the path data takes through the read data path. If the memory system is physically compact, Stage 2 timing with ECC is possible, but generally data will have to travel through Stage 3 to ensure that there is enough time to receive the data, perform the ECC process on the data, and still have enough setup time for the data to be placed on the PLB bus. Read Data Path Suggestions The internal stages in the read data path are used to realign the external data to the internal time domain of the processor. Refer to the information about DDR in the PowerPC 440GP User's Manual for details about selecting the proper stages that data should follow in the read data path. Stage 1 is the low-latency, and therefore fastest, path to the PLB. Data needs to be delivered and have time to flow to the PLB sample register. This path will not usually allow the ECC operation to be performed; there is just not enough time to do everything. Stage 2 is the usual path for most memory systems. This allows the data to be captured, realigned to the internal timing, and sometimes passed through the ECC logic. Using Stage 2 does not necessarily guarantee being able to perform the ECC function and meeting the setup time for the PLB bus stage. Stage 3 is usually used for CAS 2.5 devices, but it is also used to allow enough time to perform the ECC process on the incoming data. Refer to the PowerPC 440GP User's Manual for the details about the read data path and suggestions for selecting the proper stages to use in the read data path. Revision 1.01 Application Note (Proprietary) 5

6 General Suggestions The setup and hold times for the internal flip-flops of the read data path are 100 ps for setup and 200 ps for hold. When using ECC memory devices, the end user must take into account the time delay associated with the ECC logic. It takes 4.0 ns to perform this operation, plus the 100 ps setup time needed for the flip-flops that capture data to the PLB bus. Fixed values for the delay line calibration register can be calculated and should work for all logic boards. However, because all chips are different, process variations can affect the calibration process and board build variabilities can affect timing. Temperature can also have an effect. The delay line used in the PowerPC 440 processors should be stable to ± 200 ps. Calculated values for the programmable delay line should be stable for the particular implementations of the processor, but this should be proven on the target system and environments through testing. If this variability is too large, active tuning code can be developed to actively tune in the memory systemstimingvalues.thesoftware' can be executed each time the target board is powered up, allowing the DDR memory system interface timings to be optimized. In addition, the software can be rerun when desired to optimize timing values. The following three groups of sample register settings were generated for two different memory systems: a small point-to-point system and the PowerPC 440GP evaluation board. The small point-to-point system was built from the individual memory parts, one ECC memory, and two main memory components, soldered directly to the circuit board. The remaining values were generated from the PowerPC 440GP evaluation board. Note: These groups of registers do not cover all the settings that are needed to properly configure the DDR SDRAM controller. Point-to-point sample DDR memory controller settings (128-MB CAS MHz NON-ECC DIMM) - SDRAM0_TR0 = x' ' - SDRAM0_TR1 = x' ' - SDRAM0_CFG0 = x'b ' - SDRAM0_CLKTR = x' ' - SDRAM0_WDDCTR = x' ' PowerPC 440GP evaluation board memory controller settings (128-MB CAS MHz NON-ECC DIMM) - SDRAM0_TR0 = x'410a 4012' - SDRAM0_TR1 = x' C' - SDRAM0_DLYCAL = x' ' - SDRAM0_CFG0 = x'b ' - SDRAM0_B0CR = x'000a 4001' PowerPC 440GP evaluation board memory controller settings (256-MB CAS MHz ECC DIMM) - SDRAM0_TR0 = x'410a 4012' - SDRAM0_TR1 = x' ' - SDRAM0_DLYCAL = x' ' - SDRAM0_CFG0 = x'b ' - SDRAM0_B0CR = x'000c 4001' - SDRAM0_WDDCTR = x' ' 6 Application Note (Proprietary) Revision 1.01

7 Conclusion The DDR SDRAM memory controller in the PowerPC 440GP/GX is very flexible, but can be complex to set up. The end user must understand the function of the DDR controller, the functionality of the memory devices, and the timings associated with the end design before attempting to set up the DDR controller. With a little time and investigation, however, the task of configuring the interface can be made less complex. Revision 1.01 Application Note (Proprietary) 7

8 Document Revision History Revision Date Description v1.01 1/22/08 Converted layout to AMCC format. 8 Application Note (Proprietary) Revision 1.01

9 Applied Micro Circuits Corporation 6310 Sequence Dr., San Diego, CA Main Phone: (858) Technical Support Phone: (858) (800) AMCC reserves the right to make changes to its products, its datasheets, or related documentation, without notice and warrants its products solely pursuant to its terms and conditions of sale, only to substantially comply with the latest available datasheet. Please consult AMCC s Term and Conditions of Sale for its warranties and other terms, conditions and limitations. AMCC may discontinue any semiconductor product or service without notice, and advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the information is current. AMCC does not assume any liability arising out of the application or use of any product or circuit described herein, neither does it convey any license under its patent rights nor the rights of others. AMCC reserves the right to ship devices of higher grade in place of those of lower grade. AMCC SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. AMCC is a registered Trademark of Applied Micro Circuits Corporation. Copyright 2008 Applied Micro Circuits Corporation. I2C BUS is a registered Trademark of Philips N.V. Corporation Netherlands. Revision 1.01 Application Note (Proprietary) 9