ALTERA_CORDIC IP Core User Guide

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2 Contents Contents ALTERA_CORDIC IP Core Features DSP IP Core Device Famil Support ALTERA_CORDIC IP Core Functional Description SinCos Function Atan2 Function Vector Translate Function Vector Rotate Function ALTERA_CORDIC IP Core Parameters ALTERA_CORDIC IP Core Signals

3 1 Use the ALTERA_CORDIC IP core to implement a set of fied-point functions with the CORDIC algorithm. ALTERA_CORDIC IP Core Features on page 3 DSP IP Core Device Famil Support on page 3 ALTERA_CORDIC IP Core Functional Description on page 4 ALTERA_CORDIC IP Core Parameters on page 7 ALTERA_CORDIC IP Core Signals on page ALTERA_CORDIC IP Core Features Supports fied-point implementations. Supports both latenc and frequenc driven IP cores. Supports both VHDL and Verilog HDL code generation. Produces full unrolled implementations. Produces faithfull rounded results to either of the two closest representable numbers in the output. 1.2 DSP IP Core Device Famil Support Intel offers the following device support levels for Intel FPGA IP cores: Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cclone, Enpirion, MAX, Nios, Quartus and Strati words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in accordance with Intel's standard warrant, but reserves the right to make changes to an products and services at an time without notice. Intel assumes no responsibilit or liabilit arising out of the application or use of an information, product, or service described herein ecept as epressl agreed to in writing b Intel. Intel customers are advised to obtain the latest version of device specifications before reling on an published information and before placing orders for products or services. *Other names and brands ma be claimed as the propert of others. ISO 9001:2008 Registered

4 Advance support the IP core is available for simulation and compilation for this device famil. FPGA programming file (.pof) support is not available for Quartus Prime Pro Strati 10 Edition Beta software and as such IP timing closure cannot be guaranteed. Timing models include initial engineering estimates of delas based on earl post-laout information. The timing models are subject to change as silicon testing improves the correlation between the actual silicon and the timing models. You can use this IP core for sstem architecture and resource utilization studies, simulation, pinout, sstem latenc assessments, basic timing assessments (pipeline budgeting), and I/O transfer strateg (data-path width, burst depth, I/O standards tradeoffs). Preliminar support Intel verifies the IP core with preliminar timing models for this device famil. The IP core meets all functional requirements, but might still be undergoing timing analsis for the device famil. You can use it in production designs with caution. support Intelverifies the IP core with final timing models for this device famil. The IP core meets all functional and timing requirements for the device famil. You can use it in production designs. Table 1. DSP IP Core Device Famil Support Device Famil Support Arria II GX Arria II GZ Arria V Intel Arria 10 Cclone IV Cclone V Intel MAX 10 FPGA Strati IV GT Strati IV GX/E Strati V Intel Strati 10 Other device families Advance No support 1.3 ALTERA_CORDIC IP Core Functional Description SinCos Function on page 5 Computes the sine and cosine of angle a. Atan2 Function on page 5 Computes the function atan2(, ) from s and. Vector Translate Function on page 6 The vector translate function is an etension of the atan2 function. It outputs the magnitude of the vector and the angle a=atan2(,). Vector Rotate Function on page 6 The vector rotate function takes a vector v= (,) T given b the two coordinates and and an angle a. The function produces a similarit rotation of vector v b the angle a to produce the vector v0=(0,0) T. 4

5 1.3.1 SinCos Function Computes the sine and cosine of angle a. Figure 1. SinCos Function unit circle cos(a) a 0 sin(a) Atan2 Function The function supports two configurations, depending on the sign attribute of a: If a is signed, the allowed range is [-π,+π] and the output range for the sine and cosine is [ 1,1]. If a is unsigned, the IP core restricts the to [0,+π/2] and restricts the output range to [0,1]. Computes the function atan2(, ) from s and. Figure 2. Atan2 Function a 0 If and are signed, the IP core determines the range from the fied-point formats. The output range is [-π,+π]. 5

6 1.3.3 Vector Translate Function The vector translate function is an etension of the atan2 function. It outputs the magnitude of the vector and the angle a=atan2(,). Figure 3. Vector Translate Function 0 q v r=k v The function takes s and and outputs a=atan2(, ) and M = K( ) 0.5. M is the magnitude of the vector v=(,) T, scaled b a CORDIC specific constant that converges to , which is transcendental, hence has no fied value. The functions supports two configurations, depending on the sign attribute of and : If the s are signed, the formats give the allowed range. In this configuration the output range for a is [ π,+π]. The output range for M depends on the range of and, according with the magnitude formula. If the s are unsigned, the IP core restricts the output value for a [0,+π/2]. The magnitude value still depends on the formula Vector Rotate Function The vector rotate function takes a vector v= (,) T given b the two coordinates and and an angle a. The function produces a similarit rotation of vector v b the angle a to produce the vector v0=(0,0) T. Figure 4. Vector Rotate Function 0 v0 =K v 0 v0 0 v a 6

7 The rotation is a similarit rotation because the magnitude of the produced vector v0 is scaled up b the CORDIC specific constant K( ). The equations of the coordinates for vector v0 are: 0 = K(cos(a) sin(a)) 0 = K(sin(a)+ cos(a)) If ou set the sign attribute to true for the, s for the function, the IP core restricts their range to [ 1,1]. You provide the number of fractional bits. The angle a is allowed in the range [ π,+π], and has the same number of fractional bits as the other s. You provide the output fractional bits and the total width of the output is w=wf+3, signed. For unsigned s,, the IP core restricts the range to [0,1], the angle a to [0,π]. 1.4 ALTERA_CORDIC IP Core Parameters Table 2. SinCos Parameters Input data widths Fraction F 1 to 64 Number of fraction bits. Width w Derived Width of fied-point data. Sign signed or unsigned The sign of the fied-point data. Output data widths Fraction 1 to 64, where F OUT F IN Number of fraction bits. Width Derived Width of fied-point data. Sign Derived The sign of the fied-point data. Generate enable port On or off Turn on for enable signal. Table 3. Atan2 Parameters Input data widths Fraction 1 to 64 Number of fraction bits. Width 3 to 64 Width of fied-point data. Sign signed or unsigned The sign of the fied-point data. Output data widths Fraction Number of fraction bits. Width Derived Width of fied-point data. Sign Derived The sign of the fied-point data. continued... 7

8 Generate enable port LUT Size Optimization Manuall Specif LUT Size On or off Turn on for enable signal. Turn on to move some of the tpical CORDIC operations into look up tables to reduce implementation cost. Turn on to the LUT size. Larger values (9-11) enable mapping some computations to memor blocks Onl when LUT Size Optimization is on.. Table 4. Vector Translate Parameters Input data widths Fraction 1 to 64 Number of fraction bits. Width Sign Signed: 4 to 64; unsigned: F to 65 signed or unsigned Width of fied-point data. The sign of the fied-point data Output data widths Fraction 1 to 64 Number of fraction bits. Width Derived Width of fied-point data. Sgn Derived The sign of the fied-point data Generate enable port Scale factor compensation On or off On or off Turn on for enable signal. For vector translate, a CORDIC specific constant that converges to scales the magnitude of the vector ( ) 0.5 so that the value for the magnitude, M, is M = K( ) 0.5. The format of the output depends on the format. The largest output value occurs when both the s are equal to the maimum representable value, j. In this contet: M = K(j 2 +j 2 ) 0.5 = K(2j 2 ) 0.5 = K2 0.5 (j 2 ) 0.5 =K j ~2.32j Therefore, two etra bits left of the MSB of j are required to ensure M is representable. If scale factor compensation is selected, M becomes: M = j 0.5 ~ 1.41 j One etra bit is sufficient for representing the range of M. Scale factor compensation affects the total width of the output. Table 5. Vector Rotate Parameters Input data widths X,Y s Fraction 1 to 64 Number of fraction bits. Width Derived Width of fied-point data. Sign signed or unsigned The sign of the fied-point data. continued... 8

9 Angle Fraction Derived - Width Derived - Sign Derived - Output data widths Fraction 1 to 64 Number of fraction bits. Width Derived Width of fied-point data. Sign Derived The sign of the fied-point data Generate enable port Scale factor compensation On or off Turn on for enable signal. Turn on to compensate the CORDIC-specific constant on the magnitude output. For both signed and unsigned s, turning on decreases b 1 the weight of the magnitude for 0 and 0. The outputs belong to the interval [-2 0.5, ]K. Under default settings, the output interval will therefore be [ K, K] (with K~ ), or ~[-2.32, +2.32]. Representing the values in this interval requires 3 bits left of the binar point, one of which is for the sign. When ou turn on Scale factor compensation, the output interval becomes [-2 0.5, ] or ~[-1.41, 1.41], which requires two bits left of the binar point, one of which is for the sign. Scale factor compensation affects the total width of the output. 1.5 ALTERA_CORDIC IP Core Signals Table 6. Common Signals Name Tpe Description clk Input Clock. en Input Enable. Onl available when ou turn on Generate an enable port. areset Input Reset. Table 7. Sin Cos Function Signals Name Tpe Configura tion a Input Signed s, c Output Signed Range [ π,+π] [0,+π/2] [ 1,1] Description Specifies the number of fractional bits (F IN ). The total width of this is F IN +3.Two etra bits are for the range (representing π) and one bit for the sign. Provide the in two s complement form. Specifies the number of fractional bits (F IN ). The total width of this is w IN =F IN +1. The one etra bit accounts for the range (required to represent π/2). Computes sin(a) and cos(a) on a user-specified output fraction width(f). The output has width w OUT = F OUT +2 and is signed. [0,1] Computes sin(a) and cos(a) on a user-specified output fraction width(f OUT ). The output has the width w OUT = F OUT +1 and is unsigned. 9

10 Table 8. Atan2 Function Signals Name Tpe Configura tion, Input Signed a Ouput Signed Range Given b w, F [ π,+π] [0,+π/2] Details Specifies the total width (w) and number fractional bits (F) of the. Provide the s in two s complement form. Specifies the total width (w) and number fractional bits (F) of the. Computes atan2(,) on a user-specified output fraction width (F). The output has the width w OUT = F OUT +2 and is signed. Computes atan2(,) on output fraction width (F OUT ). The output format has the width w OUT = F OUT +2 and is signed. However, the output value is unsigned. Table 9. Vector Translate Functions Signals Name Direction Configura tion, Input Signed Range Given b w, F Details Specifies the total width (w) and number fractional bits (F) of the. Provide the s in two s complement form. q Output [ π,+π] Computes atan2(,) on a user-specified output fraction width F q. The output has the width w q =F q +3 and is signed. r, Input Given b w, F Given b w,f Computes K( ) 0.5. The total width of the output is w r =F q +3, or w r =F q +2 with scale factor compensation. The number of meaningful bits depends on the number of iterations which depends on F q. The format of the output depends on the format. MSB(M OUT )=MSB IN +2, or MSB(M OUT )=MSB IN +1 with scale factor compensation Specifies the total width (w) and number fractional bits (F) of the. q Output [0,+π/2] Computes atan2(,) on an output fraction width F q. The output has the width w q =F q +2 and is signed. r Given b w,f Computes K( ) 0.5. The total width of the output is w r =F q +3, or w r =F q +2 with scale factor compensation. MSB(M OUT )=MSB IN +2, or MSB(M OUT )=MSB IN +1 with scale factor compensation. Table 10. Vector Rotate Function Signals Name Direction Configura tion, Input Signed Range [ 1,1] Details Specifies the fraction width (F), total number of bits is w = F+2. Provide the s in two s complement form. [0,1] Specifies the fraction width (F), total number of bits is w = F+1. a Input Signed [ π,+π] Number of fractional bits is F (provided previousl for and ), total width is w a = F+3. continued... 10

11 Name Direction Configura tion 0, 0 Output Signed Range [0,+π] [ 2 0.5, ]K Details Number of fractional bits is F (provided previousl for and ), total width is w a = F+2. Number of fractional bits F OUT, where w OUT = F OUT +3 or w OUT = F OUT +2 with scale factor reduction. 11

Intel Arria 10 Native Floating- Point DSP Intel FPGA IP User Guide

Intel Arria 10 Native Floating- Point DSP Intel FPGA IP User Guide Subscribe Send Feedback Latest document on the web: PDF HTML Contents Contents 1...3 1.1 Parameterizing the Intel Arria 10 Native Floating-Point