Rndxxxxx - Ladder Diagram Page 1

Transcription

1 Rndxxxxx - Ladder Diagram Page 1 1/2/212 7:5:55 PM The following random generator is adaptation for RSLogix5K of C# code: (by John D. Cook). Workaround for signed 32-bit integers DINT, C# code uses unsigned 32-bit integers. The precision of REAL data-types is reduced. Is Importable/Exportable Routine.Called by JSR from Continous Main Task. Generates random values between ]; 1[, takes 32 scans to generate a random value. It seeds itself, although option with controller's clock is possible. Has not been statistically tested. S:FS Copyright (C) 211 Peter Tiagunov peter.tiagunov@leanmes.net This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version 3 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. //You should have received a copy of the GNU General Public License along with this program. If not, see < Set Values on First Scan: nrndxxxxx_m_w= ; nrndxxxxx_m_z= ; irndxxxxx_ecoeff= e-1 (rounded e-1) brndxxxxx_false= ; Source irndxxxxx_ Source nrndxxxxx_m_w Source nrndxxxxx_m_z Source e-1?? frndxxxxx_ecoeff. brndxxxxx_false U 1 Equal Source A. Initialize Random Generator. Source irndxxxxx_shift Source nrndxxxxx_m_w narndxxxxx_m_w[] Source nrndxxxxx_m_z narndxxxxx_m_z[] irndxxxxx_ RSLogix 5

2 Rndxxxxx - Ladder Diagram Page 2 1/2/212 7:5:55 PM 2 Equal 1. GetUnit(), Do Right Shift. (narndxxxxx_m_w[] >> 16); (narndxxxxx_m_z[] >> 16); Shift entire 32 bits in 2 Elements to the RIGHT by 16 bits (total 16 scans, 1 bit shift per scan) ctrlrndxxxxx_zshift. LIM BSR / Limit Test (CIRC) Bit Shift Right Low Limit Array narndxxxxx_m_w[] Control ctrlrndxxxxx_wshift Source Bit brndxxxxx_false Length 32 Test irndxxxxx_shift High Limit 15 BSR Bit Shift Right Array narndxxxxx_m_z[] Control ctrlrndxxxxx_zshift Source Bit brndxxxxx_false Length 32 Source A irndxxxxx_shift Source B 1 irndxxxxx_shift 1. GetUnit(), Right Shift Complete. narndxxxxx_m_w[1] = nrndxxxxx_m_w & 65535; narndxxxxx_m_z[1] = nrndxxxxx_m_z & 65535; nrndxxxxx_m_w = 18*naRndxxxxx_m_w[1]+naRndxxxxx_m_w[]; nrndxxxxx_m_z = 36969*naRndxxxxx_m_z[1]+naRndxxxxx_m_z[]; narndxxxxx_m_z[]=nrndxxxxx_m_z; AND 3 Equal Equal Bitwise AND Source A irndxxxxx_shift Source A nrndxxxxx_m_w Source B 16 Source B narndxxxxx_m_w[1] AND Bitwise AND Source A nrndxxxxx_m_z Source B narndxxxxx_m_z[1] nrndxxxxx_m_w Expression 18*naRndxxxxx_m_w[1]+naRndxxxxx_m_w[] nrndxxxxx_m_z Expression 36969*naRndxxxxx_m_z[1]+naRndxxxxx_m_z[] Source nrndxxxxx_m_z narndxxxxx_m_z[] Source irndxxxxx_shift irndxxxxx_ RSLogix 5

3 Rndxxxxx - Ladder Diagram Page 3 1/2/212 7:5:55 PM 4 Equal Source A 2 2. Do Left Shift. narndxxxxx_m_z[] << 16; irndxxxxx_shiftleft++1; Shift entire 32 bits in narndxxxxx_m_z[] to the LEFT by 16 bits (total 16 scans, 1 bit shift per scan) ctrlrndxxxxx_zshift. LIM BSL / Limit Test (CIRC) Bit Shift Left Low Limit Array narndxxxxx_m_z[] Control ctrlrndxxxxx_zshift Source Bit brndxxxxx_false Length 32 Test irndxxxxx_shift High Limit 15 Source B irndxxxxx_shift irndxxxxx_shift 5 Equal Source A 2 2.Left Shift Complete. Goto Next. Equal Source A irndxxxxx_shift Source B 16 irndxxxxx_ 3. GetUniform(). Random. Temporary Random frndxxxxx_temp, Compensate for negative, result of unsigned data types being not available in RSLogix5K 6 Equal Source A 3 frndxxxxx_temp. Expression (narndxxxxx_m_z[]+nrndxxxxx_m_w+1.)*frndxxxxx_ecoeff LES Less Than (A<B) Source A frndxxxxx_temp. Source B frndxxxxx. Expression 1.+fRndxxxxx_Temp GRT Greater Than (A>B) Source A frndxxxxx_temp. Source B Source frndxxxxx_temp. frndxxxxx. irndxxxxx_ 7 Equal Source A 4 4. Delayed Call for Next Random. tmrrndxxxxx. TON Timer On Delay Timer tmrrndxxxxx Preset 1 Accum tmrrndxxxxx RES Source irndxxxxx_ RSLogix 5

4 Rndxxxxx - Ladder Diagram Page 4 1/2/212 7:5:55 PM (End) RSLogix 5

5 Rndxxxxx - Routine Tag Listing Page 5 1/2/212 7:5:55 PM Name Value Data Type Scope brndxxxxx_false BOOL MainProgram brndxxxxx_false - MainProgram/Rndxxxxx - *(OTU), 2(BSR), 4(BSL) ctrlrndxxxxx_wshift CONTROL MainProgram ctrlrndxxxxx_wshift - MainProgram/Rndxxxxx - *2(BSR) ctrlrndxxxxx_zshift CONTROL MainProgram ctrlrndxxxxx_zshift - MainProgram/Rndxxxxx - *2(BSR), *4(BSL) ctrlrndxxxxx_zshift. BOOL ctrlrndxxxxx_zshift. - MainProgram/Rndxxxxx - 2(XIO), 4(XIO) frndxxxxx. REAL MainProgram frndxxxxx - MainProgram/Rndxxxxx - *6(), *6() frndxxxxx_ecoeff. REAL MainProgram frndxxxxx_ecoeff - MainProgram/Rndxxxxx - *(), 6() frndxxxxx_temp. REAL MainProgram frndxxxxx_temp - MainProgram/Rndxxxxx - *6(), 6(), 6(GRT), 6(LES), 6() irndxxxxx_shift INT MainProgram irndxxxxx_shift - MainProgram/Rndxxxxx - *1(), *2(), *3(), *4(), 2(), 2(LIM), 3(), 4(), 4(LIM), 5() irndxxxxx_ INT MainProgram irndxxxxx_ - MainProgram/Rndxxxxx - *(), *1(), *3(), *5(), *6(), *7(), 1(), 1(), 2(), 3(), 3(), 4(), 5(), 5(), 6(), 6(), 7() narndxxxxx_m_w DINT[2] MainProgram narndxxxxx_m_w - MainProgram/Rndxxxxx - *2(BSR) narndxxxxx_m_w[] DINT narndxxxxx_m_w[] - MainProgram/Rndxxxxx - *1(), 3() narndxxxxx_m_w[1] DINT narndxxxxx_m_w[1] - MainProgram/Rndxxxxx - *3(AND), 3() narndxxxxx_m_z DINT[2] MainProgram narndxxxxx_m_z - MainProgram/Rndxxxxx - *2(BSR), *4(BSL) narndxxxxx_m_z[] DINT narndxxxxx_m_z[] - MainProgram/Rndxxxxx - *1(), *3(), 3(), 6() RSLogix 5

6 Rndxxxxx - Routine Tag Listing Page 6 1/2/212 7:5:55 PM narndxxxxx_m_z (Continued) narndxxxxx_m_z[1] DINT narndxxxxx_m_z[1] - MainProgram/Rndxxxxx - *3(AND), 3() nrndxxxxx_m_w DINT MainProgram nrndxxxxx_m_w - MainProgram/Rndxxxxx - *(), *3(), 1(), 3(AND), 6() nrndxxxxx_m_z DINT MainProgram nrndxxxxx_m_z - MainProgram/Rndxxxxx - *(), *3(), 1(), 3(AND), 3() tmrrndxxxxx TIMER MainProgram tmrrndxxxxx - MainProgram/Rndxxxxx - *7(RES), *7(TON) tmrrndxxxxx. BOOL tmrrndxxxxx. - MainProgram/Rndxxxxx - 7(XIC) RSLogix 5