Table of Contents. Chapter Description Page. 1. PLC Fundamentals Ladder Logic

Transcription

1 vii Table of Contents Chapter Description Page 1. PLC Fundamentals Ladder Logic Schematic Drawing Hardwired System PLC System Major Components Chassis Power Supply CPU Memory a- ROM b- RAM I/O Processor I/O a- Discrete I/O b- Analog I/O Programming PLC System General Block Diagrams Processor Power Supply Chassis/Rack I/O System a- Local I/O b- Remote I/O General Design Considerations I/O Cards Typical AC Input Card Typical AC Output Card Processors Processor Specifications Fixed Controller Processor Diagnostic LED s Specifications I/O Point Configuration I/O Point Configuration I/O Point Configuration Modular Controllers SLC-5/ a- Specifications b- Processor Diagnostic LED s SLC-5/ Copyright Intertech, Inc., All Rights Reserved

2 viii a- Specifications b- Processor Diagnosic LED s SLC-5/ a- Specifications b- Processor Diagnosic LED s SLC-5/ a- Specifications b- Processor Diagnostic LED s SLC-5/ a- Specifications b- Processor Diagnostic LED s c- Custom Web Pages Power Supplies P1 Power Supply P2 Power Supply P3 Power Supply P4 Power Supply P5 Power Supply P6 Power Supply P7 Power Supply I/O Chassis Slot 1746-A Slot 1746-A Slot 1746-A Slot 1746-A Slot 1746-A Expansion Chassis Modules Discrete Input and Output Modules AC Output AC Input DC Output DC Input AC/DC Input Relay Output Combination Input/Output Analog Analog Inputs Analog Outputs Combination Analog Input/Output Modules Thermocouple/mV 1746-NT RTD/Resistance Specialty Copyright Intertech, Inc., All Rights Reserved viii

3 ix High Speed Counter Encoder Stepper Controller Servo Positioning Basic Module Communication SN Remote I/O Scanner a- LED Indicators b- DIP Switches c- Configuration - G File d- Control/Status - M Files ASB Remote I/O Adapter a- LED Indicators b- Dip Switches AIC Isolated Link Coupler DSN Distributed I/O Scanner PIC Personal Interface Converter DCM Direct Communication Module KE DH-485/RS232C Interface Module Specialty Module to AIC Cable Processor Memory Data Table Files Default Files a- File Type Descriptions Unassigned Prefixes a- File Type Descriptions Unassigned File Numbers Memory Optimization Global vs Local File Types Program Files Default Files a- File 0 System File b- File 1 System File c- File 2 Ladder Unassigned File Numbers Fault Routine Selectable Timed Interrupt (STI) Discrete Input Interrupt (DII) I/O Event Interrupt Special Files G Configuration Files M Data Files I/O Addressing and Concepts Data Table Addressing I/O Addressing a- Bit b- Word Number c- Slot Number Timer, Counter etc Addressing Indirect Addressing Copyright Intertech, Inc., All Rights Reserved

4 x 7.3 Indexed Addressing Symbolic Addressing System Design and Operation SLC-500 Scan Structure System Design Considerations Rules Of Chassis Layout a- Fixed Controller Expansion Chassis Module Combinations I/O Layout Local I/O Expansion I/O Remote I/O a- Remote I/O Communication Cabling b- Terminating Resistors DeviceNet I/O Power Supply Selection Power Distribution & E-Stop Forcing Visible Indications Software Indications Communications Data Highway DH Features Specifications RS-232-D Specifications Protocols a- DF1-Full Duplex b- DF1 Half-Duplex Slave c- ASCII Data Highway Plus (DH+) Daisy Chain Trunk-Line Strategy For Highway Implementation a- File Structures Ethernet SLC-500 Instruction Set Basic Logic Rules Rung Editing Off-Line On-Line, PLC in Program Mode On-Line, PLC in Run Mode a- Accept b- Test c- Assemble Copyright Intertech, Inc., All Rights Reserved x

5 xi 10.3 Contacts, Coils, and Branches Examine On (XIC) Normally Open Examine Off (XIO) Normally Closed Output Energize (OTE) Coil Branching Output Latch & Unlatch One Shot Rising (OSR) Reset Coil (RES) Timers Timer On Delay, (TON) Timer Off Delay (TOF) Retentive Timer On Delay (RTO) Counters Count Up Counter (CTU) Count Down Counter (CTD) Comparison Instructions Equal (EQU) Not Equal (NEQ) Greater Than (GRT) Greater Than or Equal (GEQ) Less Than (LES) Less Than or Equal (LEQ) Limit Test (LIM) Computational Instructions Add (ADD) Subtract (SUB) Multiply (MUL) Divide (DIV) Move (MOV) Square Root (SQR) Clear (CLR) Compute (CPT) Scale with Parameters (SCP) Scale Data (SCL) Exponential (XPY) Logarithm (LOG) Natural Logarithm (LN) Sine (SIN) Cosine (COS) Tangent (TAN) Arc Sine (ASN) Arc Cosine (ACS) Arc Tangent (ATN) Data Conversion Instructions Binary to BCD (TOD) BCD to Binary (FRD) Copyright Intertech, Inc., All Rights Reserved

6 xii 10.9 File Logic and Manipulation Instructions Fill File(FLL) Copy File(COP) First In-First Out (FFL & FFU) Last In-First Out (LFL & LFU) Sequencer Instructions (SQL, SQC, SQO) a- Sequencer Load (SQL) b- Sequencer Compare (SQC) c- Sequencer Output (SQO) Bit Logic and Manipulation Instructions Bitwise And (AND) Masked Move (MVM) Masked Equal (MEQ) Bitwise Inclusive OR (OR) Bitwise Exclusive Or (XOR) Not (NOT) Bit Shift Left (BSL) Bit Shift Right (BSR) Program Control Instructions Jump And Label (JMP & LBL) a- Jump (JMP) b- Label (LBL) Jump To Subroutine Functions - JSR, SBR, RET a- Jump to Subroutine (JSR) b- Subroutine (SBR) c- Return (RET) Master Control Reset - MCR Process Control Instructions PID a- Control Block Integer (N) Word Assignments b- SLC-500 PID Functions c- The PID Equation d- Computers Don't Do Calculus ASCII Instructions Copyright Intertech, Inc., All Rights Reserved xii

7 Table of Figures Table of Contents xiii Figure Description Page FIGURE 1-1 REAL-WORLD TO LOGIC EXAMPLE FIGURE 1-2 CIRCUIT EXAMPLE LOGIC FIGURE 1-3 CIRCUIT EXAMPLE LADDER LOGIC FIGURE 1-4 MAJOR PLC COMPONENTS FIGURE 1-5 PLC SYSTEM BLOCK DIAGRAM FIGURE 1-6 DAISY CHAINED IO FIGURE 1-7 STAR IO SYSTEM FIGURE 1-8 RACK BLOCK DIAGRAM FIGURE 1-9 CARD WIRING 8 POINT IO FOR 120 VAC FIGURE 1-10 INPUT CARD AC INTERNAL CIRCUIT FIGURE 1-11 OUTPUT CARD AC INTERNAL CIRCUIT FIGURE 2-1 SLC PROCESSORS FIGURE 2-2 SLC FIXED PROCESSOR FIGURE 2-3 SLC PROCESSOR FIGURE 2-4 SLC PROCESSOR FIGURE 2-5 SLC PROCESSOR FIGURE 2-6 SLC PROCESSOR FIGURE 2-7 SLC PROCESSOR FIGURE 3-1 POWER SUPPLY 1746-P FIGURE 3-2 POWER SUPPLY 1746-P FIGURE 3-3 POWER SUPPLY 1746-P FIGURE 3-4 POWER SUPPLY 1746-P FIGURE 3-5 POWER SUPPLY 1746-P FIGURE 3-6 POWER SUPPLY 1746-P FIGURE 3-7 POWER SUPPLY 1746-P FIGURE 4-1 CHASSIS 2 SLOT FIGURE 4-2 MODULE TABLE FIGURE 4-3 CHASSIS 4 SLOT FIGURE 4-4 CHASSIS 7 SLOT FIGURE 4-5 CHASSIS 10 SLOT FIGURE 4-6 CHASSIS 13 SLOT FIGURE 4-7 SLC EXPANSION CHASSIS FIGURE 5-1 SLC MODULES FIGURE 5-2 SLC DISCRETE MODULES FIGURE 5-3 SLC ANALOG MODULE FIGURE 5-4 RIO SCANNER 1741-SN FIGURE 5-5 REMOTE IO ADAPTER 1747-ASB FIGURE 5-6 REMOTE IO MODULE.DSF FIGURE 5-7 LINK COUPLER FIGURE 5-8 DISTRIBUTED IO SCANNER FIGURE 6-1 SCREEN OF A.I SOFTWARE PLC-500 DEFAULT DATA TABLE FIGURE 6-2 SCREEN OF RS LOGIX SOFTWARE RS LOGIX DEFAULT DATA TABLE FIGURE 6-3 A.I. SCREEN OF PROGRAM FILES PLC-500 DEFAULT PROGRAM FILES FIGURE 6-4 RSLOGIX 500 SCREEN OF PROGRAM FILES RS LOGIX DEFAULT PROGRAM FILES FIGURE 7-1 SLC500 RACK AND CARDS AND POWER SUPPLY FIGURE 7-2 ADDRESS STATEMENT LAYOUT FIGURE 7-3 INPUT/OUTPUT ADDRESS EXAMPLE FIGURE IB16 INPUT MODULE FIGURE 7-5 INPUT ADDRESS EXAMPLE FIGURE 7-6 SLC500 RACK AND CARDS AND POWER SUPPLY FIGURE 7-7 NON-DISCRETE ADDRESS STATEMENT FIGURE 7-8 NON-DISCRETE ADDRESS STATEMENT FIGURE 7-9 INDIRECT ADDRESS EXAMPLE Copyright Intertech, Inc., All Rights Reserved

8 xiv FIGURE 7-10 INDEXED ADDRESS EXAMPLE FIGURE 8-1 CLASSIC PROCESSOR SCAN FUNCTION DIAGRAM FIGURE 8-2 CHASSIS 2 SLOT MODULE TABLE FIGURE 8-3 SLC500 RACK AND CARDS AND POWER SUPPLY FIGURE 8-4 SLC EXPANSION CHASSIS FIGURE 8-5 REMOTE IO LAYOUT FIGURE 8-6 REMOTE IO CONNECTOR WIRING FIGURE 8-7 SLC500 RACK AND CARDS AND POWER SUPPLY FIGURE 8-8 CONTROL ROOM POWER DISTRIBUTION FIGURE 8-9 OUTPUT FORCE FILE FIGURE 9-1 DATA HIGHWAY PLUS DAISY CHAIN FIGURE 9-1 DATA HIGHWAY PLUS TRUNK LINE FIGURE 9-2 DATA HIGHWAY PLUS TAP WIRING.DSF FIGURE 10-1 LADDER LOGIC NESTING - BRANCHING EXAMPLE FIGURE 10-2 NORMALLY OPEN CONTACT DESCRIPTION FIGURE 10-3 NORMALLY CLOSED CONTACT DESCRIPTION FIGURE 10-4 OUTPUT ENERGIZE COIL DESCRIPTION FIGURE 10-5 LADDER LOGIC NESTING - BRANCHING EXAMPLE FIGURE 10-6 LADDER LOGIC NESTING - BRANCHING EXAMPLE FIGURE 10-7 LADDER LOGIC OUTPUT LATCH/UNLATCH FIGURE 10-8 ONE SHOT CONTACT DESCRIPTION FIGURE 10-9 LADDER LOGIC OSR TIMING EXAMPLE FIGURE SEAL IN CIRCUIT FOR OSR EXAMPLE FIGURE ONE SHOT CONTACT DESCRIPTION FIGURE GENERIC TIMER FUNCTION BLOCK FIGURE TIMER ON DELAY FUNCTION BLOCK FIGURE TIMER ON DELAY EXAMPLE FIGURE TIMER OFF DELAY FUNCTION BLOCK FIGURE TIMER OFF DELAY FIGURE RETENTIVE TIMER ON FUNCTION BLOCK FIGURE TIMER RETENTIVE ON DELAY FIGURE COUNTER FUNCTION BLOCK FIGURE COUNT UP COUNTER FUNCTION BLOCK FIGURE COUNTER UP FIGURE COUNT DOWN COUNTER FUNCTION BLOCK FIGURE COUNTER DOWN FIGURE EQUAL INSTRUCTION FIGURE EQUAL INSTRUCTION EXAMPLE FIGURE NOT EQUAL INSTRUCTION FIGURE NOT EQUAL INSTRUCTION EXAMPLE FIGURE GREATER THAN INSTRUCTION FIGURE GREATER THAN INSTRUCTION EXAMPLE FIGURE GREATER THAN OR EQUAL INSTRUCTION FIGURE GREATER THAN OR EQUAL INSTRUCTION EXAMPLE FIGURE LESS THAN INSTRUCTION FIGURE LESS THAN INSTRUCTION EXAMPLE FIGURE LESS THAN OR EQUAL INSTRUCTION FIGURE LESS THAN OR EQUAL INSTRUCTION EXAMPLE FIGURE LIMIT TEST INSTRUCTION FIGURE LIMIT TEST INSTRUCTION EXAMPLE FIGURE ADD INSTRUCTION FIGURE ADD INSTRUCTION EXAMPLE FIGURE SUBTRACT INSTRUCTION FIGURE SUBTRACT INSTRUCTION EXAMPLE FIGURE MULTIPLY INSTRUCTION FIGURE MULTIPLY INSTRUCTION EXAMPLE FIGURE DIVIDE INSTRUCTION FIGURE DIVIDE INSTRUCTION EXAMPLE Copyright Intertech, Inc., All Rights Reserved xiv

9 xv FIGURE MOVE INSTRUCTION FIGURE MOVE INSTRUCTION EXAMPLE FIGURE SQUARE ROOT INSTRUCTION FIGURE CLEAR INSTRUCTION FIGURE CLEAR INSTRUCTION EXAMPLE FIGURE COMPUTE INSTRUCTION FIGURE COMPUTE INSTRUCTION EXAMPLE FIGURE SCP INSTRUCTION.DSF FIGURE SCP INSTRUCTION EXAMPLE.DSF FIGURE SCL INSTRUCTION.DSF FIGURE SCL INSTRUCTION EXAMPLE.DSF FIGURE BINARY TO BCD INSTRUCTION FIGURE BCD TO BINARY INSTRUCTION FIGURE FILL FILE INSTRUCTION FIGURE FILE FILL INSTRUCTION EXAMPLE FIGURE COPY FILE INSTRUCTION FIGURE FILE COPY INSTRUCTION EXAMPLE FIGURE FIRST IN FIRST OUT LOAD UNLOAD INSTRUCTIONS FIGURE FIRST IN FIRST OUT INSTRUCTION EXAMPLE FIGURE LAST IN FIRST OUT LOAD UNLOAD INSTRUCTIONS FIGURE LAST IN FIRST OUT INSTRUCTION EXAMPLE FIGURE SEQUENCER COMPARE INSTRUCTION FIGURE SEQUENCER LOAD INSTRUCTION FIGURE SEQUENCER OUTPUT INSTRUCTION FIGURE SEQUENCER LOAD INSTRUCTION FIGURE SEQUENCER LOAD INSTRUCTION EXAMPLE.DSF FIGURE SEQUENCER COMPARE INSTRUCTION FIGURE SEQUENCER LOAD INSTRUCTION EXAMPLE.DSF FIGURE SEQUENCER OUTPUT INSTRUCTION FIGURE SEQUENCER LOAD INSTRUCTION EXAMPLE.DSF FIGURE BITWISE AND INSTRUCTION.DSF FIGURE AND INSTRUCTION FIGURE MASKED MOVE INSTRUCTION.DSF FIGURE MASKED MOVE INSTRUCTION EXAMPLE.DSF FIGURE MASKED EQUAL INSTRUCTION.DSF FIGURE MASK EQUAL INSTRUCTION.DSF FIGURE BITWISE AND INSTRUCTION.DSF FIGURE OR INSTRUCTION.DSF FIGURE BITWISE AND INSTRUCTION.DSF FIGURE OR EXCLUSIVE INSTRUCTION.DSF FIGURE NOT INSTRUCTION FIGURE NOT INSTRUCTION EXAMPLE.DSF FIGURE BIT SHIFT LEFT INSTRUCTION FIGURE BIT SHIFT LEFT INSTRUCTION EXAMPLE.DSF FIGURE BIT SHIFT RIGHT INSTRUCTION FIGURE BIT SHIFT LEFT INSTRUCTION EXAMPLE.DSF FIGURE RESET COIL.DSF FIGURE JUMP INSTRUCTION FIGURE ONE SHOT CONTACT DESCRIPTION.DSF FIGURE LABEL INSTRUCTION FIGURE MOVE INSTRUCTION.DSF FIGURE JUMP TO SUBROUTINE INSTRUCTION.DSF FIGURE SUBROUTINE INSTRUCTION.DSF FIGURE SUBROUTINE INSTRUCTION FIGURE RETURN INSTRUCTION.DSF FIGURE RETURN INSTRUCTION FIGURE MCR INSTRUCTION.DSF FIGURE MASTER CONTROL RESET INSTRUCTION FIGURE PID INSTRUCTION Copyright Intertech, Inc., All Rights Reserved

10 xvi FIGURE PID INSTRUCTION EXAMPLE FIGURE CONVEYOR PID EXAMPLE FIGURE CONVEYOR PID - ISA LOOP DIAGRAM Copyright Intertech, Inc., All Rights Reserved xvi