Shift Register Instructions/The Force Function

Transcription

1 Exercise 9 Shift Register Instructions/The Force Function EXERCISE OBJECTIVE To program and test PLC ladder programs that use shift register instructions. To become familiar with the Force function of the PLC. DISCUSSION Shift register instructions are PLC output instructions that are used to load data into a bit array, one bit at a time. The data is shifted through the bit array, and then unloaded from the bit array one bit at a time. Shift register instructions are useful in conveyor applications and product evaluation (pass/fail) control. The PLC on your trainer includes the following shift register instructions: the bit shift left (BSL) instruction and the bit shift right (BSR) instruction. To enter a BSL or BSR instruction, the following parameters must be programmed: File: address of the bit array through which the bits are shifted. The array must start at the first bit position of a 16-bit element (element 1, 2, 3, etc.) in a binary (B) data file. Control: 3-word register (R data file) that stores the status bits of the BSL or BSR instruction and the length of the bit array, as shown in Table 9-1. Word B 15 B 14 B 13 B 12 B 11 B 10 B 9 B 8 B 7 B 6 B 5 B 4 B 3 B 2 B 1 B 0 0 EN DN ER UL 1 Length (size) of the bit array 2 Reserved Table 9-1. R data file structure. Bit Address: location of the source bit that is inserted into the array. With a BSL instruction, this bit is inserted into the first (lowest) bit position of the array. With a BSR instruction, this bit is inserted into the last (highest) bit position of the array. Length: total number of bits to be shifted within the bit array. Status bits (word 0 of the control data file) The status bits of a BSL or BSR instruction provide information on the bit shifting process. They can be used in a ladder program to control relay-type instructions. 9-1

2 Enable [EN] (bit number 15 of word 0): The EN bit is set to logic state 1 when the rung containing the BSL or BSR instruction is true, indicating that this instruction is true. It is set to logic state 0 when the rung is false. Done [DN] (bit number 13 of word 0): The DN bit is set to logic state 1 when the bits in the bit array have been shifted by one position. Error [ER] (bit number 11 of word 0): The ER bit is set to logic state 1 when an error is detected, such as when a negative number has been entered for the length of the BSL or BSR instruction. Unload [UL] (bit number 10 of word 0): With the BSL instruction, this bit stores the logic state of the bit shifted out of the last bit position of the bit array. With the BSR instruction, this bit stores the logic state of the bit shifted out of the first bit position of the array. Operation of the BSL Instruction Figure 9-1 shows how a BSL instruction works. In this example: the File address is set to B3:1. Consequently, the bit array starts at the first bit position of element 1 of data file B3, that is, at bit position 16 of this file. the Length is set to 35. Consequently, the array ends at bit position 50 of data file B3. the Control address is set to R6:0. Consequently, the unload (UL) bit is stored at address R6:0/10. the Bit Address is set to I:0/0. Consequently, the source bit is located at this address. When the rung containing the BSL instruction becomes true, the 35 bits contained in the bit array are shifted one bit position higher. The source bit at address I:0/0 is inserted into the first bit position of the array (bit position 16). The bit in the last bit position of the array (bit position 50) is shifted out of the array and stored into the unload (UL) bit position, that is, at address R6:0/

3 Figure 9-1. Operation of the BSL instruction. Operation of the BSR Instruction Figure 9-2 shows how a BSR instruction works. In this example: the File address is set to B3:2. Consequently, the bit array starts at the first bit position of element 2 of data file B3, that is, at bit position 32 of this file. the Length is set to 38. Consequently, the array ends at bit position 69 of data file B3. the Control address is set to R6:0. Consequently, the unload (UL) bit is stored at address R6:0/10. the Bit Address is set to I:0/6. Consequently, the source bit is located at this address. When the rung containing the BSR instruction becomes true, the 38 bits contained in the bit array are shifted one bit position lower. The source bit at address I:0/6 is inserted into the last bit position of the array (bit position 69). The bit in the first position of the array (bit position 32) is shifted out of the array and stored into the unload (UL) bit position, that is, at address R6:0/

4 Figure 9-2. Operation of the BSR instruction. The Force Function The PLC on your trainer has a Force function that can be used while the PLC is in the Run mode to override the current status of PLC inputs or outputs, regardless of their actual status. This function can be useful in start-up and troubleshooting procedures. Forcing Input Data File Bits This consists in forcing the input data file bit associated with a PLC input to logic state 0 or 1. If, for example, the input data file bit associated with PLC input 0 is forced to logic state 1, the ladder program will be executed with this forced state regardless of whether PLC input 0 is activated or deactivated. Installing a force on an input data file bit will affect the input force table, input data file, and the program logic. Note that the Force function can also be used to force input data file bits while the PLC is in the Test mode. Forcing Output Interface Circuitry This consists in forcing the PLC output interface circuitry associated with a PLC output to the energized or deenergized state. If, for example, the circuitry associated with PLC output 0 is forced to the energized state, the voltage used for powering the device connected to terminal 0 of the PLC output interface will be applied to this terminal. Installing a force on the circuitry of a PLC output affects neither the output 9-4

5 data file bit associated with this output nor the program logic. Note that the circuitry of a PLC output can only be forced while the PLC is in the Run mode, not in the Test mode. This occurs because in the Test mode, the PLC output interface circuitry is not energized. Procedure Summary In this exercise, you will program and test a ladder program that uses a bit shift left (BSL) instruction. The address of the source bit you will program for this instruction will be the address of the last bit position within the array of this instruction. This will cause the bits in the last position of the array to be shifted back into the first position of the array, thus creating a recirculating bit register. Next you will use the Force function of the PLC to override the status of PLC inputs or outputs. Note: As earlier mentioned, the manual applies specifically to PLC Trainer Model If you are using another model, follow the exercise procedure by adapting it as described below. Model 3240-A, Model 3240-D, or Model : Same way as with Model Model : Connect an external 24-VDC source to the supply jacks intended for this purpose at the left bottom of the trainer front panel. When asked to activate a PLC input, connect the corresponding PLC input jack to the positive terminal of the 24-VDC source, using a connection lead. When asked to deactivate a PLC input, remove the lead between the corresponding PLC input jack and the 24-VDC source. To determine whether or not a PLC output is activated, observe the PLC output status indicators on the PLC module. Model 9066, connect the DC COM jacks (2) to the DC SUPPLY OUTPUT negative terminal. To activate a PLC input, connect the corresponding PLC input jack to the positive terminal of the DC SUPPLY OUTPUT. To determine whether or not a PLC output is activated, you can see it on the LCD display default page (if not on this page, press ESC and select I/O status). To act on a physical device, connect VAC/VDC jacks to the positive terminal of the DC SUPPLY OUTPUT if you are are using the two first outputs or connect DC 24 + and DC 24 V - to the corresponding terminals of the DC SUPPLY OUTPUT to use last four outputs. EQUIPMENT REQUIRED Refer to the Equipment Utilization Chart, in Appendix A of this manual, to obtain the list of equipment required to perform this exercise. PROCEDURE Setting Up the Equipment G 1. Connect the RS-232 serial port of the computer station to the communications port of the PLC on the PLC Trainer, using a 1761-CBL-PM02 cable. 9-5

6 G 2. Turn on the computer and start RSLogix Micro. Turn on the PLC Trainer. G 3. In this exercise, you will study the operation of PLC instructions through observation of the ladder program view, the data files of the processor, as well as the status of the lamps next to the PLC output jacks on the trainer front panel. Note: Since trainer models and 9066 do not have output lamps, observe the PLC output status LED's on the PLC module instead. The BSL Instruction (Recirculating Register) G 4. Create a new project having the following processor name: EXERC_9. The project tree of processor EXERC_9 and program file LAD 2 should be displayed in the RSLogix Micro window. Program file LAD 2 contains the main ladder program. The next steps of this procedure consist in entering the ladder program of Figure 9-3. Figure 9-3. The bit shift left (BSL) instruction. 9-6

7 G 5. Select the User category of instructions by clicking the corresponding instruction category selection tab. Insert a new rung into program file LAD 2. In this rung, enter instruction XIC I:0/0. Then, enter instruction BSL R6:0 by performing the following steps: Select the File Shift/Sequencer category of instructions by clicking the corresponding instruction category selection tab. Click the Bit Shift Left (BSL) button on the instruction toolbar to insert this instruction in the rung, type: B3:0, then press the mouse left button to accept this address. (The file indicator # will automatically be added to the front of this address). Double-click Control within the BSL instruction, type: R6:0, then press the mouse left button to accept this address. Double-click Bit Address within the BSL instruction, type: B3:0/15, then press the mouse left button to accept this value. Double-click Length within the BSL instruction, type: 16, then press the mouse left button to accept this value. You have now finished entering the instructions of rung 0 in the ladder program of Figure 9-3. G 6. Select the User category of instructions by clicking the corresponding instruction category selection tab. Enter a new rung into program file LAD 2. In this rung, enter instruction XIC R6:0/EN. To do so, click the Examine If Closed button on the instruction toolbar, type: R6:0/EN, then click the mouse left button to enter this address. Enter instruction OTE O:0/0. You have now finished entering the instructions of rung 1 in the ladder program of Figure 9-3. G 7. Enter a new rung into program file LAD 2. In this rung, enter instruction XIC R6:0/DN, then enter instruction OTE O:0/1. You have now finished entering the instructions of rung 2 in the ladder program of Figure 9-3. G 8. Enter a new rung into program file LAD 2. In this rung, enter instruction XIC R6:0/UL. Then, enter instruction OTE O:0/2. You have now finished entering the instructions of rung 3 in the ladder program of Figure

8 G 9. Using the Verify Rung command, verify the rungs that have been edited. Correct any errors. The main ladder program in RSLogix Micro should be identical to that shown in Figure 9-3. G 10. In the Data Files folder of processor EXERC_9, open data file B3 - BINARY. Enter 1 s at the proper bit locations of element 0 of data file B3 so that it contains the same data as Table 9-1 below. When you have finished, close data file B3. ELEMENT BINARY DATA B3: Table 9-2. Table for data file B3. G 11. Save the project in a project file named EXERC_9.RSS. G 12. Make sure the system communications are properly configured. G 13. Download project EXERC_9 to the PLC. Go online and place the PLC in the Run mode. G 14. Open data file B3 and observe that the corresponding window displays the logic state of the bits in the 16-bit array of instruction BSL R6:0 (element 0 of data file B3, or B3:0). Since the File address of this instruction is set to B3:0, the bit array starts at the first bit position of element 0 of file B3, that is, at bit position 0 of this file. Since the Length of this instruction is set to 16, the bit array ends at bit position 15 of element 0 of file B3, that is, at bit position 15 of this file. What bits in the bit array of instruction BSL R6:0 are currently set to logic state 1? Place the B3 data file window at the bottom of the RSLogix Micro window. 9-8

9 G 15. Open data file R6 - CONTROL. Observe that the corresponding window displays the status bits of instruction BSL R6:0, as well as the length (number of bits) of the bit array of this instruction. What is the logic state of the EN and DN status bits of instruction BSL R6:0? Why? Place the R6 - CONTROL data file window at the bottom of the RSLogix Micro window. G 16. Activate PLC input 0, using one of the toggle switches of the trainer, while observing the bits in positions 0 through 7 of the bit array. Are these bits shifted to the left (to a higher bit number) by one bit position? Why? G 17. What is the logic state of the EN and DN status bits of instruction BSL R6:0? Why? G 18. While observing the bits in the bit array as they are shifted to the left, deactivate and activate PLC input 0 seven times, that is, until the bits in positions 8 through 15 of the bit array are set to logic state 1, and the bits in positions 0 through 7 are set to logic state 0. Deactivate and activate PLC input 0 once more to shift the bits by one position. Is the bit in position 0 of the bit array now set to logic state 1? Why? 9-9

10 Is PLC output 2 activated? Why? G 19. Deactivate and activate PLC input 0 seven times, that is, until the bits in positions 0 through 7 of the bit array are set to logic state 1, and the bits in positions 8 through 15 are set to logic state 0. Deactivate and activate PLC input 0 once more to shift the bits by one position. Is the bit in position 0 of the bit array now set to logic state 0? Why? Is PLC output 2 still activated? Why? G 20. On the PLC Trainer, make sure that all PLC inputs are deactivated [remove the switch connection lead(s) and place all the switch toggles downward]. Close the B3 and R6 data file windows, then proceed with the exercise. Forcing an Input Data File Bit G 21. Open data file I1 - INPUT and observe that input file bits 0 through 13 (I:0.0/0 through I:0.0/13) are at logic state 0, since no PLC input is currently activated. Also, observe that since PLC input 0 is deactivated, the rung containing instruction BSL R6:0 (rung 0) is false, causing PLC output 0 to be deactivated. G 22. In the I1 - INPUT data file window, click the Forces button to display the Force table associated with this file. 9-10

11 The input data file window, now named I1 - INPUT FORCES, displays the forces currently applied on PLC input data file bits 0 through 13. A dot (.) indicates that no force is currently applied on the corresponding input data file bit. G 23. Select bit position 0 of word I:0.0 of the I1- INPUT FORCES data file window by clicking on this bit position, then choose the Force On command in the context-sensitive menu to force input data file bit 0 to logic state 1. On the PLC module, observe that the FORCE LED is now flashing. In program file LAD 2, observe that the indication ON appears below instruction XIC I:0/0 in rung 0, indicating that the installed force, when enabled, will affect the status (true/false) of this instruction. Finally, observe that the Online section in the upper left corner of the RSLogix Micro window now indicates "FORCES INSTALLED", and "FORCES ENABLED", indicating that the installed forces are currently enabled (that is, they have an effect on the input data file bits, the status of the ladder program instructions, and the logic of this program). G 24. Open data file I1 - INPUT in the Data Files folder of processor EXERC_9. You should now see two input data file windows: the one named I1 - INPUT, and the one named I1 - INPUT FORCES. In the I1 - INPUT data file window, input data file bit 0 is highlighted to indicate that a force is installed on it. Instruction XIC I:0/0 in rung 0 is true, even if PLC input 0 is currently deactivated, as indicated by PLC input status LED 0 on the PLC module. Have other instructions in the ladder program gone true based on the forced input data file bit (bit I:0.0/0) and logical continuity rules? Explain. G 25. In the I1 - INPUT FORCES data file window, select bit position 0 of word I:0.0, then choose the Force Off command in the context-sensitive menu to return input data file bit 0 to logic state 0. What happens to input data file bit 0 in the I1 - INPUT data file window? To the status of instruction XIC I:0/0 in rung 0 and to PLC outputs 0 and 1? 9-11

12 G 26. In the I1 - INPUT FORCES data file window, click the Remove All button. A message box will appear asking for a confirmation before removing all forces in the processor. Click the Yes button to remove the forces. What happens to bit 0 in the I1 - INPUT FORCES data file window? To the information provided about the forces in the Online (upper leftmost) section of the RSLogix Micro window? G 27. Using the knowledge acquired up to this point, force input data file bit 0 to logic state 0. Then, activate PLC input 0 and observe that this has no effect on the program logic, instruction XIC I:0/0 in rung 0 remaining false due to input data file bit 0 being stuck at logic state 0. In the I1 - INPUT FORCES data file window, click the Remove All button, then click the Yes button in the message box that appears to remove all forces. G 28. On the PLC Trainer, make sure that all PLC inputs are deactivated [remove the switch connection leads(s) and place all the switch toggles downward]. Close the I1 - INPUT and the I1 - INPUT FORCES data file windows, then proceed with the exercise. Forcing the circuitry of a PLC Output G 29. Open data file O0 - OUTPUT and observe that output file bits 0 through 7 (O:0.0/0 through O:0.0/7) are set to logic state 0, since no PLC output is currently activated. G 30. In the O0 - OUTPUT data file window, click the Forces button to display the force table associated with this file. The output data file window, now named O0 - OUTPUT FORCES, displays the forces currently applied on the PLC output interface circuitry associated with PLC outputs 0 through 7. A dot (.) indicates that no force is currently installed on the corresponding PLC output interface circuitry. 9-12

13 G 31. Select bit position 0 of word O:0.0 in the O0 - OUTPUT FORCES data file window, then choose the Force On command in the context-sensitive menu to force the PLC output interface circuitry associated with PLC output 0 to the energized state. On the PLC module, observe that the FORCE LED is now flashing. In program file LAD 2, observe that the indication ON appears below instruction OTE O:0/0 in rung 1. Finally, observe that the Online section now indicates "FORCES INSTALLED" and "FORCES ENABLED". G 32. Open data file O0 - OUTPUT in the Data Files folder of processor EXERC_9. You should now see two output data file windows: the one named O0 - OUTPUT, and the one named O0 - OUTPUT FORCES. In the O0 - OUTPUT data file window, output data file bit 0 has remained set to logic state 0. This occurs because when a force is installed on the circuitry of a PLC output, it does not affect the logic state of the output data file bit associated with this output. However, this bit is highlighted to indicate that a force is installed on the corresponding PLC output circuitry. Instruction OTE O:0/0 in rung 0 remains false. This occurs because when a force is installed on the circuitry of a PLC output, it does not affect the program logic. However, the PLC output interface circuitry associated with PLC output 0 is energized, since PLC output status indicator 0 on the PLC module and PLC output lamp 0 on the trainer front panel are both lit. G 33. Using the knowledge acquired up to this point, force the circuitry associated with PLC output 0 to the deenergized state. Then, activate PLC input 0 to make rung 0 and instruction BSL R6:0 in this rung true. Observe that the applied force has no effect on the program logic, since instruction OTE O:0/0 in rung 1 becomes true. However, PLC output status indicator 0 on the PLC module and PLC output lamp 0 on the trainer front panel both remain unlit because of the applied force. In the O0 - OUTPUT FORCES data file window, click the Remove All button, then click the Yes button in the message box that appears to remove all forces. G 34. Place the PLC in the Program mode and clear the PLC memory. G 35. Close RSLogix Micro. Turn off the computer. 9-13

14 G 36. On the PLC Trainer, make sure that all PLC inputs are deactivated. Turn off the PLC Trainer. Remove all the switch connection leads, set all the switch toggles downward, and return all the equipment. CONCLUSION In this exercise, you became familiar with the following shift register instructions of the trainer PLC: the bit shift left (BSL) instruction and the bit shift right (BSR) instruction. You learned that these instructions shift a block of bits within a bit array, one bit at a time, on each false-to-true transition of the rung in which they are contained. The BSL instruction shifts the block of bits to a higher bit number by one position on each false-to-true rung transition. The source bit at the specified bit address is inserted into the first bit position of the array, while the bit in the last position of the array is shifted out of the array and stored into the unload (UL) bit position. The BSR instruction shifts the block of bits to a lower bit number by one position on each false-to-true rung transition. The source bit at the specified bit address is inserted into the last position of the array, while the bit in the first position of the array is shifted out of the array and stored into the UL bit position. You also became familiar with the Force function of the trainer PLC. You saw that this function can be used while the PLC is in the Run mode to override the current status of PLC inputs or outputs, regardless of their actual status. REVIEW QUESTIONS 1. What is the bit array of a BSL or BSR instruction? 2. If the File address of a BSL instruction is set to B3:2 and the length of this instruction is set to 25, at what bit position of data file B3 does the bit array start? At what position does it end? 3. What is the unload (UL) status bit of a BSR instruction? 9-14

15 4. Briefly describe how a BSL instruction works. 5. True or false? When the circuitry associated with a PLC output is forced to the energized state, the output data file bit associated with this output is set to logic state 1, while the logic of the ladder program is affected accordingly. 9-15