Dynacache: Dynamic Cloud Caching

Size: px
Start display at page:

Download "Dynacache: Dynamic Cloud Caching"

Transcription

1 Dynacache: Dynamic Cloud Caching Asaf Cidon, Assaf Eisenman, Mohammad Alizadeh and Sachin Ka? Stanford University MIT 1

2 Driving Web Applica4on Performance Web- scale applica4ons heavily reliant on memory caches Facebook: 1000s servers, 5 billion requests per second

3 Hit- rate Impacts Performance +1% cache hit- rate à 35% speedup Old latency: 374 µs New latency: 278 µs Facebook study: A4koglu et al [Sigmetrics 12] End- to- end speedup even greater User queries wait on hundreds of requests

4 How Does Work? Get(key) Set(key, value) Client

5 How Does Work? Get(key) Set(key, value) Response(value) ACK Client

6 : Sounds Familiar? CPU Cache Memory Management Fixed- sized entries First Come First Serve Evic4on Policy LRU LRU Fixed- sized slabs First Come First Serve Resource Alloca4on Across Applica4ons First Come First Serve First Come First Serve

7 Not the Same! CPU Cache Request size Even Highly variable Available resources and complexity Constrained Unconstrained Workload predictability Predictable Unpredictable

8 Dynacache: Dynamic Cache Controller Hit-rate curve estimation Controller Request distribution Client

9 Dynacache: Dynamic Cache Controller Change Memory Allocation Controller Change Eviction Policy Client

10 Opportuni4es for Dynacache 1. Dynamic memory alloca4on 2. Dynamic evic4on policy 3. Dynamic resource alloca4on across applica4ons 4.

11 Opportuni4es for Dynacache 1. Dynamic memory allocaeon 2. Dynamic evic4on policy 3. Dynamic resource alloca4on across applica4ons 4.

12 Memory Alloca4on in Key 1 35 bytes Empty Page Empty Page

13 Memory Alloca4on in Key 1 35 bytes 64 bytes slab class Key 1 Empty Page

14 Memory Alloca4on in Key bytes 64 byte slab class Key 1 Key bytes 256 byte slab class Key 2 Key 3

15 Memory Alloca4on in Key 4 33 bytes Key 5 31 bytes Key bytes 64 byte slab class Key 1 Key 7 Key 4 Key 8 Key 5 Key 9 Key 6 Key byte slab class Key 2 Key 3

16 Separate Evic4on Queue for Each Slab Class Key bytes Key bytes Eviction Eviction 64 byte slab class Key 1 Key 4 Key 5 Key 6 Key 7 Key 8 Key 9 Key byte slab class Key 2 Key 3

17 Problems with Memory Alloca4on Key bytes Key bytes Eviction Eviction 64 byte slab class Key 1 Key 4 Key 5 Key 6 Key 7 Key 8 1. Greedy slab class alloca4on favors large slab classes Key 9 Key byte slab class Key 2 Key 3

18 Problems with Memory Alloca4on Key bytes Key bytes Eviction Eviction 64 byte slab class Key 1 Key 4 Key 5 Key 6 Key 7 Key 8 1. Greedy slab class alloca4on favors large slab classes 2. Slab calcifica4on when request sizes change over 4me Key 9 Key byte slab class Key 2 Key 3

19 MemCachier Dataset Weeklong trace taken from MemCachier 30 servers 490 applica4ons Each applica4on has its own pages Each slab class has its own evic4on queue

20 Applica4on 3: Greedy Alloca4on Favors Large Slabs Classes 80% Slab Class AllocaEon: ApplicaEon 3, Memcachier 70% 60% 50% 40% 30% 20% % Memory Allocated by Default Slab Alloca4on % Memory Allocated by Op4mal Slab Alloca4on 10% 0% K 2K 4K 8K 16K 32K 64K 128K Slab Class Size (bytes)

21 Hit- rate Curve Profiling

22 Dynamically Op4mize Memory Alloca4on Using Hit- rate curves ƒ frequency of requests h hit- rate of requests m memory allocated to slab class e evic4on policy M memory allocated to applica4on

23 Poten4al of Dynamic Memory Alloca4on in Memcachier 45% Speedup 40% 35% 30% 25% 20% 15% 10% 5% 0% ApplicaEon ID

24 Related Work Op4mizing memory alloca4on across applica4ons based on hitrate curves Mimir: Saemundsson et al [SOCC 14] client McRouter: Likhtarov et al [Facebook blog 14] Rebalancing slabs to reduce slab calcifica4on Twimer: Rajashekhar et al [Twimer blog 12] Facebook: Nishtala et al [NSDI 13]

25 Summary Web applica4ons heavily reliant on s policies are sta4c and greedy Resource alloca4on Evic4on policy Web applica4ons are dynamic and variable Dynacache is dynamic cache controller that can dynamically adapt resource alloca4on and evic4on policy

26 Dynacache Prototype Implementa4on Low Entropy Low Classifier Entropy High Entropy Classifier App 7 Classifie Hitrate r Curve App 7 Op4mal Slab Alloc. App 1, Slab 0 App 3, Slab 6 App 7, Slab 3 LRU Queues Client Requests Responses Profiler Optimize r Dynacache Controller

27 Evalua4on Throughput) Overhead) 8.00%$ 6.00%$ 4.00%$ 2.00%$ 0.00%$ 4$ 8$ 12$ 16$ 20$ 24$ 28$ 32$ 36$ 40$ Requests)per)Second)(1000s))

Asaf Cidon, Assaf Eisenman, Mohammad Alizadeh and Sachin KaH

Asaf Cidon, Assaf Eisenman, Mohammad Alizadeh and Sachin KaH Cli$anger: Scaling Performance Cliffs in Memory Caches [NSDI 2016] Cache OS: Data Center Dynamic Cache Management Asaf Cidon, Assaf Eisenman, Mohammad Alizadeh and Sachin KaH 1 Key-Value Caches are Essen1al

More information

Memshare: a Dynamic Multi-tenant Key-value Cache

Memshare: a Dynamic Multi-tenant Key-value Cache Memshare: a Dynamic Multi-tenant Key-value Cache ASAF CIDON*, DANIEL RUSHTON, STEPHEN M. RUMBLE, RYAN STUTSMAN *STANFORD UNIVERSITY, UNIVERSITY OF UTAH, GOOGLE INC. 1 Cache is 100X Faster Than Database

More information

Cliffhanger: Scaling Performance Cliffs in Web Memory Caches

Cliffhanger: Scaling Performance Cliffs in Web Memory Caches Cliffhanger: Scaling Performance Cliffs in Web Memory Caches The MIT Faculty has made this article openly available. Please share how this access benefits you. Your story matters. Citation As Published

More information

MemC3: MemCache with CLOCK and Concurrent Cuckoo Hashing

MemC3: MemCache with CLOCK and Concurrent Cuckoo Hashing MemC3: MemCache with CLOCK and Concurrent Cuckoo Hashing Bin Fan (CMU), Dave Andersen (CMU), Michael Kaminsky (Intel Labs) NSDI 2013 http://www.pdl.cmu.edu/ 1 Goal: Improve Memcached 1. Reduce space overhead

More information

ElCached: Elastic Multi-Level Key-Value Cache

ElCached: Elastic Multi-Level Key-Value Cache Rahman Lavaee University of Rochester ElCached: Elastic Multi-Level Key-Value Cache Stephen Choi, Yang-Suk Kee Samsung Memory Solutions Lab Chen Ding University of Rochester Abstract Today s cloud service

More information

Efficient Memory and Bandwidth Management for Industrial Strength Kirchhoff Migra<on

Efficient Memory and Bandwidth Management for Industrial Strength Kirchhoff Migra<on Efficient Memory and Bandwidth Management for Industrial Strength Kirchhoff Migra

More information

Flashield: a Hybrid Key-value Cache that Controls Flash Write Amplification

Flashield: a Hybrid Key-value Cache that Controls Flash Write Amplification Flashield: a Hybrid Key-value Cache that Controls Flash Write Amplification Assaf Eisenman 1, Asaf Cidon 1,2, Evgenya Pergament 1, Or Haimovich 1, Ryan Stutsman 3, Mohammad Alizadeh 4, and Sachin Katti

More information

Cache memories are small, fast SRAM-based memories managed automatically in hardware. Hold frequently accessed blocks of main memory

Cache memories are small, fast SRAM-based memories managed automatically in hardware. Hold frequently accessed blocks of main memory Cache Memories Cache memories are small, fast SRAM-based memories managed automatically in hardware. Hold frequently accessed blocks of main memory CPU looks first for data in caches (e.g., L1, L2, and

More information

Hyperbolic Caching: Flexible Caching for Web Applications

Hyperbolic Caching: Flexible Caching for Web Applications Hyperbolic Caching: Flexible Caching for Web Applications Aaron Blankstein Princeton University (now @ Blockstack Inc.) Siddhartha Sen Microsoft Research NY Michael J. Freedman Princeton University Modern

More information

Virtual Memory B: Objec5ves

Virtual Memory B: Objec5ves Virtual Memory B: Objec5ves Benefits of a virtual memory system" Demand paging, page-replacement algorithms, and allocation of page frames" The working-set model" Relationship between shared memory and

More information

NetCache: Balancing Key-Value Stores with Fast In-Network Caching

NetCache: Balancing Key-Value Stores with Fast In-Network Caching NetCache: Balancing Key-Value Stores with Fast In-Network Caching Xin Jin, Xiaozhou Li, Haoyu Zhang, Robert Soulé Jeongkeun Lee, Nate Foster, Changhoon Kim, Ion Stoica NetCache is a rack-scale key-value

More information

NetCache: Balancing Key-Value Stores with Fast In-Network Caching

NetCache: Balancing Key-Value Stores with Fast In-Network Caching NetCache: Balancing Key-Value Stores with Fast In-Network Caching Xin Jin, Xiaozhou Li, Haoyu Zhang, Robert Soulé Jeongkeun Lee, Nate Foster, Changhoon Kim, Ion Stoica NetCache is a rack-scale key-value

More information

GD-Wheel: A Cost-Aware Replacement Policy for Key-Value Stores

GD-Wheel: A Cost-Aware Replacement Policy for Key-Value Stores GD-Wheel: A Cost-Aware Replacement Policy for Key-Value Stores Conglong Li Carnegie Mellon University conglonl@cs.cmu.edu Alan L. Cox Rice University alc@rice.edu Abstract Memory-based key-value stores,

More information

The Art and Science of Memory Alloca4on

The Art and Science of Memory Alloca4on The Art and Science of Memory Alloca4on Don Porter 1 Binary Formats RCU Logical Diagram Memory Allocators Threads User System Calls Kernel Today s Lecture File System Networking Sync Memory Management

More information

Implica(ons of Non Vola(le Memory on So5ware Architectures. Nisha Talagala Lead Architect, Fusion- io

Implica(ons of Non Vola(le Memory on So5ware Architectures. Nisha Talagala Lead Architect, Fusion- io Implica(ons of Non Vola(le Memory on So5ware Architectures Nisha Talagala Lead Architect, Fusion- io Overview Non Vola;le Memory Technology NVM in the Datacenter Op;mizing sobware for the iomemory Tier

More information

Tools for Social Networking Infrastructures

Tools for Social Networking Infrastructures Tools for Social Networking Infrastructures 1 Cassandra - a decentralised structured storage system Problem : Facebook Inbox Search hundreds of millions of users distributed infrastructure inbox changes

More information

High-Performance Key-Value Store on OpenSHMEM

High-Performance Key-Value Store on OpenSHMEM High-Performance Key-Value Store on OpenSHMEM Huansong Fu*, Manjunath Gorentla Venkata, Ahana Roy Choudhury*, Neena Imam, Weikuan Yu* *Florida State University Oak Ridge National Laboratory Outline Background

More information

LHD: Improving Cache Hit Rate by Maximizing Hit Density

LHD: Improving Cache Hit Rate by Maximizing Hit Density LHD: Improving Cache Hit Rate by Maximizing Hit Density Nathan Beckmann Haoxian Chen Asaf Cidon Carnegie Mellon University University of Pennsylvania Stanford University/Barracuda Networks beckmann@cs.cmu.edu

More information

hashfs Applying Hashing to Op2mize File Systems for Small File Reads

hashfs Applying Hashing to Op2mize File Systems for Small File Reads hashfs Applying Hashing to Op2mize File Systems for Small File Reads Paul Lensing, Dirk Meister, André Brinkmann Paderborn Center for Parallel Compu2ng University of Paderborn Mo2va2on and Problem Design

More information

Cascade Mapping: Optimizing Memory Efficiency for Flash-based Key-value Caching

Cascade Mapping: Optimizing Memory Efficiency for Flash-based Key-value Caching Cascade Mapping: Optimizing Memory Efficiency for Flash-based Key-value Caching Kefei Wang and Feng Chen Louisiana State University SoCC '18 Carlsbad, CA Key-value Systems in Internet Services Key-value

More information

6.888 Lecture 8: Networking for Data Analy9cs

6.888 Lecture 8: Networking for Data Analy9cs 6.888 Lecture 8: Networking for Data Analy9cs Mohammad Alizadeh ² Many thanks to Mosharaf Chowdhury (Michigan) and Kay Ousterhout (Berkeley) Spring 2016 1 Big Data Huge amounts of data being collected

More information

MongoDB Revs You Up: What Storage Engine is Right for You?

MongoDB Revs You Up: What Storage Engine is Right for You? MongoDB Revs You Up: What Storage Engine is Right for You? Jon Tobin, Director of Solution Eng. --------------------- Jon.Tobin@percona.com @jontobs Linkedin.com/in/jonathanetobin Agenda How did we get

More information

Be Fast, Cheap and in Control with SwitchKV. Xiaozhou Li

Be Fast, Cheap and in Control with SwitchKV. Xiaozhou Li Be Fast, Cheap and in Control with SwitchKV Xiaozhou Li Goal: fast and cost-efficient key-value store Store, retrieve, manage key-value objects Get(key)/Put(key,value)/Delete(key) Target: cluster-level

More information

Execu&on Templates: Caching Control Plane Decisions for Strong Scaling of Data Analy&cs

Execu&on Templates: Caching Control Plane Decisions for Strong Scaling of Data Analy&cs Execu&on Templates: Caching Control Plane Decisions for Strong Scaling of Data Analy&cs Omid Mashayekhi Hang Qu Chinmayee Shah Philip Levis July 13, 2017 2 Cloud Frameworks SQL Streaming Machine Learning

More information

Example. You manage a web site, that suddenly becomes wildly popular. Performance starts to degrade. Do you?

Example. You manage a web site, that suddenly becomes wildly popular. Performance starts to degrade. Do you? Scheduling Main Points Scheduling policy: what to do next, when there are mul:ple threads ready to run Or mul:ple packets to send, or web requests to serve, or Defini:ons response :me, throughput, predictability

More information

Heterogeneous Resources Management In Modern Data Centers with Dynamic Workloads Ningfang Mi

Heterogeneous Resources Management In Modern Data Centers with Dynamic Workloads Ningfang Mi Heterogeneous Resources Management In Modern Data Centers with Dynamic Workloads Ningfang Mi Electrical and Computer Engineering Dept. Northeastern University ningfang@ece.neu.edu 1 Research Focus To investigate

More information

SHARDS & Talus: Online MRC estimation and optimization for very large caches

SHARDS & Talus: Online MRC estimation and optimization for very large caches SHARDS & Talus: Online MRC estimation and optimization for very large caches Nohhyun Park CloudPhysics, Inc. Introduction Efficient MRC Construction with SHARDS FAST 15 Waldspurger at al. Talus: A simple

More information

Facebook Tao Distributed Data Store for the Social Graph

Facebook Tao Distributed Data Store for the Social Graph L. Lancia, G. Salillari Cloud Computing Master Degree in Data Science Sapienza Università di Roma Facebook Tao Distributed Data Store for the Social Graph L. Lancia & G. Salillari 1 / 40 Table of Contents

More information

On BigFix Performance: Disk is King. How to get your infrastructure right the first time! Case Study: IBM Cloud Development - WW IT Services

On BigFix Performance: Disk is King. How to get your infrastructure right the first time! Case Study: IBM Cloud Development - WW IT Services On BigFix Performance: Disk is King How to get your infrastructure right the first time! Case Study: IBM Cloud Development - WW IT Services Authors: Shaun T. Kelley, Mark Leitch Abstract: Rolling out large

More information

L7: Performance. Frans Kaashoek Spring 2013

L7: Performance. Frans Kaashoek Spring 2013 L7: Performance Frans Kaashoek kaashoek@mit.edu 6.033 Spring 2013 Overview Technology fixes some performance problems Ride the technology curves if you can Some performance requirements require thinking

More information

CS 465 Final Review. Fall 2017 Prof. Daniel Menasce

CS 465 Final Review. Fall 2017 Prof. Daniel Menasce CS 465 Final Review Fall 2017 Prof. Daniel Menasce Ques@ons What are the types of hazards in a datapath and how each of them can be mi@gated? State and explain some of the methods used to deal with branch

More information

Distributed caching for cloud computing

Distributed caching for cloud computing Distributed caching for cloud computing Maxime Lorrillere, Julien Sopena, Sébastien Monnet et Pierre Sens February 11, 2013 Maxime Lorrillere (LIP6/UPMC/CNRS) February 11, 2013 1 / 16 Introduction Context

More information

Virtual Memory COMPSCI 386

Virtual Memory COMPSCI 386 Virtual Memory COMPSCI 386 Motivation An instruction to be executed must be in physical memory, but there may not be enough space for all ready processes. Typically the entire program is not needed. Exception

More information

Be Fast, Cheap and in Control with SwitchKV Xiaozhou Li

Be Fast, Cheap and in Control with SwitchKV Xiaozhou Li Be Fast, Cheap and in Control with SwitchKV Xiaozhou Li Raghav Sethi Michael Kaminsky David G. Andersen Michael J. Freedman Goal: fast and cost-effective key-value store Target: cluster-level storage for

More information

ECE 30 Introduction to Computer Engineering

ECE 30 Introduction to Computer Engineering ECE 0 Introduction to Computer Engineering Study Problems, Set #9 Spring 01 1. Given the following series of address references given as word addresses:,,, 1, 1, 1,, 8, 19,,,,, 7,, and. Assuming a direct-mapped

More information

CISC 360. Cache Memories Exercises Dec 3, 2009

CISC 360. Cache Memories Exercises Dec 3, 2009 Topics ν CISC 36 Cache Memories Exercises Dec 3, 29 Review of cache memory mapping Cache Memories Cache memories are small, fast SRAM-based memories managed automatically in hardware. ν Hold frequently

More information

Analysis and Implementation of Global Preemptive Fixed-Priority Scheduling with Dynamic Cache Allocation

Analysis and Implementation of Global Preemptive Fixed-Priority Scheduling with Dynamic Cache Allocation Analysis and Implementation of Global Preemptive Fixed-Priority Scheduling with Dynamic Cache Allocation Meng Xu Linh Thi Xuan Phan Hyon-Young Choi Insup Lee Department of Computer and Information Science

More information

MemC3: Compact and Concurrent MemCache with Dumber Caching and Smarter Hashing

MemC3: Compact and Concurrent MemCache with Dumber Caching and Smarter Hashing To appear in Proceedings of the 1th USENIX Symposium on Networked Systems Design and Implementation (NSDI 13), Lombard, IL, April 213 MemC3: Compact and Concurrent MemCache with Dumber Caching and Smarter

More information

: Advanced Compiler Design. 8.0 Instruc?on scheduling

: Advanced Compiler Design. 8.0 Instruc?on scheduling 6-80: Advanced Compiler Design 8.0 Instruc?on scheduling Thomas R. Gross Computer Science Department ETH Zurich, Switzerland Overview 8. Instruc?on scheduling basics 8. Scheduling for ILP processors 8.

More information

Evaluating Phase Change Memory for Enterprise Storage Systems

Evaluating Phase Change Memory for Enterprise Storage Systems Hyojun Kim Evaluating Phase Change Memory for Enterprise Storage Systems IBM Almaden Research Micron provided a prototype SSD built with 45 nm 1 Gbit Phase Change Memory Measurement study Performance Characteris?cs

More information

mpart: Miss Ratio Curve Guided Partitioning in Key-Value Stores

mpart: Miss Ratio Curve Guided Partitioning in Key-Value Stores Michigan Technological University Digital Commons @ Michigan Tech Dissertations, Master's Theses and Master's Reports 2018 mpart: Miss Ratio Curve Guided Partitioning in Key-Value Stores Daniel Byrne Michigan

More information

CS 261 Fall Caching. Mike Lam, Professor. (get it??)

CS 261 Fall Caching. Mike Lam, Professor. (get it??) CS 261 Fall 2017 Mike Lam, Professor Caching (get it??) Topics Caching Cache policies and implementations Performance impact General strategies Caching A cache is a small, fast memory that acts as a buffer

More information

RouteBricks: Exploi2ng Parallelism to Scale So9ware Routers

RouteBricks: Exploi2ng Parallelism to Scale So9ware Routers RouteBricks: Exploi2ng Parallelism to Scale So9ware Routers Mihai Dobrescu and etc. SOSP 2009 Presented by Shuyi Chen Mo2va2on Router design Performance Extensibility They are compe2ng goals Hardware approach

More information

Atomix: A Framework for Deploying Signal Processing Applica:ons on Wireless Infrastructure

Atomix: A Framework for Deploying Signal Processing Applica:ons on Wireless Infrastructure Atomix: A ramework for Deploying Signal Processing Applica:ons on Wireless Infrastructure Manu Bansal, Aaron Schulman, Sachin KaA Stanford University NSDI 15 SoIware- defined base- sta:ons DSP0 DSP1 Local

More information

Dynamic Languages. CSE 501 Spring 15. With materials adopted from John Mitchell

Dynamic Languages. CSE 501 Spring 15. With materials adopted from John Mitchell Dynamic Languages CSE 501 Spring 15 With materials adopted from John Mitchell Dynamic Programming Languages Languages where program behavior, broadly construed, cannot be determined during compila@on Types

More information

Infiniswap. Efficient Memory Disaggregation. Mosharaf Chowdhury. with Juncheng Gu, Youngmoon Lee, Yiwen Zhang, and Kang G. Shin

Infiniswap. Efficient Memory Disaggregation. Mosharaf Chowdhury. with Juncheng Gu, Youngmoon Lee, Yiwen Zhang, and Kang G. Shin Infiniswap Efficient Memory Disaggregation Mosharaf Chowdhury with Juncheng Gu, Youngmoon Lee, Yiwen Zhang, and Kang G. Shin Rack-Scale Computing Datacenter-Scale Computing Geo-Distributed Computing Coflow

More information

Optimizing Flash-based Key-value Cache Systems

Optimizing Flash-based Key-value Cache Systems Optimizing Flash-based Key-value Cache Systems Zhaoyan Shen, Feng Chen, Yichen Jia, Zili Shao Department of Computing, Hong Kong Polytechnic University Computer Science & Engineering, Louisiana State University

More information

Treadmill: Tail Latency Measurement at Microsecond-level Precision. Yunqi Zhang Johann Hauswald David Meisner Jason Mars Lingjia Tang

Treadmill: Tail Latency Measurement at Microsecond-level Precision. Yunqi Zhang Johann Hauswald David Meisner Jason Mars Lingjia Tang Treadmill: Tail Latency Measurement at Microsecond-level Precision Yunqi Zhang Johann Hauswald David Meisner Jason Mars Lingjia Tang Schedule Welcome Section 1: Tail latency 08:40 ~ 09:00 Overview of data

More information

Computer Systems CSE 410 Autumn Memory Organiza:on and Caches

Computer Systems CSE 410 Autumn Memory Organiza:on and Caches Computer Systems CSE 410 Autumn 2013 10 Memory Organiza:on and Caches 06 April 2012 Memory Organiza?on 1 Roadmap C: car *c = malloc(sizeof(car)); c->miles = 100; c->gals = 17; float mpg = get_mpg(c); free(c);

More information

Mlcached: Multi-level DRAM-NAND Key-value Cache

Mlcached: Multi-level DRAM-NAND Key-value Cache Mlcached: Multi-level DRAM-NAND Key-value Cache I. Stephen Choi, Byoung Young Ahn, and Yang-Suk Kee Samsung Memory Solutions Lab Abstract We present Mlcached, multi-level DRAM-NAND keyvalue cache, that

More information

Design and Implementa/on of a Consolidated Middlebox Architecture. Vyas Sekar Sylvia Ratnasamy Michael Reiter Norbert Egi Guangyu Shi

Design and Implementa/on of a Consolidated Middlebox Architecture. Vyas Sekar Sylvia Ratnasamy Michael Reiter Norbert Egi Guangyu Shi Design and Implementa/on of a Consolidated Middlebox Architecture Vyas Sekar Sylvia Ratnasamy Michael Reiter Norbert Egi Guangyu Shi 1 Need for Network Evolu/on New applica/ons Evolving threats Performance,

More information

Cache Memory and Performance

Cache Memory and Performance Cache Memory and Performance Cache Organization 1 Many of the following slides are taken with permission from Complete Powerpoint Lecture Notes for Computer Systems: A Programmer's Perspective (CS:APP)

More information

Treadmill: Attributing the Source of Tail Latency through Precise Load Testing and Statistical Inference

Treadmill: Attributing the Source of Tail Latency through Precise Load Testing and Statistical Inference Treadmill: Attributing the Source of Tail Latency through Precise Load Testing and Statistical Inference Yunqi Zhang, David Meisner, Jason Mars, Lingjia Tang Internet services User interactive applications

More information

Network Measurement. COS 461 Recita8on. h:p://

Network Measurement. COS 461 Recita8on. h:p:// Network Measurement COS 461 Recita8on h:p://www.cs.princeton.edu/courses/archive/spr14/cos461/ 2! Why Measure the Network? Scien8fic discovery Characterizing traffic, topology, performance Understanding

More information

MicroFuge: A Middleware Approach to Providing Performance Isolation in Cloud Storage Systems

MicroFuge: A Middleware Approach to Providing Performance Isolation in Cloud Storage Systems 1 MicroFuge: A Middleware Approach to Providing Performance Isolation in Cloud Storage Systems Akshay Singh, Xu Cui, Benjamin Cassell, Bernard Wong and Khuzaima Daudjee July 3, 2014 2 Storage Resources

More information

Goals. Facebook s Scaling Problem. Scaling Strategy. Facebook Three Layer Architecture. Workload. Memcache as a Service.

Goals. Facebook s Scaling Problem. Scaling Strategy. Facebook Three Layer Architecture. Workload. Memcache as a Service. Goals Memcache as a Service Tom Anderson Rapid application development - Speed of adding new features is paramount Scale Billions of users Every user on FB all the time Performance Low latency for every

More information

Building Adaptive Performance Models for Dynamic Resource Allocation in Cloud Data Centers

Building Adaptive Performance Models for Dynamic Resource Allocation in Cloud Data Centers Building Adaptive Performance Models for Dynamic Resource Allocation in Cloud Data Centers Jin Chen University of Toronto Joint work with Gokul Soundararajan and Prof. Cristiana Amza. Today s Cloud Pay

More information

A Comparison of Capacity Management Schemes for Shared CMP Caches

A Comparison of Capacity Management Schemes for Shared CMP Caches A Comparison of Capacity Management Schemes for Shared CMP Caches Carole-Jean Wu and Margaret Martonosi Princeton University 7 th Annual WDDD 6/22/28 Motivation P P1 P1 Pn L1 L1 L1 L1 Last Level On-Chip

More information

PebblesDB: Building Key-Value Stores using Fragmented Log Structured Merge Trees

PebblesDB: Building Key-Value Stores using Fragmented Log Structured Merge Trees PebblesDB: Building Key-Value Stores using Fragmented Log Structured Merge Trees Pandian Raju 1, Rohan Kadekodi 1, Vijay Chidambaram 1,2, Ittai Abraham 2 1 The University of Texas at Austin 2 VMware Research

More information

3/3/2014! Anthony D. Joseph!!CS162! UCB Spring 2014!

3/3/2014! Anthony D. Joseph!!CS162! UCB Spring 2014! Post Project 1 Class Format" CS162 Operating Systems and Systems Programming Lecture 11 Page Allocation and Replacement" Mini quizzes after each topic Not graded Simple True/False Immediate feedback for

More information

Improving Cloud Application Performance with Simulation-Guided CPU State Management

Improving Cloud Application Performance with Simulation-Guided CPU State Management Improving Cloud Application Performance with Simulation-Guided CPU State Management Mathias Gottschlag, Frank Bellosa April 23, 2017 KARLSRUHE INSTITUTE OF TECHNOLOGY (KIT) - OPERATING SYSTEMS GROUP KIT

More information

Tales of the Tail Hardware, OS, and Application-level Sources of Tail Latency

Tales of the Tail Hardware, OS, and Application-level Sources of Tail Latency Tales of the Tail Hardware, OS, and Application-level Sources of Tail Latency Jialin Li, Naveen Kr. Sharma, Dan R. K. Ports and Steven D. Gribble February 2, 2015 1 Introduction What is Tail Latency? What

More information

SEDA An architecture for Well Condi6oned, scalable Internet Services

SEDA An architecture for Well Condi6oned, scalable Internet Services SEDA An architecture for Well Condi6oned, scalable Internet Services Ma= Welsh, David Culler, and Eric Brewer University of California, Berkeley Symposium on Operating Systems Principles (SOSP), October

More information

Cache Memory Mapping Techniques. Continue to read pp

Cache Memory Mapping Techniques. Continue to read pp Cache Memory Mapping Techniques Continue to read pp. 289-305 Cache Memory Mapping Again cache memory is a small and fast memory between CPU and main memory A block of words have to be brought in and out

More information

First-In-First-Out (FIFO) Algorithm

First-In-First-Out (FIFO) Algorithm First-In-First-Out (FIFO) Algorithm Reference string: 7,0,1,2,0,3,0,4,2,3,0,3,0,3,2,1,2,0,1,7,0,1 3 frames (3 pages can be in memory at a time per process) 15 page faults Can vary by reference string:

More information

Caching At Twitter and moving towards a persistent, in-memory key-value store

Caching At Twitter and moving towards a persistent, in-memory key-value store aching At Twitter and moving towards a persistent, in-memory key-value store Manju Rajashekhar @manju Outline aching System Architecture Twemcache Twemproxy Learnings in-memory persistent store ache In

More information

CS152 Computer Architecture and Engineering

CS152 Computer Architecture and Engineering CS152 Computer Architecture and Engineering Caches and the Memory Hierarchy Assigned 9/17/2016 Problem Set #2 Due Tue, Oct 4 http://inst.eecs.berkeley.edu/~cs152/fa16 The problem sets are intended to help

More information

CS152 Computer Architecture and Engineering CS252 Graduate Computer Architecture Spring Caches and the Memory Hierarchy

CS152 Computer Architecture and Engineering CS252 Graduate Computer Architecture Spring Caches and the Memory Hierarchy CS152 Computer Architecture and Engineering CS252 Graduate Computer Architecture Spring 2019 Caches and the Memory Hierarchy Assigned February 13 Problem Set #2 Due Wed, February 27 http://inst.eecs.berkeley.edu/~cs152/sp19

More information

JIGSAW: SCALABLE SOFTWARE-DEFINED CACHES

JIGSAW: SCALABLE SOFTWARE-DEFINED CACHES JIGSAW: SCALABLE SOFTWARE-DEFINED CACHES NATHAN BECKMANN AND DANIEL SANCHEZ MIT CSAIL PACT 13 - EDINBURGH, SCOTLAND SEP 11, 2013 Summary NUCA is giving us more capacity, but further away 40 Applications

More information

Cache Memories. Andrew Case. Slides adapted from Jinyang Li, Randy Bryant and Dave O Hallaron

Cache Memories. Andrew Case. Slides adapted from Jinyang Li, Randy Bryant and Dave O Hallaron Cache Memories Andrew Case Slides adapted from Jinyang Li, Randy Bryant and Dave O Hallaron 1 Topics Cache memory organiza3on and opera3on Performance impact of caches 2 Cache Memories Cache memories are

More information

Operating System - Virtual Memory

Operating System - Virtual Memory Operating System - Virtual Memory Virtual memory is a technique that allows the execution of processes which are not completely available in memory. The main visible advantage of this scheme is that programs

More information

On Smart Query Routing: For Distributed Graph Querying with Decoupled Storage

On Smart Query Routing: For Distributed Graph Querying with Decoupled Storage On Smart Query Routing: For Distributed Graph Querying with Decoupled Storage Arijit Khan Nanyang Technological University (NTU), Singapore Gustavo Segovia ETH Zurich, Switzerland Donald Kossmann Microsoft

More information

CS 5523 Operating Systems: Memory Management (SGG-8)

CS 5523 Operating Systems: Memory Management (SGG-8) CS 5523 Operating Systems: Memory Management (SGG-8) Instructor: Dr Tongping Liu Thank Dr Dakai Zhu, Dr Palden Lama, and Dr Tim Richards (UMASS) for providing their slides Outline Simple memory management:

More information

Portal Cache Tuning with Portal Cache Viewer Open Mic 10/01/2014

Portal Cache Tuning with Portal Cache Viewer Open Mic 10/01/2014 Portal Cache Tuning with Portal Cache Viewer Open Mic 10/01/2014 Klaus Nossek Software Engineer, WebSphere Portal Dr. Andreas Wickenhaeuser Software Engineer, WebSphere Portal IBM Collaboration Solutions

More information

GCMA: Guaranteed Contiguous Memory Allocator. SeongJae Park

GCMA: Guaranteed Contiguous Memory Allocator. SeongJae Park GCMA: Guaranteed Contiguous Memory Allocator SeongJae Park These slides were presented during The Kernel Summit 2018 (https://events.linuxfoundation.org/events/linux-kernel-summit-2018/)

More information

Gecko: Contention-Oblivious Disk Arrays for Cloud Storage

Gecko: Contention-Oblivious Disk Arrays for Cloud Storage Gecko: Contention-Oblivious Disk Arrays for Cloud Storage Ji-Yong Shin Cornell University In collaboration with Mahesh Balakrishnan (MSR SVC), Tudor Marian (Google), and Hakim Weatherspoon (Cornell) FAST

More information

HYRISE In-Memory Storage Engine

HYRISE In-Memory Storage Engine HYRISE In-Memory Storage Engine Martin Grund 1, Jens Krueger 1, Philippe Cudre-Mauroux 3, Samuel Madden 2 Alexander Zeier 1, Hasso Plattner 1 1 Hasso-Plattner-Institute, Germany 2 MIT CSAIL, USA 3 University

More information

G Virtual Memory. Robert Grimm New York University

G Virtual Memory. Robert Grimm New York University G22.3250-001 Virtual Memory Robert Grimm New York University Altogether Now: The Three Questions! What is the problem?! What is new or different?! What are the contributions and limitations? VAX-11 Memory

More information

Learning-based Dynamic Cache Management in a Cloud

Learning-based Dynamic Cache Management in a Cloud Learning-based Dynamic Cache Management in a Cloud Jinhwan Choi Yu Gu Jinoh Kim Texas A&M University, Commerce, TX 75428, USA VISA Inc., Austin, USA Email: jchoi8@leomail.tamuc.edu, yugu1@visa.com, jinoh.kim@tamuc.edu

More information

Improving Cache Performance and Memory Management: From Absolute Addresses to Demand Paging. Highly-Associative Caches

Improving Cache Performance and Memory Management: From Absolute Addresses to Demand Paging. Highly-Associative Caches Improving Cache Performance and Memory Management: From Absolute Addresses to Demand Paging 6.823, L8--1 Asanovic Laboratory for Computer Science M.I.T. http://www.csg.lcs.mit.edu/6.823 Highly-Associative

More information

Question Points Score Total 100

Question Points Score Total 100 Midterm #2 CMSC 412 Operating Systems Fall 2005 November 22, 2004 Guidelines This exam has 7 pages (including this one); make sure you have them all. Put your name on each page before starting the exam.

More information

CS370 Operating Systems

CS370 Operating Systems CS370 Operating Systems Colorado State University Yashwant K Malaiya Fall 2016 Lecture 33 Virtual Memory Slides based on Text by Silberschatz, Galvin, Gagne Various sources 1 1 FAQ How does the virtual

More information

PARALLEL ID3. Jeremy Dominijanni CSE633, Dr. Russ Miller

PARALLEL ID3. Jeremy Dominijanni CSE633, Dr. Russ Miller PARALLEL ID3 Jeremy Dominijanni CSE633, Dr. Russ Miller 1 ID3 and the Sequential Case 2 ID3 Decision tree classifier Works on k-ary categorical data Goal of ID3 is to maximize information gain at each

More information

Agenda. EE 260: Introduction to Digital Design Memory. Naive Register File. Agenda. Memory Arrays: SRAM. Memory Arrays: Register File

Agenda. EE 260: Introduction to Digital Design Memory. Naive Register File. Agenda. Memory Arrays: SRAM. Memory Arrays: Register File EE 260: Introduction to Digital Design Technology Yao Zheng Department of Electrical Engineering University of Hawaiʻi at Mānoa 2 Technology Naive Register File Write Read clk Decoder Read Write 3 4 Arrays:

More information

Page 1. Multilevel Memories (Improving performance using a little cash )

Page 1. Multilevel Memories (Improving performance using a little cash ) Page 1 Multilevel Memories (Improving performance using a little cash ) 1 Page 2 CPU-Memory Bottleneck CPU Memory Performance of high-speed computers is usually limited by memory bandwidth & latency Latency

More information

Problem: Processor Memory BoJleneck

Problem: Processor Memory BoJleneck Today Memory hierarchy, caches, locality Cache organiza:on Program op:miza:ons that consider caches CSE351 Inaugural Edi:on Spring 2010 1 Problem: Processor Memory BoJleneck Processor performance doubled

More information

Computer Architecture and Engineering. CS152 Quiz #2. March 3rd, Professor Krste Asanovic. Name:

Computer Architecture and Engineering. CS152 Quiz #2. March 3rd, Professor Krste Asanovic. Name: Computer Architecture and Engineering CS152 Quiz #2 March 3rd, 2008 Professor Krste Asanovic Name: Notes: This is a closed book, closed notes exam. 80 Minutes 10 Pages Not all questions are of equal difficulty,

More information

D3N: A multi-layer cache for data centers with imbalanced networks

D3N: A multi-layer cache for data centers with imbalanced networks D3N: A multi-layer cache for data centers with imbalanced networks Emine Ugur Kaynar *, Mohammad Hossein Hajkazemi, Mania Abdi, Ata Turk *, Raja R. Sambasivan *, Larry Rudolph, Peter Desnoyers, Orran Krieger

More information

Perform page replacement. (Fig 8.8 [Stal05])

Perform page replacement. (Fig 8.8 [Stal05]) Virtual memory Operations and policies Chapters 3.4. 3.7 1 Policies and methods Fetch policy (Noutopolitiikka) When to load page to memory? Placement policy (Sijoituspolitiikka ) Where to place the new

More information

Crescando: Predictable Performance for Unpredictable Workloads

Crescando: Predictable Performance for Unpredictable Workloads Crescando: Predictable Performance for Unpredictable Workloads G. Alonso, D. Fauser, G. Giannikis, D. Kossmann, J. Meyer, P. Unterbrunner Amadeus S.A. ETH Zurich, Systems Group (Funded by Enterprise Computing

More information

FairRide: Near-Optimal Fair Cache Sharing

FairRide: Near-Optimal Fair Cache Sharing UC BERKELEY FairRide: Near-Optimal Fair Cache Sharing Qifan Pu, Haoyuan Li, Matei Zaharia, Ali Ghodsi, Ion Stoica 1 Caches are crucial 2 Caches are crucial 2 Caches are crucial 2 Caches are crucial 2 Cache

More information

Fluxo. Improving the Responsiveness of Internet Services with Automa7c Cache Placement

Fluxo. Improving the Responsiveness of Internet Services with Automa7c Cache Placement Fluxo Improving the Responsiveness of Internet Services with Automac Cache Placement Alexander Rasmussen UCSD (Presenng) Emre Kiciman MSR Redmond Benjamin Livshits MSR Redmond Madanlal Musuvathi MSR Redmond

More information

Large-scale Caching. CS6450: Distributed Systems Lecture 18. Ryan Stutsman

Large-scale Caching. CS6450: Distributed Systems Lecture 18. Ryan Stutsman Large-scale Caching CS6450: Distributed Systems Lecture 18 Ryan Stutsman Material taken/derived from Princeton COS-418 materials created by Michael Freedman and Kyle Jamieson at Princeton University. Licensed

More information

VIRTUAL MEMORY READING: CHAPTER 9

VIRTUAL MEMORY READING: CHAPTER 9 VIRTUAL MEMORY READING: CHAPTER 9 9 MEMORY HIERARCHY Core! Processor! Core! Caching! Main! Memory! (DRAM)!! Caching!! Secondary Storage (SSD)!!!! Secondary Storage (Disk)! L cache exclusive to a single

More information

EVCache: Lowering Costs for a Low Latency Cache with RocksDB. Scott Mansfield Vu Nguyen EVCache

EVCache: Lowering Costs for a Low Latency Cache with RocksDB. Scott Mansfield Vu Nguyen EVCache EVCache: Lowering Costs for a Low Latency Cache with RocksDB Scott Mansfield Vu Nguyen EVCache 90 seconds What do caches touch? Signing up* Logging in Choosing a profile Picking liked videos

More information

Cache Memories. From Bryant and O Hallaron, Computer Systems. A Programmer s Perspective. Chapter 6.

Cache Memories. From Bryant and O Hallaron, Computer Systems. A Programmer s Perspective. Chapter 6. Cache Memories From Bryant and O Hallaron, Computer Systems. A Programmer s Perspective. Chapter 6. Today Cache memory organization and operation Performance impact of caches The memory mountain Rearranging

More information

Memory Management 3/29/14 21:38

Memory Management 3/29/14 21:38 Presentation for use with the textbook Data Structures and Algorithms in Java, 6 th edition, by M. T. Goodrich, R. Tamassia, and M. H. Goldwasser, Wiley, 2014 Memory Management Diagram of a 4 4 plane of

More information

Anti-Caching: A New Approach to Database Management System Architecture. Guide: Helly Patel ( ) Dr. Sunnie Chung Kush Patel ( )

Anti-Caching: A New Approach to Database Management System Architecture. Guide: Helly Patel ( ) Dr. Sunnie Chung Kush Patel ( ) Anti-Caching: A New Approach to Database Management System Architecture Guide: Helly Patel (2655077) Dr. Sunnie Chung Kush Patel (2641883) Abstract Earlier DBMS blocks stored on disk, with a main memory

More information

HW1 Solutions. Type Old Mix New Mix Cost CPI

HW1 Solutions. Type Old Mix New Mix Cost CPI HW1 Solutions Problem 1 TABLE 1 1. Given the parameters of Problem 6 (note that int =35% and shift=5% to fix typo in book problem), consider a strength-reducing optimization that converts multiplies by

More information

Predictive Elastic Database Systems. Rebecca Taft HPTS 2017

Predictive Elastic Database Systems. Rebecca Taft HPTS 2017 Predictive Elastic Database Systems Rebecca Taft becca@cockroachlabs.com HPTS 2017 1 Modern OLTP Applications Large Scale Cloud-Based Performance is Critical 2 Challenges to transaction performance: skew

More information