An IEEE Decimal Parallel and Pipelined FPGA Floating Point Multiplier

Transcription

1 An IEEE Decimal Parallel and Pipelined FPGA Floating Point Multiplier Malte Baesler, Sven Ole Voigt, Thomas Teufel Institute for Reliable Computing Hamburg University of Technology September 1st, 2010

2 Agenda 1. Introduction a)why Decimal Floating Point Arithmetic? b)what are the Requirements on the Decimal Multiplier? 2. Decimal Fixed Point Multiplier 3. Decimal Floating Point Multiplier 4. Post Place & Route Results a)fixed Point Multiplier b)floating Point Multiplier 1/30

3 Introduction 2/30

4 Why decimal floating point arithmetic? avoid conversion errors human centric applications required for commercial applications, e.g. interest calculation 2/30

5 Why decimal floating point arithmetic? avoid conversion errors human centric applications required for commercial applications, e.g. interest calculation IEEE Standard for Floating Point Arithmetic published in August 2008 replaces IEEE and IEEE binary and decimal floating point arithmetic 2/30

6 Floating Point Arithmetic IEEE Floating Point Arithmetic decimal64 data format radix b=10 significand precision p=16 exponent range q min = 398, q max =369 3/30

7 Requirements on the multiplier fast low resource usage IEEE compliant pipelined due to re use in accurate scalar product fully combinational optimized for FPGA architecture (Virtex5) internal fast carry chain DSP48E slices 4/30

8 Requirements on the multiplier fast low resource usage IEEE compliant pipelined due to re use in accurate scalar product fully combinational optimized for FPGA architecture (Virtex5) internal fast carry chain DSP48E slices 4/30

9 Decimal Fixed Point Multiplier 5/30

10 Fixed Point Multiplier How does multiplication work? school method: partial product generation accumulation of partial products = /30

11 Fixed Point Multiplier based on concepts of A. Vazquez, E. Antelo, P.Montuschi 1 fully combinational BCD recoding schemes fast partial product generation fast BCD 4221 carry save adder reduction tree 1 A new family of high performance parallel decimal multipliers, 18 th IEEE Symposium on Computer Arithmetic, June /30

12 Fixed Point Multiplier ABCD 8421 BBCD 8421 p digits p digits DRec PPGen P 0 BCD 4221 P 1 BCD P p+1 BCD 4221 CSAT 2p CPA SBCD p digits S_sBCD p S_wBCD 4221 PPGen DRec Partial Product Generator Decimal Recoding Unit CSAT CPA Carry Save Adder Tree Carry Propagation Adder 7/30

13 Decimal Recoding ABCD 8421 BBCD 8421 p digits p digits DRec PPGen P 0 BCD 4221 P 1 BCD P p+1 BCD 4221 CSAT 2p CPA SBCD p digits S_sBCD p S_wBCD 4221 PPGen DRec Partial Product Generator Decimal Recoding Unit CSAT CPA Carry Save Adder Tree Carry Propagation Adder 8/30

14 Decimal Recoding transforms the multiplier's digit set {0, 9} into { 5, 5} reduces number of multiplicand multiples A 1, A 2, A 3, A 4, A 5 very fast operation, no ripple carry 8/30

15 Partial Product Generator ABCD 8421 BBCD 8421 p digits p digits DRec PPGen P 0 BCD 4221 P 1 BCD P p+1 BCD 4221 CSAT 2p CPA SBCD p digits S_sBCD p S_wBCD 4221 PPGen DRec Partial Product Generator Decimal Recoding Unit CSAT CPA Carry Save Adder Tree Carry Propagation Adder 9/30

16 Partial Product Generator calculates multiples exploits correlation between shift operation and constant value multiplication X = X X = X BCD Recoding is fast fixed value shift operation is for free only A 3 requires one carry propagate adder generates partial products P 0 P p 1 by selection of A 1 A 5 10's complement for A 1, A 2, A 3, A 4, A 5 B k 0: X n X 0 = X n X 0 1 9/30

17 BCD 4221 Carry Save Adder Tree ABCD 8421 BBCD 8421 p digits p digits DRec PPGen P 0 BCD 4221 P 1 BCD P p+1 BCD 4221 CSAT 2p CPA SBCD p digits S_sBCD p S_wBCD 4221 PPGen DRec Partial Product Generator Decimal Recoding Unit CSAT CPA Carry Save Adder Tree Carry Propagation Adder 10/30

18 Carry Save Adder Tree carry save adder tree sums up p+1 partial products P 3 P 2 P 1... P p+1 10/30

19 Carry Save Adder Tree CSA tree with respect to decimal recoding sign extension P 1 sign extension P 2 C 1 sign extension P 3 C 2... P p+1 C p 10/30

20 Carry Save Adder Tree improved CSA tree with respect to decimal recoding P 1 P 2 C 1 P 3 C 2... P p+1 C p improved sign extension 10/30

21 Improved Sign Extension adding several words composed of leading nines and following zeros always yields to a word composed of 0, 8, and 9. For example = x position of 0, 8, and 9 can be calculated very fast by means of FPGA's fast carry chain for c k X NegDC k ={9 in =0 sign k =1 8 for c in k =1 sign k =1 0 else c out in k =c k 1 ={ 1 for sign =1 k in c k else 11/30

22 Fixed Point Multiplier ABCD 8421 BBCD 8421 p digits p digits DRec PPGen P 0 BCD 4221 P 1 BCD P p+1 BCD 4221 CSAT 2p CPA SBCD p digits S_sBCD p S_wBCD 4221 PPGen DRec Partial Product Generator Decimal Recoding Unit CSAT CPA Carry Save Adder Tree Carry Propagation Adder 12/30

23 Fixed Point Multiplier ABCD 8421 BBCD 8421 p digits p digits DRec PPGen P 0 BCD 4221 P 1 BCD P p+1 BCD 4221 CSAT 2p CPA SBCD p digits S_sBCD p S_wBCD 4221 PPGen DRec Partial Product Generator Decimal Recoding Unit CSAT CPA Carry Save Adder Tree Carry Propagation Adder 12/30

24 Decimal Floating Point Multiplier 13/30

25 Decimal Floating Point Multiplier additional units for rounding, exponent computation and data format encoding/decoding based on M. Erle, B. Hickmann, M.Schulte 2 early estimation of shift left amount fully IEEE compliant support for gradual underflow and all rounding modes adapted to FPGA technology 2 Decimal Floating Point Multiplication, IEEE Transaction on Computers, VOL. 58, NO. 7, July /30

26 Y Densily Packed Decimal (DPD) Decoder X X = 0x03C B9C1E Y = 0x CB0D10 Leading Zeros Count / Shift Left Amount Computation Decimal Fixed Point Multipliplier Left Shift Register Exponent Computation Carry Propagate Adder Round Up Detection Overflow / Underflow Correction Rounding Unit Exception Unit DPD Encoder exception signals X Y 14/30

27 Y Densily Packed Decimal (DPD) Decoder Leading Zeros Count / Shift Left Amount Computation X Decimal Fixed Point Multipliplier X = 0x03C B9C1E Y = 0x CB0D10 X = EXP 156 Y = EXP 250 X Y = EXP 406 Left Shift Register Exponent Computation Carry Propagate Adder Round Up Detection Overflow / Underflow Correction Rounding Unit Exception Unit DPD Encoder exception signals X Y 15/30

28 Y Densily Packed Decimal (DPD) Decoder X X = EXP 156 Y = EXP 250 X Y = EXP 406 Leading Zeros Count / Shift Left Amount Computation Decimal Fixed Point Multipliplier Left Shift Register Z = significand(x Y) Z = Zs = Zc = Exponent Computation Carry Propagate Adder Round Up Detection Overflow / Underflow Correction Rounding Unit Exception Unit DPD Encoder exception signals X Y 16/30

29 Y Densily Packed Decimal (DPD) Decoder X X = EXP 156 Y = EXP 250 X Y = EXP 406 Leading Zeros Count / Shift Left Amount Computation Exponent Computation Decimal Fixed Point Multipliplier Left Shift Register Carry Propagate Adder Z = significand(x Y) Z = Zs = Zc = LZ(X)=6, LZ(Y)=6, SLA=min(6+6, p)=12 Z = Zs = Zc = Round Up Detection Overflow / Underflow Correction Rounding Unit Exception Unit DPD Encoder exception signals X Y 17/30

30 Y Densily Packed Decimal (DPD) Decoder X X = EXP 156 Y = EXP 250 X Y = EXP 406 Leading Zeros Count / Shift Left Amount Computation Exponent Computation Decimal Fixed Point Multipliplier Left Shift Register Carry Propagate Adder Z = significand(x Y) Z = Zs = Zc = LZ(X)=6, LZ(Y)=6, SLA=min(6+6, p)=12 Z = Zs = Zc = Round Up Detection Overflow / Underflow Correction Z' = , G=6, R=9, sb='0' Rounding Unit Exception Unit DPD Encoder exception signals X Y 18/30

31 Y Densily Packed Decimal (DPD) Decoder X X = EXP 156 Y = EXP 250 X Y = EXP 406 Leading Zeros Count / Shift Left Amount Computation Exponent Computation Decimal Fixed Point Multipliplier Left Shift Register Carry Propagate Adder Z = significand(x Y) Z = Zs = Zc = LZ(X)=6, LZ(Y)=6, SLA=min(6+6, p)=12 Z = Zs = Zc = Round Up Detection Overflow / Underflow Correction Z' = , G=6, R=9, sb='0' exponent = p SLA = 402 Rounding Unit Exception Unit DPD Encoder exception signals X Y 19/30

32 Y Densily Packed Decimal (DPD) Decoder X X = EXP 156 Y = EXP 250 X Y = EXP 406 Leading Zeros Count / Shift Left Amount Computation Exponent Computation Decimal Fixed Point Multipliplier Left Shift Register Carry Propagate Adder Z = significand(x Y) Z = Zs = Zc = LZ(X)=6, LZ(Y)=6, SLA=min(6+6, p)=12 Z = Zs = Zc = Round Up Detection Overflow / Underflow Correction Z' = , G=6, R=9, sb='0' exponent = p SLA = 402 Exception Unit Rounding Unit DPD Encoder Z'' = , G=6, R=3, sb='1' exponent = 398 exception signals X Y 20/30

33 Y Densily Packed Decimal (DPD) Decoder X X = EXP 156 Y = EXP 250 X Y = EXP 406 Leading Zeros Count / Shift Left Amount Computation Exponent Computation Decimal Fixed Point Multipliplier Left Shift Register Carry Propagate Adder Z = significand(x Y) Z = Zs = Zc = LZ(X)=6, LZ(Y)=6, SLA=min(6+6, p)=12 Z = Zs = Zc = Round Up Detection Overflow / Underflow Correction Z' = , G=6, R=9, sb='0' exponent = p SLA = 402 Exception Unit exception signals Rounding Unit DPD Encoder X Y Z'' = , G=6, R=3, sb='1' exponent = 398 round up Z''' = EXP /30

34 Y Densily Packed Decimal (DPD) Decoder X X = EXP 156 Y = EXP 250 X Y = EXP 406 Leading Zeros Count / Shift Left Amount Computation Exponent Computation Decimal Fixed Point Multipliplier Left Shift Register Carry Propagate Adder Z = significand(x Y) Z = Zs = Zc = LZ(X)=6, LZ(Y)=6, SLA=min(6+6, p)=12 Z = Zs = Zc = Round Up Detection Overflow / Underflow Correction Z' = , G=6, R=9, sb='0' exponent = p SLA = 402 Exception Unit exception signals Rounding Unit DPD Encoder X Y Z'' = , G=6, R=3, sb='1' exponent = 398 round up Z''' = EXP 398 Z = 0x BCCC493 invalid inexact overflow underflow 22/30

35 fixed point multiplier output type1 type2 type3 redundant (delayed CPA) redundant (delayed CPA) non redundant CPA length (digits) p+2 = 18 p+2 = 18 2 p = 32 shift register multiplier based multiplexer based multiplexer based decimal fixed point multiplier Ps Pc shift register shift register Qs u Qs l Qc u Qc l decimal fixed point multiplier Ps Pc CPA (2 p) CPA (p+2) CPA (p 2)... OR shift register... OR product G R sticky bit product G R sticky bit 23/30

36 fixed point multiplier output type1 type2 type3 redundant (delayed CPA) redundant (delayed CPA) non redundant CPA length (digits) p+2 = 18 p+2 = 18 2 p = 32 shift register multiplier based multiplexer based multiplexer based decimal fixed point multiplier Ps Pc shift register shift register Qs u Qs l Qc u Qc l decimal fixed point multiplier Ps Pc CPA (2 p) CPA (p+2) CPA (p 2)... OR shift register... OR product G R sticky bit product G R sticky bit 23/30

37 fixed point multiplier output type1 type2 type3 redundant (delayed CPA) redundant (delayed CPA) non redundant CPA length (digits) p+2 = 18 p+2 = 18 2 p = 32 shift register multiplier based multiplexer based multiplexer based decimal fixed point multiplier Ps Pc shift register shift register Qs u Qs l Qc u Qc l decimal fixed point multiplier Ps Pc CPA (2 p) CPA (p+2) CPA (p 2)... OR shift register... OR product G R sticky bit product G R sticky bit 23/30

38 fixed point multiplier output type1 type2 type3 redundant (delayed CPA) redundant (delayed CPA) non redundant CPA length (digits) p+2 = 18 p+2 = 18 2 p = 32 shift register multiplier based multiplexer based multiplexer based shifting through multiplication: X n X 2 n requires two DSP48Es per 32bit shift saves LUTs DSP48E X(31:16) MUL ADD shift 2 k X(15:0) MUL DSP48E Y(31:16) Y(15:0) 24/30

39 Post Place & Route Results 25/30

40 Decimal Fixed Point Multiplier with CPA output Xilinx Virtex5, speed grade 2 up to 13 pipeline registers, configurable via VHDL generics LUTs, FFs combined LUTs and FFs 25/30

41 Decimal Fixed Point Multiplier with CPA output Xilinx Virtex5, speed grade 2 up to 13 pipeline registers, configurable via VHDL generics LUTs, FFs combined LUTs and FFs 25/30

42 Decimal Floating Point Multiplier 26/30

43 Decimal Floating Point Multiplier 27/30

44 Decimal Floating Point Multiplier Type1 mul based shifting, delayed CPA Type2 mux based shifting, delayed CPA Type3 mux based shifting, no delayed CPA #LUTs #FFs #(LUT + FFs) #DSP48E approx. 70% of the LUTs are used by the fixed point multiplier (for Type2 and Type3) medium Virtex5 XC5VLX110T: LUTs ~ 11.5% 13% 28/30

45 Comparison to binary floating point multiplier 64 bit binary floating point multiplier generated with CoreGen no DSP48E Type2 decimal vs. CoreGen binary multiplier decimal binary decimal binary number of LUTs number of pipeline registers max. frequency (MHz) number of pipeline registers decimal mult. : more LUTs binary mult. : times faster 29/30

46 Comparison to binary floating point multiplier 64 bit binary floating point multiplier generated with CoreGen no DSP48E Type2 decimal vs. CoreGen binary multiplier decimal binary decimal binary number of LUTs number of pipeline registers max. frequency (MHz) number of pipeline registers decimal mult. : more LUTs binary mult. : times faster 29/30

47 Summary decimal fixed point multiplier parallel, fully combinational configurable number of pipeline stages decimal floating point multiplier configurable number of pipeline stages three different implementations tradeoff: area vs. speed future work: fully IEEE compliant co processor 30/30

48 Thank you for your attention!!!