Intel C++ Composer XE 2013 for Linux* Installation Guide and Release Notes

Transcription

1 Intel C++ Composer XE 2013 for Linux* Installation Guide and Release Notes Document number: US 4 October 2012 Table of Contents 1 Introduction Change History Update 1 (2013.1) Changes since Intel C++ Composer XE Product Contents System Requirements IA-64 Architecture (Intel Itanium ) Development Not Supported Documentation Samples Japanese Language Support Technical Support Installation Intel Software Manager Installation of Intel Many Integrated Core (Intel MIC) Platform Software Stack (MPSS) Cluster Installation Silent Install Using a License Server Eclipse* Integration Installation Known Installation Issues Installation Folders Removal/Uninstall Intel Many Integrated Core (Intel MIC) Architecture About Intel Composer XE 2013 for Linux* including Intel MIC Architecture...14 Installation Guide and Release Notes 1

2 3.2 Compatibility Getting Started Product Documentation Debuggers Intel Math Kernel Library (Intel MKL) Notes Intel C++ Compiler Debugging and Intel Debugger Intel C++ Compiler Compatibility New and Changed Features Inline assembly and intrinsic support for Intel architecture code named Broadwell added to Composer XE 2013 Update core_4th_gen_avx added for manual cpu dispatch in Composer XE 2013 Update Static Analysis Feature (formerly Static Security Analysis or Source Checker ) Requires Intel Inspector XE New and Changed Compiler Options New and Changed in Composer XE check-pointers=w added to Composer XE 2013 Update opt-assume-safe-padding, opt-streaming-cache-evict and opt-threads-per-core added in Composer XE 2013 Update ipp-link option fimf-domain-exclusion Other Changes Support for Microsoft loop pragma syntax added to Composer XE 2013 Update New Warning Level w3 and Changes to Warning Levels in Composer XE Binary compatibility change with regcall functions and elemental functions (i.e. declspec(vector)) New libirng library for vectorizing random number generator functions added to Composer XE Establishing the Compiler Environment Instruction Set Default Changed to Require Intel Streaming SIMD Extensions 2 (Intel SSE2)...30 Installation Guide and Release Notes 2

3 4.4.7 New Warning Level w3 and Changes to Warning Levels in Composer XE Intel Cilk Plus scalar Clause removed Intel Cilk Plus Array Notations Semantics Change in 2011 update Known Issues Intel Cilk Plus Known Issues Guided Auto-Parallel Known Issues Static Analysis Known Issues Intel Debugger (IDB) Support Deprecated for Intel Debugger Setting up the Java* Runtime Environment Starting the Debugger Additional Documentation Debugger Features Main Features of IDB Inspector XE 2011 Update 6 Supports break into debug with IDB Known Issues and Changes Default.gdbinit script on Pardus* systems may cause the Debugger crash No thread info available on Pardus* systems Thread Data Sharing Filters may not work correctly Core File Debugging Debugger crash if $HOME not set on calling shell Command line parameter idb and -dbx not supported Watchpoints now using processor debug registers (hardware based) in Composer XE 2011 Update Position Independent Executable (PIE) Debugging not Supported Command line parameter parallel not supported Signals Dialog Not Working Resizing GUI $cdir, $cwd Directories info stack Usage $stepg0 Default Value Changed SIGTRAP error on some Linux* Systems idb GUI cannot be used to debug MPI processes...37 Installation Guide and Release Notes 3

4 Thread Syncpoint Creation in GUI Data Breakpoint Dialog Stack Alignment for IA-32 Architecture GNOME Environment Issues Accessing Online-Help Eclipse Integration Supplied Integrations Integration notes How to Install the Intel C++ Eclipse Product Extension in Your Eclipse Platform Integrating the Intel Debugger into Eclipse How to Obtain and Install Eclipse, CDT and a JRE Installing JRE, Eclipse and CDT Launching Eclipse for Development with the Intel C++ Compiler Installing on Fedora* Systems Selecting Compiler Versions Intel Integrated Performance Primitives Intel IPP static threaded Libraries are Available as a Separate Download Intel IPP Cryptography Libraries are Available as a Separate Download Intel IPP Code Samples Intel Math Kernel Library Notices Changes in This Version What s New in Intel MKL 11.0 Update Changes in Initial Release Attributions Intel Threading Building Blocks Disclaimer and Legal Information Introduction This document describes how to install the product, provides a summary of new and changed features and includes notes about features and problems not described in the product documentation. Installation Guide and Release Notes 4

5 1.1 Change History This section highlights important from the previous product version and changes in product updates. For information on what is new in each component, please read the individual component release notes Update 1 (2013.1) Intel C++ Compiler XE Intel Debugger Intel Math Kernel Library 11.0 Update 1 Intel Integrated Performance Primitives 7.1 Update 1 Intel Threading Building Blocks 4.1 Update 1 Default code generation for Intel Xeon Phi processors no longer supported on A0 processor steppings Support for Eclipse* platform versions 4.2 and 3.8 and Eclipse CDT 8.1 Inline assembly and intrinsic support for Intel architecture code named Broadwell -opt-assume-safe-padding support for Intel Many Integrated Core architecture -opt-streaming-cache-evict and -opt-threads-per-core support for Intel Many Integrated Core architecture -check-pointers=w core_4th_gen_avx added for manual cpu dispatch in Composer XE 2013 Update 1 Microsoft* loop pragma support Corrections to reported problems Changes since Intel C++ Composer XE 2011 Development of applications that offload work to or natively run on an Intel Many Integrated Core (Intel MIC) architecture coprocessor is now supported. For details, see the section on Intel Many Integrated Core Architecture. Intel C++ Compiler updated to version Intel Debugger updated to version 13.0 o Intel Debugger support deprecated Intel Math Kernel Library updated to version 11.0 o Removed support for Intel Pentium III processor. See the Knowledge Base article on Deprecations for further information. Intel Integrated Performance Primitives updated to version 7.1 o Intel IPP static threaded libraries now available in separate package Intel Threading Building Blocks updated to version 4.1 Fedora 17*, SUSE* LINUX Enterprise Server 11 SP2, Ubuntu 11.10* and Ubuntu 12.04* now supported Support for the following versions of Linux distributions has been dropped: o Red Hat Enterprise Linux 4* o SUSE* LINUX Enterprise Server 11 SP1 o Fedora 15* Installation Guide and Release Notes 5

6 o Ubuntu 11.04* o Ubuntu 10.04* o Asianux* The Intel Software Manager has been added to help you manage product updates and license activation New C++11 features Improved support for future Intel processors Out-of-bounds memory checking New Warning Level w3 and Changes to Warning Levels in Composer XE 2013 Static Analysis Improvements 1.2 Product Contents Intel C++ Composer XE 2013 Update 1 for Linux* includes the following components: Intel C++ Compiler XE for building applications that run on IA-32, Intel 64, and Intel Many Integrated Core (Intel MIC) architecture systems running the Linux* operating system Intel Debugger Intel Integrated Performance Primitives 7.1 Update 1 Intel Math Kernel Library 11.0 Update 1 Intel Threading Building Blocks 4.1 Update 1 Integration into the Eclipse* development environment On-disk documentation 1.3 System Requirements For an explanation of architecture names, see A PC based on an IA-32 or Intel 64 architecture processor supporting the Intel Streaming SIMD Extensions 2 (Intel SSE2) instructions (Intel Pentium 4 processor or later, or compatible non-intel processor) o Development of 64-bit applications or applications targeting Intel MIC architecture is supported on a 64-bit version of the OS only. Development of 32- bit applications is supported on either 32-bit or 64-bit versions of the OS o Development for a 32-bit on a 64-bit host may require optional library components (ia32-libs, lib32gcc1, lib32stdc++6, libc6-dev-i386, gcc-multilib, g++multilib) to be installed from your Linux distribution. For Intel MIC architecture development/testing: o Intel Xeon Phi processor o Intel MIC Platform Software Stack (MPSS) For the best experience, a multi-core or multi-processor system is recommended 1GB of RAM (2GB recommended) 2.5GB free disk space for all features Installation Guide and Release Notes 6

7 One of the following Linux distributions (this is the list of distributions tested by Intel; other distributions may or may not work and are not recommended - please refer to Technical Support if you have questions): o Fedora* 17 o Red Hat Enterprise Linux* 5, 6 o SUSE LINUX Enterprise Server* 10, 11 SP2 o Ubuntu* 11.10, o Debian* 6.0 o Intel Cluster Ready o Pardus* (x64 only) Linux Developer tools component installed, including gcc, g++ and related tools Library libunwind.so is required in order to use the traceback option. Some Linux distributions may require that it be obtained and installed separately. Additional requirements to use the Graphical User Interface of the Intel Debugger Java* Runtime Environment (JRE) 6.0 (also called 1.6 ) 5.0 recommended o A 32-bit JRE must be used on an IA-32 architecture system and a 64-bit JRE must be used on an Intel 64 architecture system Additional requirements to use the integration into the Eclipse* development environment Eclipse Platform version 4.2 with: o Eclipse C/C++ Development Tools (CDT) 8.1 or later o Java* Runtime Environment (JRE) 6.0 (also called 1.6 ) or later Eclipse Platform version 3.8 with: o Eclipse C/C++ Development Tools (CDT) 8.1 or later o Java* Runtime Environment (JRE) 6.0 (also called 1.6 ) or later Eclipse Platform version 3.7 with: o Eclipse C/C++ Development Tools (CDT) 8.0 or later o Java* Runtime Environment (JRE) 6.0 (also called 1.6 ) or later There is a known issue with JRE 6.0 through update 10 that causes a crash on Intel 64 architecture. It is recommended to use the latest update for your JRE. See section for details. Notes The Intel compilers are tested with a number of different Linux distributions, with different versions of gcc. Some Linux distributions may contain header files different from those we have tested, which may cause problems. The version of glibc you use must be consistent with the version of gcc in use. For best results, use only the gcc versions as supplied with distributions listed above. The default for the Intel compilers is to build IA-32 architecture applications that require a processor supporting the Intel SSE2 instructions - for example, the Intel Pentium Installation Guide and Release Notes 7

8 4 processor. A compiler option is available to generate code that will run on any IA-32 architecture processor. However, if your application uses Intel Integrated Performance Primitives or Intel Threading Building Blocks, executing the application will require a processor supporting the Intel SSE2 instructions. Compiling very large source files (several thousands of lines) using advanced optimizations such as -O3, -ipo and -openmp, may require substantially larger amounts of RAM. The above lists of processor model names are not exhaustive - other processor models correctly supporting the same instruction set as those listed are expected to work. Please refer to Technical Support if you have questions regarding a specific processor model Some optimization options have restrictions regarding the processor type on which the application is run. Please see the documentation of these options for more information IA-64 Architecture (Intel Itanium ) Development Not Supported This product version does not support development on or for IA-64 architecture (Intel Itanium ) systems. The version 11.1 compiler remains available for development of IA-64 architecture applications. 1.4 Documentation Product documentation can be found in the Documentation folder as shown under Installation Folders. 1.5 Samples Samples for each product component can be found in the Samples folder as shown under Installation Folders. 1.6 Japanese Language Support Intel compilers provide support for Japanese language users. Error messages, visual development environment dialogs and some documentation are provided in Japanese in Installation Guide and Release Notes 8

9 addition to English. By default, the language of error messages and dialogs matches that of your operating system language selection. Japanese-language documentation can be found in the ja_jp subdirectory for documentation and samples. Japanese language support will be available in an update on or after the release of Intel C++ Composer XE If you wish to use Japanese-language support on an English-language operating system, or English-language support on a Japanese-language operating system, you will find instructions at Technical Support If you did not register your compiler during installation, please do so at the Intel Software Development Products Registration Center. Registration entitles you to free technical support, product updates and upgrades for the duration of the support term. For information about how to find Technical Support, Product Updates, User Forums, FAQs, tips and tricks, and other support information, please visit Note: If your distributor provides technical support for this product, please contact them for support rather than Intel. 2 Installation The installation of the product requires a valid license file or serial number. If you are evaluating the product, you can also choose the Evaluate this product (no serial number required) option during installation. If you received your product on DVD, mount the DVD, change the directory (cd) to the toplevel directory of the mounted DVD and begin the installation using the command:./install.sh If you received the product as a downloadable file, first unpack it into a writeable directory of your choice using the command: tar xzvf name-of-downloaded-file Then change the directory (cd) to the directory containing the unpacked files and begin the installation using the command:./install.sh Follow the prompts to complete installation. Installation Guide and Release Notes 9

10 Note that there are several different downloadable files available, each providing different combinations of components. Please read the download web page carefully to determine which file is appropriate for you. You do not need to uninstall previous versions or updates before installing a newer version the new version will coexist with the older versions. 2.1 Intel Software Manager The installation now provides an Intel Software Manager to provide a simplified delivery mechanism for product updates and provide current license status and news on all installed Intel software products. You can also volunteer to provide Intel anonymous usage information about these products to help guide future product design. This option, the Intel Software Improvement Program, is not enabled by default you can opt-in during installation or at a later time, and may opt-out at any time. For more information please see Installation of Intel Many Integrated Core (Intel MIC) Platform Software Stack (MPSS) The Intel MIC Platform Software Stack (MPSS) may be installed before or after installing the Intel Composer XE 2013 for Linux* including Intel MIC Architecture product. Refer to the Intel MIC Platform Software Stack (MPSS) documentation for the necessary steps to install the user space and kernel drivers. 2.3 Cluster Installation To install a product on multiple nodes of a cluster on Linux*, the following steps should be taken: 1) Run the installation on a system where Intel Cluster Studio is installed. Also, passwordless ssh must be configured between machines in a cluster. 2) On step "4 Options" there will be a "Cluster installation" option. The default value is "Current node". 3) To install on a cluster, the user must select this option and then provide a machines.linux file with IP-addresses, hostnames, FQDNs, and other information for the cluster nodes (one node per line). The first line is expected to describe the current (master) node. 4) Once the machines.linux file is provided, additional options will appear: Number of parallel installations, Check for shared installation directory. 5) When all options are configured and installation has begun, the installation will check connectivity with all nodes (a prerequisite) and only then will it install the product on these nodes. 2.4 Silent Install For information on automated or silent install capability, please see Installation Guide and Release Notes 10

11 2.5 Using a License Server If you have purchased a "floating" license, see for information on how to install using a license file or license server. This article also provides a source for the Intel License Server that can be installed on any of a wide variety of systems. 2.6 Eclipse* Integration Installation Please refer to the section below on Eclipse Integration 2.7 Known Installation Issues If you have enabled the Security-Enhanced Linux (SELinux*) feature of your Linux distribution, you must change the SELINUX mode to permissive before installing the Intel C++ Compiler. Please see the documentation for your Linux distribution for details. After installation is complete, you may reset the SELINUX mode to its previous value. On some versions of Linux, auto-mounted devices do not have the "exec" permission and therefore running the installation script directly from the DVD will result in an error such as: bash:./install.sh: /bin/bash: bad interpreter: Permission denied If you see this error, remount the DVD with exec permission, for example: mount /media/<dvd_label> -o remount,exec and then try the installation again. The product is fully supported on Ubuntu*, Debian*, and Pardus* Linux distributions for IA-32 and Intel 64 architecture systems as noted above under System Requirements. Due to a restriction in the licensing software, however, it is not possible to use the Trial License feature when evaluating IA-32 components on an Intel 64 architecture system under Ubuntu, Debian or Pardus. This affects using a Trial License only. Use of serial numbers, license files, floating licenses or other license manager operations, and off-line activation (with serial numbers) is not affected. If you need to evaluate IA-32 components of the product on an Intel 64 architecture Ubuntu, Debian, or Pardus system, please visit the Intel Software Evaluation Center ( to obtain an evaluation serial number. 2.8 Installation Folders The compiler installs, by default, under /opt/intel this is referenced as <install-dir> in the remainder of this document. You are able to specify a different location, and can also perform a non-root install in the location of your choice. The directory organization has changed since the Intel Compilers 11.1 release. While the top-level installation directory has also changed between the original C++ Composer XE 2011 release and Composer XE 2013, the composerxe symbolic link can still be used to reference the latest product installation. Installation Guide and Release Notes 11

12 Under <install-dir> are the following directories: bin contains symbolic links to executables for the latest installed version lib symbolic link to the lib directory for the latest installed version include symbolic link to the include directory for the latest installed version man symbolic link to the directory containing man pages for the latest installed version ipp symbolic link to the directory for the latest installed version of Intel Integrated Performance Primitives mkl symbolic link to the directory for the latest installed version of Intel Math Kernel Library tbb symbolic link to the directory for the latest installed version of Intel Threading Building Blocks composerxe symbolic link to the composer_xe_2013 directory composer_xe_2013 directory containing symbolic links to subdirectories for the latest installed Intel Composer XE 2013 compiler release composer_xe_2013.<n>.<pkg> - physical directory containing files for a specific compiler version. <n> is the update number, and <pkg> is a package build identifier. Each composer_xe_2013 directory contains the following directories that reference the latest installed Intel Composer XE 2013 compiler: bin directory containing scripts to establish the compiler environment and symbolic links to compiler executables for the host platform pkg_bin symbolic link to the compiler bin directory include symbolic link to the compiler include directory lib symbolic link to the compiler lib directory ipp symbolic link to the ipp directory mkl symbolic link to the mkl directory tbb symbolic link to the tbb directory debugger symbolic link to the debugger directory eclipse_support symbolic link to the eclipse_support directory man symbolic link to the man directory Documentation symbolic link to the Documentation directory Samples symbolic link to the Samples directory Each composer_xe_2013.<n>.<pkg> directory contains the following directories that reference a specific update of the Intel Composer XE 2013 compiler: bin all executables pkg_bin symbolic link to bin directory compiler shared libraries and header files debugger debugger files Installation Guide and Release Notes 12

13 Documentation documentation files man man pages eclipse_support files to support Eclipse integration ipp Intel Integrated Performance Primitives libraries and header files mkl Intel Math Kernel Library libraries and header files tbb Intel Threading Building Blocks libraries and header files Samples Product samples and tutorial files.scripts scripts for installation If you have both the Intel C++ and Intel Fortran compilers installed, they will share folders for a given version and update. This directory layout allows you to choose whether you want the latest compiler, no matter which version, the latest update of the Intel Composer XE 2013 compiler, or a specific update. Most users will reference <install-dir>/bin for the compilervars.sh [.csh] script, which will always get the latest compiler installed. This layout should remain stable for future releases. 2.9 Removal/Uninstall Removing (uninstalling) the product should be done by the same user who installed it (root or a non-root user). If sudo was used to install, it must be used to uninstall as well. It is not possible to remove the compiler while leaving any of the performance library or Eclipse* integration components installed. 1. Open a terminal window and set default (cd) to any folder outside <install-dir> 2. Type the command: <install-dir>/bin/uninstall.sh 3. Follow the prompts 4. Repeat steps 2 and 3 to remove additional platforms or versions If you have the same-numbered version of Intel Fortran Compiler installed, it may also be removed. If you have added the Intel C++ Eclipse integration to an instance of Eclipse in your environment, you will need to update your Eclipse configuration by removing the Intel integration extension site from your Eclipse configuration. To do this, Go to Help > About Eclipse and click on "Installation Details". Select "Intel(R) C++ Compiler XE 13.0 for Linux* OS " under "Installed Software" and click on "Uninstall..." Click "Finish". When asked to restart Eclipse, select "Yes". 3 Intel Many Integrated Core (Intel MIC) Architecture This section summarizes changes, new features and late-breaking news about the Intel Composer XE 2013 for Linux* including Intel MIC Architecture. Installation Guide and Release Notes 13

14 3.1 About Intel Composer XE 2013 for Linux* including Intel MIC Architecture The Intel Composer XE 2013 for Linux* including Intel MIC Architecture extends the feature set of the Intel C++ Composer XE 2013 and the Intel Fortran Composer XE 2013 products by enabling predefined sections of code to execute on an Intel Xeon Phi coprocessor. These sections of code run on the coprocessor if it is available. Otherwise, they run on the host CPU. This document uses the terms coprocessor and target to refer to the target of an offload operation. The current components of Intel Composer XE 2013 that support Intel MIC architecture are the: Intel C++ and Fortran Compilers Intel Debugger (Intel IDB) Intel Math Kernel Library (Intel MKL) Intel Threading Building Blocks (Intel TBB) Eclipse* IDE Integration 3.2 Compatibility This release supports the Intel Xeon Phi coprocessor. Refer to the Technical Support section for additional information. If you need generated code to support A0 steppings of this coprocessor, please see the note recommending use of opt-streaming-stores never. 3.3 Getting Started There is only one compiler that generates code both for Intel 64 architecture and for Intel MIC architecture. Refer to the section on Establishing the Compiler Environment to get started, using intel64 as the architecture you setup for. Refer to the Notes section below for further changes. 3.4 Product Documentation Documentation concerning the Intel MIC architecture for Composer XE 2013 is currently undergoing change. For the latest documentation updates, please go to our web site at Debuggers For graphical debugging, use the Eclipse* integration pointing to the idb_mpm debugger startup script (under bin/intel64_mic). You can attach to code running on Intel MIC architecture or you can debug code offloaded from the CPU. Use of the debuggers on a remote system through SSH requires setting the DISPLAY environment variable to your local X display to minimize lag caused by SSH display forwarding. Installation Guide and Release Notes 14

15 The package also contains command line versions of these debuggers. They are called idbc (for the Intel 64 architecture host) and idbc_mic (for the Intel MIC architecture target). Please note that the auto-attach feature is not supported in the command line versions of the debuggers. 3.6 Intel Math Kernel Library (Intel MKL) For details on Intel MIC support, see the section on Intel MKL. 3.7 Notes Intel C++ Compiler Default code generation no longer supports Intel Xeon Phi coprocessor A0 stepping in Composer XE 2013 Update 1 Composer XE 2013 update 1 now generates new streaming store instructions that were introduced in the Intel Xeon Phi coprocessor B0 stepping. These instructions are not supported on the A0 stepping, and will cause runtime errors. If you require your application to run on A0 steppings, use the option opt-streaming-stores never to avoid generating these instructions. This may decrease performance on B0 or later steppings opt-assume-safe-padding new in Composer XE 2013 Update 1 By default, the compiler should not assume that sizes of objects in memory are greater than written in program even though it is allowed to insert padding if needed. When opt-assumesafe-padding is set, the compiler may assume that variables and dynamically allocated memory is padded, so that accessing up to 64 bytes beyond what is specified in the program source will not cause any faults. This new option provides a way for the programmer to declare safety of access slightly beyond object boundary which may be used by optimizations to loosen safety considerations required by some Intel MIC instructions and thus emit faster code. The option doesn t tell or require the compiler to provide such padding for static and automatic objects: providing padding is the programmer s responsibility. The option simply changes the assumptions the compiler can safely make. The default is disabled (-no-opt-assume-safepadding) opt-streaming-cache-evict and opt-threads-per-core new in Composer XE 2013 Update 1 The option opt-streaming-cache-evict specifies cache eviction level when streaming loads/stores are used on Intel MIC architecture: opt-streaming-cache-evict =0 no cache evict instructions generated opt-streaming-cache-evict =1 Installation Guide and Release Notes 15

16 L1 cache eviction instruction generated after streaming load/store opt-streaming-cache-evict =2 L2 cache eviction instruction generated after streaming load/store opt-streaming-cache-evict =3 L1 and L2 cache eviction instruction generated after streaming load/store The option opt-threads-per-core specifies the number of hardware threads per core on the Intel MIC architecture to be used for an application. The number of threads specified can be a number between 1 and New -fimf-domain-exclusion Compiler Option The following compiler option information was omitted from the on-disk documentation. fimf-domain-exclusion Indicates the domain on which a function is evaluated. IDE Equivalent None Architectures Intel 64 architecture, targeting Intel MIC Architecture Syntax Linux*: -fimf-domain-exclusion=classlist[:funclist] OS X*: None Windows*: None Arguments classlist A comma separated list of: One or more of the five floating point value class names you can exclude from the function domain without affecting the correctness of your program One of the short-hand tokens. The class names are: extremes nans infinities Installation Guide and Release Notes 16

17 denormals zeros The short-hand tokens are: none: None of the above are excluded from the domain. all: All of the above are excluded from the domain. common: Same as extremes,nans,infinities,denormals. The order of the class tokens is unimportant, and you can specify each token more than once. funclist A comma separated list of function names. If you don t specify this argument, the domain restrictions apply to all math library functions. Default None Description This indicates the domain on which a function is evaluated, and specifies that your program will function correctly if the functions specified in funclist do not produce standard conforming results on the number classes Missing symbols not detected at link time In the offload compilation model, the binaries targeting the Intel MIC architecture are generated as dynamic libraries (.so). Dynamic libraries do not need all referenced variables or routines to be resolved during linking as these can be resolved during load time. This behavior could mask some missing variable or routine in the application resulting in a failure during load time. In order to identify and resolve all missing symbols at link time, use the following command line option to list the unresolved variables. -offload-option,mic,compiler,"-z defs" Tuning Memory Allocation Performance This content updates/overrides similar content in the C++ Composer XE 2013 User s Guide. For user-allocated data on the coprocessor, using large (2 MB) page allocations via mmap(), instead of malloc or _mm_malloc, may improve application performance. Not all applications benefit from using a larger page size. In general, the performance impact from a larger page-size depends greatly on the data access pattern. If the application accesses multiple data-structures that are allocated in different pages, having only limit TLB entries for 2 MB pages on the coprocessor can cause performance degradation. The default page size is 4KB for malloc and _mm_malloc. To enable your application to use 2MB pages, use the sample method provided below: Installation Guide and Release Notes 17

18 #include <string.h> #include <sys/mman.h> #include <stdio.h> #include <errno.h> #define TWO_MB (2*1024*1024ULL) #define MAP_HUGETLB 0x40000 /* create a huge page mapping */ /* allocate memory using huge page support */ #define MALLOC_2M(size) \ mmap(null, size, PROT_READ PROT_WRITE, MAP_ANONYMOUS MAP_SHARED \ MAP_HUGETLB MAP_POPULATE, -1, 0) /* free allocated memory */ #define FREE_2M(addr, size) munmap(addr, (size + TWO_MB & ~(TWO_MB-1))) /** * allocate_huge_pages - Allocate memory using 2MB page support - Size of the memory to allocate */ static inline void* allocate_huge_pages(size_t size) { size_t sz = size + TWO_MB & ~(TWO_MB-1); void* mem = MALLOC_2M(sz); if (mem == MAP_FAILED) printf("mmap allocation failed\n"); return mem; } opt-prefetch-distance compiler option Syntax: -opt-prefetch-distance=n1[,n2] Allowed values for n1,n2 are >=0 (non-negative integer values). n2 is optional. If n2 is specified, n1 should be >= n2. Sample usages: -opt-prefetch-distance=64,32 -opt-prefetch-distance=16,2 -opt-prefetch-distance=24 Description: Installation Guide and Release Notes 18

19 This option is used for performance tuning. This option allows the user to specify the prefetchdistance. The unit is the number of (possibly-vectorized) iterations that should be used for compiler-generated prefetches inside loops. The value of n1 will be used as the distance for the vprefetch1 instruction (prefetch from memory to L2 cache) and value of n2 (if specified) will be used as the distance for the vprefetch0 instruction (prefetch from L2 cache to L1 cache). If the option is not used, the prefetch distances will be determined based on compiler heuristics. Note that the -opt-prefetch option is turned ON by default for Intel MIC architecture. This option is ignored if opt-prefetch=0 is specified *MIC* tag added to compile-time diagnostics The compiler diagnostics infrastructure is modified to add an additional offload *MIC* tag to the output message to allow differentiation from the Target (Intel MIC Architecture) and the host CPU compilations. The additional tag appears only in the Target compilation diagnostics issued when compiling with offload extensions for Intel MIC architecture. In the examples below the sample source programs trigger identical diagnostics during both the host CPU and Target MIC compilations; however, some programs will generate different diagnostics during these two compilations. The new tag permits easier association with either the CPU or Target compilation. $ icc -c sample.c sample.c(1): warning #1079: *MIC* return type of function "main" must be "int" void main() ^ sample.c(5): warning #120: *MIC* return value type does not match the function type return 0; ^ sample.c(1): warning #1079: return type of function "main" must be "int" void main() ^ sample.c(5): warning #120: return value type does not match the function type return 0; Runtime Type Information (RTTI) not supported Runtime Type Information (RTTI) is not supported under the Virtual-Shared memory programming method; specifically, use of dynamic_cast<> and typeid() is not supported. Installation Guide and Release Notes 19

20 Direct (native) mode requires transferring runtime libraries like libiomp5.so to coprocessor The Intel MIC Platform Software Stack (MPSS) no longer includes Intel compiler libraries under /lib, for example the OpenMP* library, libiomp5.so. When running OpenMP* applications in direct mode (i.e. on the coprocessor card), users must first upload (via scp) a copy of the Intel MIC Architecture OpenMP* library (<install_dir>/compiler/lib/mic/libiomp5.so) to the card (device names will be of the format micn, where the first card will be named mic0, the second mic1, and so on) before running their application. Failure to make this library available will result in a run-time failure like: /libexec/ld-elf.so.1: Shared object "libiomp5.so" not found, required by "sample" This can also apply to other compiler runtimes like libimf.so. The required libraries will depend on the application and how it s built Calling exit() from an offload region When calling exit() from within an offload region, the application terminates with an error diagnostic offload error: process on the device 0 unexpectedly exited with code Environment Variable for Controlling Offload Behavior Several additional environment variables are available for controlling offload behavior MIC_ENV_PREFIX This is the general mechanism to pass environment variable values to each Intel Xeon Phi coprocessor. The value of MIC_ENV_PREFIX sets the value of the prefix which is used to recognize environment variable values intended for coprocessors. For example, setenv MIC_ENV_PREFIX MYCARDS will use MYCARDS as the string that indicates that an environment variable is intended for a specific coprocessor. Environment variable values of the form <mic-prefix>_<var>=<value> will send <var>=<value> to each coprocessor. Environment variable values of the form <mic-prefix>_<card-number>_<var>=<value> will send <var>=<value> to the coprocessor numbered <card-number>. Installation Guide and Release Notes 20

21 Environment variable values of the form <mic-prefix>_env=<variable1=value1 variable2=value2> will send <variable1>=<value1> and <variable2>=<value2> to each coprocessor. Environment variable values of the form <mic-prefix>_<card-number>_env=<variable1=value1 variable2=value2> will send <variable1>=<value1> and <variable2>=<value2> to the coprocessor numbered <card-number>. Examples: setenv MIC_ENV_PREFIX PHI // Defines the prefix to be used setenv PHI_ABCD abcd // Sets ABCD=abcd on all coprocessors setenv PHI_2_EFGH efgh // Sets EFGH=efgh on coprocessor 2 setenv PHI_VAR X=x Y=y // Sets X=x and Y=y on all coprocessors setenv PHI_4_VAR P=p Q=q // Sets P=p and Q=q on coprocessor MIC_USE_2MB_BUFFERS Sets the threshold for creating buffers with large pages. A buffer is created with the large pages hint if its size exceeds the threshold value. Example: // any variable allocated on a coprocessor that is equal to // or greater than 100KB in size will be allocated in large pages. setenv MIC_USE_2MB_BUFFERS 100k MIC_STACKSIZE Sets the size of the offload process stack for all Intel Xeon Phi coprocessors used in the application. This is the overall stack size. Use MIC_OMP_STACKSIZE to modify the size of each OpenMP* thread. Example: setenv MIC_STACKSIZE 100M // Sets MIC stack to 100 MB OFFLOAD_DEVICES The environment variable OFFLOAD_DEVICES restricts the process to use only the coprocessors specified as the value of the variable. <value> is a comma separated list of physical device numbers in the range 0 to (number_of_devices_in_the_system-1). Devices available for offloading are numbered logically. That is _Offload_number_of_devices() Installation Guide and Release Notes 21

22 returns the number of allowed devices and device indexes specified in the target specifier of an offload directive are in the range 0 to (number_of_allowed_devices-1). Example setenv OFFLOAD_DEVICES 1, Debugging and Intel Debugger Using IDB with MPSS Alpha 2 ( x) When using the Intel Debugger for Intel Many Integrated Core architecture with firmware version MPSS Alpha 2 ( x) the following limitations apply: The Eclipse* CDT integration of the Intel Debugger does not support "Attach to process" for native applications running on the coprocessor When debugging native coprocessor applications on the command line, the remote debug agent idbserver_mic is uploaded and started using scp/ssh. This implies that the user id used to start idbc_mic must also exist on the coprocessor card. Unless passwordless authentication has been configured for this user id, scp and ssh will require a password being typed. When debugging native coprocessor applications on the command line, the shared library libmyodbl-service.so, that used to be uploaded to the coprocessor automatically needs to be uploaded manually now. The way to achieve this is to create an overlay, so the file is uploaded at boot time. Follow the instructions on how to use overlays in the MPSS readme.txt (currently available from the Intel SDP MAKC1 Family product in Intel Premier Support). The steps needed to implement this specific overlay look like this: a. Create /etc/sysconfig/mic/conf.d/myo.conf containing the following: # MYO download files Overlay / /opt/intel/mic/myo/config/myo.filelist b. Create /opt/intel/mic/myo/config/myo.filelist containing dir /lib file /lib64/libmyodbl-service.so opt/intel/mic/myo/lib/libmyodbl-service.so When debugging heterogeneous applications on the command line, the offload process is started as root. Using idbc_mic with a different user id than root will cause the offload process to not be visible by the remote debug server idbserver_mic. The workaround is to launch the command line debugger idbc_mic as root. Alternatively the options -mpm-launch=1 -mpm-cardid=<card-id> can be added to the default launch options: idbc_mic -mpm-launch=1 -mpm-cardid=<card-id> -tco - rconnect=tcpip:<cardip>:<port> Installation Guide and Release Notes 22

23 When debugging heterogeneous applications from Eclipse*, you may get the error offload error: cannot start process on the device 0 (error code 1) when creating the offload process. To work around this, restart the debugging session until you get a session that creates the offload process successfully The IDB Debugger may fail to setup the command line argument for the debuggee under Eclipse* The debugger may not set the command line argument for the debuggee correctly under Eclipse when loading an application using the `file command in GDB mode. The debugee may abort with the message: *** abort -internal failure : get_command_argumentfailed In this case, add the executable to the command line argument of IDB Eclipse* fails to display local variables Local variables cannot be seen under the Eclipse environment while debugging an application. Workaround: Enter the local variable into the Expression Window of Eclipse to get its value Safely ending offload debug sessions To avoid issues like orphan processes or stale debugger windows when ending offload applications, manually end the debugging session before the application is reaching its exit code. The following procedure is recommended for terminating a debug session. Manually stop a debug session before the application reaches the exit-code. When stopped, press the red stop button in the toolbar in the MIC-side debugger first. This will end the offloaded part of the application. Next, do the same in the CPU-side debugger. The link between the two debuggers will be kept alive. The MIC-side debugger will stay connected to the debug agent and the application will remain loaded in the CPU-side debugger, including all breakpoints that have been set. At this point, both debugger windows can safely be closed MIC-side debugger asserts on setting source dirs Setting source directories in the ABR debugger might lead to an assertion. Resolution: The assertion should not affect debugger operation. To avoid the assertion anyway, don t use source directory settings. The debugger will prompt you to browse for files it cannot locate automatically Accessing _Cilk_shared variables in the debugger Writing to a shared variable in an offloaded section from within the CPU-side debugger before the CPU-side debugee has accessed that variable may result in loss of the written value/might display a wrong value or cause the application to crash. Installation Guide and Release Notes 23

24 Consider the following code snippet: _Cilk_shared bool is_active; _Cilk_shared my_target_func() { //Accessing is_active from the debugger *could* lead to unexpected //results e.g. a lost write or outdated data is read. is_active = true; //Accessing "is_active" (read or write) from the debugger at this //point is considered safe e.g. correct value is displayed. } 4 Intel C++ Compiler This section summarizes changes, new features and late-breaking news about the Intel C++ Compiler. 4.1 Compatibility In version 11.0, the IA-32 architecture default for code generation changed to assume that Intel Streaming SIMD Extensions 2 (Intel SSE2) instructions are supported by the processor on which the application is run. See below for more information. 4.2 New and Changed Features C++ Composer XE 2013 now contains Intel C++ Compiler XE The following features are new or significantly enhanced in this version. For more information on these features, please refer to the documentation. Support for Intel MIC architecture, both via offload (pragmas/keywords) and native (with mmic) compilation o Language Extensions for Offload o Offload Extensions for Data Marshaling (Non-shared memory) method o Offload Extensions for Virtual-Shared memory method Improved support for 3 rd Generation Intel Core processor family (-xcore-avx-i and axcore-avx-i) and future Intel processors supporting Intel Advanced Vector Extensions 2 (Intel AVX2) (-xcore-avx2 and axcore-avx2) Features from C++11 (-std=c++0x) o Additional type traits o Uniform initialization o Generalized constant expressions (partial support) o noexcept o Range based for loops o Conversions of lambdas to function pointers o Implicit move constructors and move assignment operators o Support for C++11 features in gcc 4.6 and 4.7 headers Out-of-bounds memory checking (-check-pointers) Installation Guide and Release Notes 24

25 More options for controlling the analysis for Static Analysis (-diag-enable sc- {full concise precise}) Inline assembly and intrinsic support for Intel architecture code named Broadwell added to Composer XE 2013 Update 1 Some new instructions have been added in the upcoming Intel architecture code named Broadwell. Composer XE 2013 Update 1 has added inline assembly and intrinsic support for these instructions. Intrinsics are defined in immintrin.h. extern int _rdseed16_step(unsigned short *random_val); extern int _rdseed32_step(unsigned int *random_val); extern int _rdseed64_step(unsigned int64 *random_val); These intrinsics generate random numbers of 16/32/64 bit wide random integers. These intrinsics are mapped to the hardware instruction RDSEED. The generated random value is written to the given memory location and the success status is returned - 1if the hardware returned a valid random value, and 0 otherwise. The difference between rdseed and rdrand intrinsics is that rdseed intrinsics meet the NIST SP B and NIST SP C standards, while the rdrand meets the NIST SP A standard. extern unsigned char _addcarry_u32(unsigned char c_in, unsigned int src1, unsigned int src2, unsigned int *sum_out); extern unsigned char _addcarry_u64(unsigned char c_in, unsigned int64 src1, unsigned int64 src2, unsigned int64 *sum_out); The intrinsic computes the sum of two 32/64 bit wide integer values (src1, src2) and a carryin value. The carry-in value is considered 1 for any non-zero c_in input value or 0 otherwise. The sum is stored to a memory location referenced by sum_out argument: *sum_out = src1 + src2 + (c_in!=0? 1 : 0) The intrinsic does not perform validness check of a memory address pointed by sum_out thus it cannot be used to find out if a sum produces carry-out without storing result of the sum. The return value of the intrinsic is a carry-out value generated by sum. The sum result is stored into memory location pointed by sum_out argument. extern unsigned char _subborrow_u32(unsigned char b_in, unsigned int src1, unsigned int src2, unsigned int *diff_out); extern unsigned char _subborrow_u64(unsigned char b_in, unsigned int64 src1, unsigned int64 src2, unsigned int64 *diff_out); Installation Guide and Release Notes 25

26 The intrinsic computes the sum of a 32/64 bit wide unsigned integer value src2 and a borrow-in value and then subtracts the result of the sum from the 32/64 bit wide unsigned integer value src1. The borrow-in value is considered 1 for any non-zero b_in input value or 0 otherwise. The difference is then stored to a memory location referenced by diff_out argument: *diff_out = src1 + (src2 + (b_in!=0? 1 : 0)) The intrinsic does not perform validness check of a memory address pointed by diff_out thus it cannot be used to find out if a subtraction produces borrow-out without storing the result of the subtraction. The return value of the intrinsic is a borrow-out value generated by subtraction. The result of the subtraction is stored into memory location pointed by the diff_out argument. extern unsigned char _addcarryx_u32(unsigned char c_in, unsigned int src1, unsigned int src2, unsigned int *sum_out); extern unsigned char _addcarryx_u64(unsigned char c_in, unsigned int64 src1, unsigned int64 src2, unsigned int64 *sum_out); The intrinsic computes sum of two 32/64 bit wide integer values (src1, src2) and a carry-in value. The carry-in value is considered 1 for any non-zero c_in input value or 0 otherwise. The sum is stored to a memory location referenced by sum_out argument: *sum_out = src1 + src2 + (c_in!=0? 1 : 0) The intrinsic does not perform validness check of a memory address pointed by sum_out thus it cannot be used to find out if a sum produces carry-out without storing the result of the sum. The intrinsic is translated to either a ADCX or ADOX instruction depending on compiler s decision. By their design these instructions allow running of two interleaved add-with-carry instruction sequences in parallel via using ADCX and ADOX instructions for these sequences respectively. The return value of the intrinsic is the carry-out value generated by the sum. The sum result is stored into memory location pointed by the sum_out argument. New _MM_HINT_ET0 hint to _mm_prefetch instrinsic The _MM_HINT_ET0 hint makes the intrinsic being lowered to the instruction PREFETCHW which is supported by the Intel architecture code name Broadwell. Check if the target CPU supports the instruction PREFETCHW before using _MM_HINT_ET core_4th_gen_avx added for manual cpu dispatch in Composer XE 2013 Update 1 The cpuid core_4th_gen_avx is now supported for use with the cpu_dispatch and cpu_specific manual cpu dispatch mechanisms. This cpuid targets processors that support Intel Advanced Vector Extensions 2 (Intel AVX2). Installation Guide and Release Notes 26