Please! Can someone make UVM easy to use?

Transcription

1 Please! Can someone make UVM easy to use? Rich Edelman Raghu Ardeishar Mentor Graphics Accellera Systems Initiative 1

2 Main Concerns Unnecessary use of Parameterized classes Confusing sequences Config DB issues Heavy use of Macros Accellera Systems Initiative 2

3 Parameterized Classes Parameterized classes are very powerful but misunderstood Not needed in all cases Overriding becomes problematic Layering UVM makes is harder Complicated use model with factory Use it only when needed Accellera Systems Initiative 3

4 Parameterized Classes A couple of examples Class parameterized by value class classvalue #(int V = 3) int delay = V; Class parameterized by type class classtype #(type T = int) T delay; First Principles : Lets look at polymorphism Accellera Systems Initiative 4

5 Parameterized Classes Basic Polymorphism class classvalue; class classvaluenew extends classvalue classvalue cv = new; classvaluenew cvn = new; cv = cvn; classvalue classvaluenew baseclass newclassvalue is an extension of classvalue Can be assigned to classvalue They are type compatible Accellera Systems Initiative 5

6 Parameterized Classes Now with value parameters class classvalue (int V = 3); classvalue baseclass classvalue classvalue #(3) cv3 = new(); classvalue #(4) cv4 = new(); classvalue#(3) classvalue#(4) cv3 = cv4; //ERRRRROR Not type compatible Not Possible Will compile and load Will result in a run time Fatal cv3 and cv4 are not type compatible Accellera Systems Initiative 6

7 Parameterized Classes Now with type parameters class classtype (type T = int); classtype baseclass classtype classtype #(int) cint = new(); classtype #(integer) cinteger = new(); classtype#(int) classtype#(integer) cint = cinteger; //ERRRRROR Not type compatible Not Possible Will compile and load Will result in a run time Fatal cint and cinteger are not type compatible Accellera Systems Initiative 7

8 Parameterized Classes Do you really need a parameter? Only if you need a elaboration time constant Most likely you need a dynamic variable class classvalue; int T = 3; class classvaluenew extends classvalue int T = 4; classvalue cv = new; classvaluenew cvn = new; cv = cvn; Accellera Systems Initiative 8

9 Parameterized Classes Layer on UVM and you raise the level of complication Add the factory and you get a perfect storm Macros (in parameterized classes) don t work as expected Or at least as most people expect!! Lets first look at regular UVM classes p and pd are type compatible class packet extends uvm_object ; `uvm_object_utils(packet). class packetd extends packet; `uvm_object_utils(packetd) packet p = new(); packetd pd = new(); p = pd; //Works!! Accellera Systems Initiative 9

10 Parameterized Classes Util Macros work well in non-param classes Use it to register with factory Use uvm_top.print_topology() and factory.print() to get details virtual function end_of_elaboration_phase(uvm_phase phase) ; uvm_top.print_topology(); factory.print();. Macros (in parameterized classes) will not create all the necessary routines!! Factory override print will NOT show anything! To see details you will need to NEED to register MANUALLY Accellera Systems Initiative 10

11 Parameterized Classes Don t use *_param_utils, It will not help Write this simple code as shown below factory.print() will show overrides class driverb #(type T = int) extends uvm_driver #(T); //`uvm_component_param_utils(driverb#(t)) localparam type_name = $sformatf("driverb#(%s)", T::type_name); typedef uvm_component_registry #(driverb#(t), type_name) type_id; static function type_id get_type(); return type_id::get(); endfunction virtual function uvm_object_wrapper get_object_type(); return type_id::get(); endfunction virtual function string get_type_name(); return type_name; endfunction Accellera Systems Initiative 11

12 Parameterized Classes But the inherent issues remain driverd2packet and driverd2packetd are not type compatible class driverd2 #(type T = uvm_object) extends driverb #(T);. driverb baseclass driverb typedef driverd2#(packet) driverd2packet; typedef driverd2#(packetd) driverd2packetd; driverd2packet driverd2packetd Not type compatible driverd2 cannot accept packets of different types w/o some more work Accellera Systems Initiative 12

13 Parameterized Classes Deparameterized the class class classtype #(type T = int); T mydelay; function calcdelay(); class config env_config extends uvm_object rand int delay; class classtype; int mydelay ; env_config e; uvm_config_db :: get( e,e); function new ( ); mydelay = e.delay; endfunction Use uvm_config_db to get the parameter from config objects set in the environment Accellera Systems Initiative 13

14 Parameterized Tests/Sequences Sequences and Parameterization Not always needed Tempting to parameterize tests/sequences based on bus width, LANES etc Will create issues while creating sequences to run on interfaces with different parameters Solution: Instantiate with max possible bus widths and control individual dimensions using environment configs Accellera Systems Initiative 14

15 Parameterized Sequences class test #(Int LANES = 2, int PIPE_BYTES_MAX = 1, int NUM_OF_FUNCTIONS = 1) extends uvm_test; typedef pcieseq #(LANES,PIPE_BYTE_MAX,NUM_OF_FUNCTIONS) pcieseqt; task run_phase; pcieseqt pcieseq = pcieseqt::type_id ; pcieseq.start(sequencer); endtask Task and sequence have become more complicated to extend and override Cannot run it on agents/sequencers with different parameters Will need to create a new sequence for each variation of parameters Code Bloat Accellera Systems Initiative 15

16 Parameterized test simplified class env_config extends uvm_object rand int LANES; rand int PIPE_BYTE_MAX; rand int NUM_OF_FUNCTIONS; module top; initial begin env_config ec = new(); randomize(ec) with ; uvm_config_db #(env_config):: set(uvm_root::get(), *, ec, ec); end endmodule env_config Set env_config in config_db Get env_config from config_db Extract properties from env_config Remove parameters from test or sequences Use configs to set and retrieve parameters. Use the same sequence/test class test extends uvm_test; int LANES; int PIPE_BYTE_MAX; int NUM_OF_FUNCTIONS; typedef pcieseq pcieseqt; task run_phase; pcieseqt pcieseq = pcieseqt::type_id ; env_config ec; uvm_config_db :: get( ec,e); LANES = ec.lanes; PIPE_BYTE_MAX = ec.pipe_byte_max; pcieseq.start(sequencer); endtask Accellera Systems Initiative 16

17 Config DB Very useful BUT very Often Misused/Misunderstood Very useful but expensive during lookups Use to set and get interfaces Use to set and get configuration objects Do not use to set and get integers, strings Do not call get multiple times eg, in a for/foreach loop Accellera Systems Initiative 17

18 Config DB Can you get it to work? Sure, But it all the effort with paths worth it? static function void set ( uvm_component cntxt, string inst_name, string field_name, T value) Inside a class to set the value: uvm_config_db #(type)::set(this, *.pathname, label,value); Outside a class to set the value: uvm_config_db #(type)::set(uvm_root::get(), *.pathname, label,value); Inside a class to set the value: To get the value uvm_config_db #(type)::get(this,, label,value) Accellera Systems Initiative 18

19 Config DB Use unique names for labels Avoid variables with same names in different instance paths Use * for instance names avoiding paths Big Hammer but worthwhile in the long run Puts the variable in Global space uvm_config_db #(virtual interfacename) ::set (uvm_root::get(), *, pcieintf1, pcieintf1); uvm_config_db #(virtual interfacename) ::set (uvm_root::get(), *, pcieintf2, pcieintf2); Get the interface uvm_config_db #(type)::get(uvm_root::get(), *, pcieintf1, pcieintf); Use +UVM_CONFIG_DB_TRACE (simulator command line argument) to debug set/get issues Accellera Systems Initiative 19

20 Config DB Avoid using automated macros with config_db Example: uvm_agent is_active Mistaken assumption that `uvm_component_utils implements uvm_config_db::get Implement get manually in the env or test OR Use `uvm_field_enum(uvm_active_passive_enum, is_active, UVM_ALL_ON) Accellera Systems Initiative 20

21 Finally Macros! To use or not to use? Well, Depends on the macro `uvm_do AVOID You don t need a macro to execute sequences They expand into complicated code Do the following instead task sequence::body; myitem item; `uvm_do(item) // AVOID endtask task sequence::body; myitem item = myitem::type_id::create( ); start_item(item); randomize(item); finish_item(item); endtask task sequence::body; myseq seq; `uvm_do(seq) // AVOID endtask task sequence::body; myseq seq = myseq::type_id::create( ); seq.start( ); endtask Accellera Systems Initiative 21

22 Finally Macros! `uvm_field AVOID like the Plague Implements copy, compare, pack, unpack etc Code bloat and very hard to debug Simulators have optimized a lot for performance but still is a debug issue Write the routines manually LOT easier to debug Refer to Are OVM and UVM Macros Evil? A Cost-Benefit Analysis by Adam Erikson Accellera Systems Initiative 22

23 Questions Accellera Systems Initiative 23