Easier UVM Functional Verification for Mainstream Designers
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1 Easier UVM Functional Verification for Mainstream Designers John Aynsley, Doulos 1
2 Easier UVM Functional Verification for Mainstream Designers Introducing UVM Transactions and Components Sequencers and Drivers Configurations and the Factory What next?
3 Easier UVM? Aimed at mainstream Verilog & VHDL users Goal = Reduce UVM to a set of simple concepts and coding idioms Easier UVM is UVM Use more features of UVM as you learn Learning UVM is still not easy 3
4 Why UVM? UVM = Universal Verification Methodology The big wins are Verification quality Reusable verification environment Testbench reuse Knowhow reuse 4
5 UVM Highlights 1 Constrained random verification Configurable, flexible, test benches A standard approach consistency and uniformity Open source SystemVerilog Base Class Library Supported by all the main vendors 5
6 UVM Highlights 2 Separation of tests from test bench Transaction-level communication (TLM) Layered sequential stimulus Message reporting Register layer 6
7 Test versus Testbench Test writer Tests define differences Verification specialist Allows for unanticipated changes 7
8 Testbench Structure A consistent spatial structure uvm_env uvm_agent 8
9 Quasi-static vs Dynamic Objects 9
10 Quasi-static vs Dynamic Objects 10
11 Quasi-static vs Dynamic Objects 11
12 Quasi-static vs Dynamic Objects class my_comp extends uvm_component; `uvm_component_utils(my_comp) Pattern 1 function new (string name, uvm_component parent); super.new(name, parent); endclass class my_tx extends uvm_sequence_item; `uvm_object_utils(my_tx) function new (string name = ""); super.new(name); endclass Pattern 2 12
13 Classes Permit Extensions class my_tx extends uvm_sequence_item; `uvm_object_utils(my_tx) Original VIP function new (string name = ""); super.new(name); endclass Extensions class refined_tx extends my_tx; `uvm_object_utils(refined_tx) function new (string name = ""); super.new(name); some_type extra_property; constraint C { } endclass Polymorphism Specific test 13
14 Transactions Methods class my_tx extends uvm_sequence_item; `uvm_object_utils(my_tx) Pattern 2a rand bit cmd; rand int addr; rand int data; constraint c_addr { addr >= 0; addr < 256; } constraint c_data { data >= 0; data < 256; } function new (string name = ""); super.new(name); function string convert2string; function void do_copy( uvm_object rhs ); function bit do_compare( uvm_object rhs, uvm_comparer comparer ); endclass 14
15 Execution Phases A consistent temporal structure 15
16 Phase Methods of a Component class my_comp extends uvm_component; `uvm_component_utils(my_comp) Pattern 1 function new (string name, uvm_component parent); super.new(name, parent); function void build_phase (uvm_phase phase); super.build_phase(phase); function void connect_phase (uvm_phase phase); task run_phase (uvm_phase phase); endtask function void report_phase (uvm_phase phase); endclass 16
17 Build Phase class my_agent extends uvm_agent; `uvm_component_utils(my_agent) my_driver driv; my_sequencer seqr; function void build_phase (uvm_phase phase); super.build_phase(phase); driv = my_driver::type_id::create( driv", this); seqr = my_sequencer::type_id::create( seqr", this); Factory-made components driv seqr function void connect_phase (uvm_phase phase); b.p_port.connect( c.q_export ); 17
18 Connect Phase class my_agent extends uvm_agent; `uvm_component_utils(my_agent) my_driver driv; my_sequencer seqr; function void build_phase (uvm_phase phase); super.build_phase(phase); driv = my_driver::type_id::create( driv", this); seqr = my_sequencer::type_id::create( seqr", this); driv Port seqr Export function void connect_phase (uvm_phase phase); driv.seq_item_port.connect( seqr.seq_item_export ); 18
19 Transaction-Level Connections port.put(tx); Port Push Export task put(input my_tx tx); endtask port.get(tx); Port Pull Export task get(output my_tx tx); endtask 19
20 Analysis Ports Broadcast function void write(input my_tx tx); port.write(tx); function void write(input my_tx tx); Analysis port Analysis export / imp function void write(input my_tx tx); Readonly, non-blocking 20
21 Run Phase class my_monitor extends uvm_component; `uvm_component_utils(my_monitor) uvm_analysis_port #(my_tx) port; function void build_phase (uvm_phase phase); super.build_phase(phase); port = new("port", this); mon chk task run_phase (uvm_phase phase); my_tx tx; tx = my_tx::type_id::create("tx"); port.write(tx); Port Export endtask 21
22 Constrained Random Generation Populate/randomize configuration objects Set factory overrides Top-down build Factory-made sequences Factory-made transactions Constraints 22
23 Agent Architecture Agent Agent Agent Checking and Coverage Constrained random stimulus generation Agent-per-interface 23
24 Sequence versus Sequencer x count Sequences Transactions 24
25 Sequences Function object can be constrained or overridden body() body() body() body() Sequence of transactions 25
26 Transaction vs Sequence class my_tx extends uvm_sequence_item; `uvm_object_utils(my_tx) Pattern 2a function new (string name = ""); super.new(name); endclass class my_seq extends uvm_sequence #(my_tx); `uvm_object_utils(my_seq) Pattern 2b function new (string name = ""); super.new(name); task body; endtask endclass 26
27 Body of a Sequence class my_seq extends uvm_sequence #(my_tx); `uvm_object_utils(my_seq) function new (string name = ""); super.new(name); Pattern 2b task body; repeat (6) begin req = my_tx::type_id::create("req"); Factory-made transaction Handshake with driver start_item(req); assert( req.randomize() with { data > 127; } ); finish_item(req); end endtask Late randomization endclass 27
28 Sequencer Driver DUT Sequences TLM port-export Transactions Virtual interface SystemVerilog interface SystemVerilog module 28
29 The Configuration Database set Scope Scope Scope Name = Value Name = Value Name = Value get x count Sequences 29
30 Driver 1 class my_driver extends uvm_driver #(my_tx); `uvm_component_utils(my_driver) Pattern 1 virtual dut_if dut_vi; Driver-DUT comms via interface function void build_phase( uvm_phase phase ); super.build_phase(phase); uvm_config_db #(virtual dut_if)::get( this, "", "dut_vi", dut_vi ); Interface set using config_db 30
31 Driver 2 task run_phase( uvm_phase phase ); forever Sequencer-driver comms via implicit port begin dut_vi.clock); dut_vi.cmd = req.cmd; dut_vi.addr = req.addr; dut_vi.data = req.data; Wiggle DUT pins through interface seq_item_port.item_done(); end endtask endclass or item_done(rsp); 31
32 Configuration Object class my_top_seq_config extends uvm_object; rand int count; rand A set of parameters / generics endclass 32
33 Populate Configuration from a Test class my_test extends uvm_test; Pattern 1 `uvm_component_utils(my_test) function void build_phase (uvm_phase phase); super.build_phase(phase); begin my_top_seq_config config = new; config.count = 6; Could randomize the configuration uvm_config_db #(my_top_seq_config)::set(this, "*.*seq*", "config", config); end env = top::type_id::create("env", this); cf. parameter overrides / generic map 33
34 Retrieve Configuration Information class my_top_seq extends uvm_sequence #(my_top_tx); Pattern 2b `uvm_object_utils(my_top_seq) `uvm_declare_p_sequencer(my_top_seqr) rand int count; constraint how_many { count inside { [4:10] }; } task body; my_top_seq_config config; if ( uvm_config_db #(my_top_seq_config)::get(p_sequencer, "", "config", config) ) count = config.count; endtask 34
35 Factory Overrides class my_seq extends uvm_sequence #(my_tx); `uvm_object_utils(my_seq) Pattern 2b function new (string name = ""); super.new(name); task body; req = my_tx::type_id::create("req"); endtask endclass Pattern 1 class my_test extends uvm_test; function void build_phase (uvm_phase phase); my_tx::type_id::set_type_override( alt_tx::get_type() ); my_component::type_id::set_inst_override( alt_component::get_type(), "subsys.*", this ); 35
36 Start Sequence from Test class my_test extends uvm_test; `uvm_component_utils(my_test) my_env env; task run_phase( uvm_phase phase ); my_top_seq seq; seq = my_top_seq::type_id::create("seq"); Pattern 1 assert( seq.randomize() with { count < 8; } ); Randomize with constraint seq.start( env.sequencer ); endtask Start sequence on sequencer 36
37 Running the Test module top; import uvm_pkg::*; import my_pkg::*; UVM package dut_if dut_if1 (); dut dut1 (._if(dut_if1) ); SV interface Design-Under-Test initial begin uvm_config_db #(virtual dut_if)::set(null, "*", "dut_vi", dut_if1); end run_test(); endmodule 37
38 End-of-Test Test ends when all objections dropped task run_phase(uvm_phase phase); task dut_vi.clock); uvm_test_done.raise_objection(this); forever repeat(n) begin begin seq_item_port.get_next_item(req); req = my_top_req::type_id::create("req"); phase.raise_objection(this); start_item(req); assert( req.randomize() dut_vi.clock); finish_item(req); dut_vi.data = req.data; end phase.drop_objection(this); uvm_test_done.drop_objection(this); endtask end endtask 38
39 Summary of Coding Idioms class my_comp extends uvm_component; `uvm_component_utils(my_comp) Pattern 1 function new(string name, uvm_component parent); super.new(name, parent); function void build_phase(); endclass Pattern 2a class my_tx extends uvm_sequence_item; `uvm_object_utils(my_tx) Pattern 2b class my_seq extends uvm_sequence #(my_tx); `uvm_object_utils(my_seq) function new (string name = ""); super.new(name); endclass function new(string name = ""); super.new(name); task body; endclass 39
40 Other Features of UVM Message reporting Further sequence mechanisms (lock, arbitration, sequence library) User-defined phasing Further transaction-level communication, including TLM-2.0 Printing, recording, and packing/unpacking of transactions Synchronization mechanisms (events, barriers, heartbeats) Customized reporting and report catching Command line processor The register abstraction layer 40
41 What Next? Download UVM Download Easier UVM examples Future webinars from Doulos 41
42 SystemVerilog Training Portfolio Public Classes Nothing SystemVerilog for FPGA/ASIC Design RTL and test benches Verilog Comprehensive SystemVerilog SV for Designers Class-based verification UVM Adopter Class 42
43 43
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