I Didn t Know Constraints Could Do That!

Transcription

1 I Didn t Know Constraints Could Do That! John Dickol Samsung Austin R&D Center 6 February 2018 DVClub Europe DVClub Europe 6 Feb

2 Agenda Introduction SystemVerilog Constraint Techniques Constraint Examples DVClub Europe 6 Feb

3 Introduction SystemVerilog constraint solvers continue to improve Solvers can handle more complex constraint problems Why use complex constraints? Use constraints to define legal stimulus Add constraints to steer stimulus Complex stimulus needs complex constraints DVClub Europe 6 Feb

4 Constraint Techniques DVClub Europe 6 Feb

5 Constraint Basics SystemVerilog constraints are declarative, not procedural. Describe what you want - Solver will figure out how Constraints specify expressions which must be true Can be any SV expression using variables & constants of integral type Constraint solver chooses values for random variables to ensure all constraints are satisfied All constraints solved simultaneously (usually some exceptions) Full specification in SystemVerilog Language Reference Latest version: IEEE Std Download free copy from IEEE Get Program: DVClub Europe 6 Feb

6 Constraint Expressions Simple Complex 1; 0; x == 1; x inside {[0:10]; x < y; (x + y) == z; if(a>b) c<d; if(x==y) { 0; foreach(n_txns_per_slave[s]) { n_txns_per_slave[s] == txn_map.sum with( (item.index(2) == s)? item : 0); ); map.ranges.or(r) with ( item.addr inside {[r.start_addr : (r.end_addr - item.size)] && item.cache_type == r.cache_type ); DVClub Europe 6 Feb

7 Soft Constraints Are applied only if not contradicted by other constraints with higher priority In general, last constraint specified has higher priority See SV LRM for complete list of priorities Good for specifying default values for UVM sequence/sequence_item which can be overridden in higher-level sequence DVClub Europe 6 Feb

8 Soft Constraint Example class myseq extends uvm_sequence#(mytxn); rand int count // number of transactions Default constraint for count Soft constraint may be overridden constraint c_count { soft count inside {[10:20]; task body; mytxn txn; repeat(count) begin `uvm_do(txn) end endtask endclass class topseq extends uvm_sequence#(mytxn); task body; myseq seq; `uvm_do(seq) `uvm_do_with(seq, {count == 1000; endtask endclass Default soft constraint applies Inline hard constraint overrides soft constraint DVClub Europe 6 Feb

9 Unique Constraints Constrain set of variables to have unique values: Scalar integral values Unpacked arrays of integral values rand int x, y, z; rand int arr[10]; int q[$] = {1, 2, 7, 11; constraint c_unique { unique {x, y, z; unique {arr; unique {x, y, arr; unique {x, y, q; Equivalent to: x!=y; y!=z; z!=x; Fill arr with unique values Can mix scalars and arrays Pick x & y not equal to elements of non-rand queue DVClub Europe 6 Feb

10 Array Iterative Constraints foreach constraint applies to each element of array Array size can be constrained LRM requirement: array size solved before iterative constraints rand int arr[10]; rand int q[$]; constraint c_foreach { foreach(arr[i]) arr[i] inside {[0:15]; q.size() inside {[5:10]; Constrain each array element Constrain queue size foreach(q[i]) { if(i>0) q[i] > q[i-1]; Create sorted queue: q[0] < q[1], q[2] Constraint guard avoids index out of bounds error DVClub Europe 6 Feb

11 Array Reduction Constraints Operate on unpacked arrays of integral values Apply specified operation between each element of the array rand int a[10]; a.sum == a[0] + a[1] + a.product == a[0] * a[1] * a.and == a[0] & a[1] & a.or == a[0] a[1] a.xor == a[0] ^ a[1] ^ Methods return single value of the same type as array element i.e sum of int returns int. xor of bit returns bit, etc. Optional with expression applied to each element before reduction operation Inside with expression: item refers to current array element item.index refers to current array index DVClub Europe 6 Feb

12 Array Reduction Constraint Examples Constrain number of 1s in array of bits: rand bit bq[$]; constraint c_sum { bq.size inside {[10:20]; (bq.sum with (int (item))) == 7; Constrain sum of first 3 elements of array: sum() of bit is single bit Cast to int to avoid overflow sum with( ) equivalent to: foreach(a[i]) if(i<3) sum+= a[i] rand int a[10]; constraint c_sum_first_3 { (a.sum with ((item.index < 3)? item : 0)) == 10; item.index equivalent to i item equivalent to a[i] DVClub Europe 6 Feb

13 Global (Hierarchical) Constraints Class with rand variables may be rand member of another class When top-level object is randomized, all rand class members are also randomized Top-level object may constrain lower-level object variables DVClub Europe 6 Feb

14 Global Constraint Example: Line Drawing Rand instances of XY point class class XY; rand int x; rand int y; constraint c_valid { x inside {[0:100]; y inside {[0:100]; endclass class Line; rand XY pt1; rand XY pt2; rand enum {HORIZONTAL, VERTICAL direction; function new; if(pt1==null) pt1 = new; if(pt2==null) pt2 = new; endfunction constraint c_valid { if(direction == VERTICAL) { pt1.x == pt2.x; pt1.y!= pt2.y; Top-level object constrains lower-level if(direction == HORIZONTAL) { pt1.y == pt2.y; pt1.x!= pt2.x; endclass DVClub Europe 6 Feb

15 Reusing Constraints: Policy Classes Problem: Define constraints once and reuse in multiple objects Add additional constraints to object at runtime Implementation: Variation of hierarchical constraints: Lower-level object constrains parent object Define reusable constraints in policy class container Policy classes extended from common base class item variable in policy class refers to parent object Parent object has rand queue of policy base class More info in DVCon 2015 paper: SystemVerilog Constraint Layering via Reusable Randomization Policy Classes DVClub Europe 6 Feb

16 Policy Class Example class rand_policy_base #(type T=uvm_object); T item; virtual function void set_item(t item); this.item = item; endfunction endclass item refers to parent Line object Rand queue of policy base class class line_direction_policy extends rand_policy_base#(line); constraint c_direction { item.direction dist { Line::VERT := 5, Line::HORIZ := 1 ; endclass class Line; rand enum {HORIZ, VERT direction; rand rand_policy_base#(line) pcy[$]; function void pre_randomize; foreach(pcy[i]) pcy[i].set_item(this); endfunction... endclass Test case Line l = new; line_direction_policy dir_pcy = new; l.pcy = {dir_pcy; l.randomize; Set item in policy objects to point to this Line instance Add policy to queue DVClub Europe 6 Feb

17 Example 1: Bus Interconnect Testbench DVClub Europe 6 Feb

18 Bus Interconnect Testbench Master Agent Master Agent Tests may want to control: Total number of transactions for all masters Number of transactions per master Bus Interconnect DUT Number of transactions per slave Number of transactions from one master to a particular slave Slave Agent Slave Agent Use/avoid using certain masters or slaves Etc. DVClub Europe 6 Feb

19 Bus Interconnect Configuration Constraints Use 2-D array to model number of transactions rand int unsigned txn_map[n_master][n_slave]; Add rand variables and constraints for provide knobs controllable by test S0 S1 S2 S3 S4 S5 Total txns per master Sum rows to get txns per master M Sum columns to get txns per slave M M M M Sum entire array to get total txns Total Txns per slave Total txns 1151 DVClub Europe 6 Feb

20 Constrain Total Number of Transactions class ms_config#(n_master=5, N_SLAVE=6); rand int unsigned txn_map[n_master][n_slave]; rand int unsigned total_txns; sum with( )is equivalent to: foreach(txn_map[m,s]) sum += txn_map[m][s]; constraint c_valid { total_txns == txn_map.sum; endclass DVClub Europe 6 Feb

21 Constrain Transactions Per Master class ms_config#(n_master=5, N_SLAVE=6); rand int unsigned txn_map[n_master][n_slave]; rand int unsigned n_txns_per_master[n_master]; Sum each row of txn_map array constraint c_valid { foreach(n_txns_per_master[m]) { n_txns_per_master[m] == txn_map[m].sum; endclass DVClub Europe 6 Feb

22 Constrain Transactions Per Slave class ms_config#(n_master=5, N_SLAVE=6);... rand int unsigned n_txns_per_slave[n_slave]; sum with( ) is equivalent to: foreach(txn_map[m,s]) if(s == s) sum += txn_map[m][s]; else sum += 0; constraint c_valid { foreach(n_txns_per_slave[s]) { n_txns_per_slave[s] == txn_map.sum with( (item.index(2) == s)? item : 0); ); endclass item.index(2) returns Index for 2 nd array dimension; DVClub Europe 6 Feb

23 Constrain Individual Masters/Slaves class ms_config#(n_master=5, N_SLAVE=6);... rand bit use_master[n_master]; rand bit use_slave[n_master]; rand int unsigned use_n_masters; rand int unsigned use_n_slaves; constraint c_valid { foreach(use_master[m]) { (use_master[m] == 1) == (n_txns_per_master[m] > 0); use_n_masters == use_master.sum with (int'(item)); Master is used if it has at least 1 transaction Count number of used masters foreach(use_slave[s]) { (use_slave[s] == 1) == (n_txns_per_slave[s] > 0); use_n_slaves == use_slave.sum with (int'(item)) endclass DVClub Europe 6 Feb

24 Test Scenario Constraints ms_config cfg = new; cfg.randomize with { total_txns == 10000; use_n_masters inside {[2:4]; use_master[1] == 1; use_slave[3] == 0; Generate a total of transactions Use between 2 and 4 masters Use Master 1 Don t use Slave 3 DVClub Europe 6 Feb

25 Command Line Control of Constraints function void ms_config::get_plusargs; if($value$plusargs("total_txns=%d", total_txns)) total_txns.rand_mode(0); if($value$plusargs("use_n_masters=%d", use_n_masters)) use_n_masters.rand_mode(0); foreach(use_master[m]) begin string format = $sformatf("use_master[%0d]=%%b", m); if($value$plusargs(format, use_master[m])) use_master[m].rand_mode(0); end... endfunction If plusarg specified on command line, disable randomization for corresponding variable Compute plusarg names for individual array elements Test case configuration ms_config cfg = new; cfg.get_plusargs; cfg.randomize; Simulator command line {irun simv vsim +total_txns= use_n_masters=3 +use_master[1]=1... DVClub Europe 6 Feb

26 Example 2: Memory Map Generation See Appendix DVClub Europe 6 Feb

27 Summary Constraint techniques: Soft constraints Unique constraints Array constraints (foreach, size) Array reduction constraints (sum, and, ) Reusable constraints: policy classes Constraint solver can handle complex problems use it! DVClub Europe 6 Feb

28 Thank You DVClub Europe 6 Feb

29 Appendix DVClub Europe 6 Feb

30 Example 2: Memory Map Generation DVClub Europe 6 Feb

31 Memory Map Generation Memory Management Unit Features: 32-bit address 3 address range (page) sizes: 1KB, 4KB, 1MB Range starting address aligned to range size Range can be Non-cacheable, Write-through cacheable, write-back cacheable Problem: Generate interesting sets of non-overlapping memory ranges Select memory transactions from mapped ranges DVClub Europe 6 Feb

32 Memory Map Generation Implementation: mem_range class describes single range mem_map class has rand array of mem_range (plus constraints) mem_range array fixed maximum size; randomize number of valid ranges (workaround for solve size before foreach limitation) Configurable constraint policy classes select number & types of ranges map range[0] range[1] range[2] range[3] range[n-1] range[n] valid size cache... valid size cache... valid size cache... valid size cache invalid size cache... invalid size cache... DVClub Europe 6 Feb

33 Memory Range Class typedef bit [31:0] addr_t; typedef enum addr_t { SIZE_1K='h400, SIZE_4K='h1000, SIZE_1M='h size_t; typedef enum { NONCACHEABLE, WT_CACHEABLE, WB_CACHEABLE cache_t; This range is valid (will be constrained) class mem_range; rand bit rand size_t rand addr_t rand addr_t rand cache_t valid; size; start_addr; end_addr; cache_type; constraint c_valid { size == (1 + end_addr - start_addr); (start_addr & (size - 1)) == 0; endclass Ensure size, start, end are in sync Size-align start address DVClub Europe 6 Feb

34 Memory Map Class class mem_map; int max_ranges = 10; rand int num_ranges; rand mem_range ranges[]; rand rand_policy_base#(mem_map) pcy[$]; function new(int max_ranges); this.max_ranges = max_ranges; endfunction function void pre_randomize; ranges = new[max_ranges]; foreach (ranges[i]) ranges[i] = new(); foreach(pcy[i]) pcy[i].set_item(this); endfunction... Rand array of mem_ranges Ensure all mem_range instances are constructed before randomizing DVClub Europe 6 Feb

35 Memory Map Class class mem_map; int max_ranges = 10; rand int num_ranges; rand mem_range ranges[]; rand rand_policy_base#(mem_map) pcy[$]; Non-overlapping valid ranges sorted by address function new(int max_ranges); this.max_ranges = max_ranges; endfunction function void pre_randomize; ranges = new[max_ranges]; foreach (ranges[i]) ranges[i] = new(); foreach(pcy[i]) pcy[i].set_item(this); endfunction... Ensure first num_ranges entries are valid, remainder invalid... constraint c_valid { foreach(ranges[i]) if(i>0) { if(ranges[i].valid) ranges[i].start_addr > ranges[i-1].end_addr; num_ranges inside {[1:max_ranges]; foreach(ranges[i]) { ranges[i].valid == ((i < num_ranges)? 1 : 0); endclass DVClub Europe 6 Feb

36 Memory Range Allocation Policies Allocate between min and max pages of specified size class page_count_policy extends rand_policy_base#(mem_map); addr_t size; int min; // minimum number of pages of given size int max; // maximum number of pages of given size Constrain number of valid pages of desired size constraint c_count { item.ranges.sum(r) with (int'(r.valid && (r.size == size))) inside {[min:max]; function new(addr_t size, int min, int max=min); this.size = size; this.min = min; this.max = max; endfunction endclass DVClub Europe 6 Feb

37 Memory Range Allocation Policies Allocate between min and max bytes of a specified cache type class cache_size_policy extends rand_policy_base#(mem_map); cache_t cache_type; addr_t min; addr_t max; constraint c_cache { item.ranges.sum(r) with ( (r.valid && (r.cache_type == cache_type))? r.size : 0 ) inside {[min:max]; Constrain number of valid pages of desired cache type function new(cache_t cache_type, addr_t min, addr_t max='1); this.cache_type = cache_type; this.min = min; this.max = max; endfunction endclass DVClub Europe 6 Feb

38 Configuring the Memory Map // Allocate memory map with: // Any number of 1K pages // At most 2 4KB pages // No 1MB pages // At least 4KB of non-cacheable memory // At least 8KB of write-back cacheable memory // No write-though cacheable memory Construct policies with desired characteristics mem_map map = new; page_count_policy count_4k_pcy = new(size_4k, 0, 2); page_count_policy count_1m_pcy = new(size_1m, 0); Add policies to map cache_size_policy NC_pcy = new(noncacheable, SIZE_4K); cache_size_policy WB_pcy = new(wb_cacheable, 2*SIZE_4K); cache_size_policy WT_pcy = new(wt_cacheable, 0,0); map.pcy = { NC_pcy, WB_pcy, WT_pcy, count_4k_pcy, count_1m_pcy; map.randomize; DVClub Europe 6 Feb

39 Using the Memory Map Problem: Generate Memory Transactions Using Memory Map Transactions may be 1, 2 or 4 bytes. All bytes of a transaction must be within a single memory range Transaction addresses must be size-aligned Transaction s cache type must match its memory range cache type Implementation Use policy class to inject memory map constraints into memory transaction DVClub Europe 6 Feb

40 Memory Transaction class mem_txn; rand addr_t addr; rand addr_t size; rand cache_t cache_type; rand rand_policy_base#(mem_txn) pcy[$]; Constrain sizes and alignment constraint c_size { size inside {1, 2, 4; constraint c_align { (addr & (size-1)) == 0; function void pre_randomize; foreach(pcy[i]) pcy[i].set_item(this); endfunction endclass DVClub Europe 6 Feb

41 Transaction Selection Policy class mem_txn; rand addr_t addr; rand addr_t size; rand cache_t cache_type; rand rand_policy_base#(mem_txn) pcy[$]; class txn_pick_policy extends rand_policy_base#(mem_txn); constraint c_size mem_map { size map; inside {1, 2, 4; constraint c_align { (addr & (size-1)) == 0; function new(mem_map map); function void pre_randomize; this.map = map; foreach(pcy[i]) endfunction pcy[i].set_item(this); endfunction endclass constraint c_pick { map.ranges.or(r) with ( item.addr inside {[r.start_addr : (r.end_addr - item.size)] && item.cache_type == r.cache_type ); endclass Use the policy when randomizing txn txn_pick_policy pick_pcy = new(mem_map); mem_txn txn = new; txn.pcy = {pick_pcy; txn.randomize; Non-rand mem_map used as state variable Use OR-reduction to constrain txn to fit within range with same cache type DVClub Europe 6 Feb