MR44V064A GENERAL DESCRIPTION FEATURES. FEDR44V064A-01 Issue Date: Apr. 22, k(8,192-Word 8-Bit) FeRAM (Ferroelectric Random Access Memory)

Size: px

Start display at page:

Download "MR44V064A GENERAL DESCRIPTION FEATURES. FEDR44V064A-01 Issue Date: Apr. 22, k(8,192-Word 8-Bit) FeRAM (Ferroelectric Random Access Memory)"

Angel Webster
5 years ago
Views:

1 64k(8,192-ord 8-Bit) FeM (Ferroelectric andom ccess Memory) Issue ate: pr. 22, 213 GENEL EIPION he is a nonvolatile 8,192-word x 8-bit ferroelectric random access memory (FeM) developed in the ferroelectric process and silicon-gate MO technology. he is accessed using wo-wire erial Interface ( I2 BU ).Unlike Ms, this device, whose cells are nonvolatile, eliminates battery backup required to hold data. his device has no mechanisms of erasing and programming memory cells and blocks, such as those used for various EEPOMs. herefore, the write cycle time can be equal to the read cycle time and the power consumption during a write can be reduced significantly. he can be used in various applications, because the device is guaranteed for the write/read tolerance of 1 12 cycles per bit and the rewrite count can be extended significantly. FEUE 8,192-word 8-bit configuration I2 BU Interface single 3.3 V typ (2.5V to 3.6V) power supply Operating frequency: 3.4MHz(Max) H-mode 4Hz(Max) F/-mode ead/write tolerance 1 12 cycles/bit ata retention 1 years Guaranteed operating temperature range 4 to 85 (Extended temperature version) Package options: 8-pin plastic OP (P-OP ) 1/16

2 PIN ONFIGUION 8-pin plastic OP 1 2 V V P L PIN EIPION Pin Name 2 L P V, V escription ddress ( input ) ddress pin indicates device address. hen ddress value is match the device address code from, the device will be selected. he address pins are pulled down internally. erial data input serial data output ( input / output ) is a bi-directional line for I2 interface. he output driver is open-drain. pull-up resistor is required. erial lock ( input ) erial lock is the clock input pin for setting for serial data timing. Inputs are latched on the rising edge and outputs occur on the falling edge. rite protect ( input ) rite Protect pin controls write-operation to the memory. hen P is high, all address in the memory will be protected. hen P is low, all address in the memory will be written. P pin is pulled down internally. Power supply pply the specified voltage to V. onnect V to ground. 2/16

3 I2 BU he employs a bi-directional two-wire I2 BU interface, works as a slave device. n example of I2 interface system with L Pull-up resistor L I2 BU master L (slave) 2 1 L (slave) I2 BU OMUNIION I2 BU data communication starts by start condition input, and ends by stop condition input. ata is always 8bit long, acknowledge is always required after each byte. I2 BU carries out data transmission with plural devices connected by 2 communication lines of serial data ( ) and serial clock ( L ). L condition E / OP condition ONIION Before executing each command, start condition ( start bit ) where goes from HIGH down to LO when L is HIGH is necessary. always detects whether and L are in start condition ( start bit ) or not, therefore, unless this condition is satisfied, any command is executed. OP ONIION Each command can be ended by rising from LO to HIGH when stop condition ( stop bit ), namely,l is HIGH. 3/16

4 NOLEGE ( ) IGNL his acknowledge ( ) signal is a software rule to show whether data transfer has been made normally or not. In master and slave, the device (μ-om at slave address input of write command, read command, and this I at data output of read command) at the transmitter (sending) side releases the bus after output of 8bit data. he device (this I at slave address input of write command, read command, and μ-om at data output of read command) at the receiver (receiving) side sets LO during 9 clock cycles, and outputs acknowledge signal ( signal) showing that it has received the 8bit data. his I, after recognizing start condition and slave address (8bit), outputs acknowledge signal ( signal) LO. Each write action outputs acknowledge signal ( signal ) LO, at receiving 8bit data ( word address and write data ). Each read action outputs 8bit data ( read data ), and detects acknowledge signal ( signal ) LO. hen acknowledge signal ( signal ) is detect, and stop condition is not sent from the master (μ-om) side, this I continues data output. hen acknowledge signal ( signal ) is not detected, this I stops data transfer, and recognizes stop condition ( stop bit ), and ends read action. nd this I gets in status. LVE E Output slave address after start condition from master. he significant 4 bits of slave address are used for recognizing a device type. he device code of this I is fixed to 11. Next slave addresses (2 1 device address) are for selecting devices, and plural ones can be used on a same bus according to the number of device addresses. he most insignificant bit (/ E/IE) of slave address is used for designating write or read action, and is as shown below. etting / to write (setting to word address setting of random read) etting / to 1 read L / condition IE POE hen P terminal is set Vcc(H level), data rewrite of all addresses is prohibited. hen it is set Vss(L level), data rewrite of all address is enabled. Be sure to connect this terminal to Vcc or Vss, or control it to H level or L level. t extremely low voltage at power ON / OFF, by setting the P terminal H, mistake write can be prevented. 4/16

5 OMMN BYE IE YLE rbitrary data is written to FeM. hen to write only 1 byte, byte write is normally used. start condition slave address with LB is (write) 1 st and 2 nd word address byte of write data. stop condition lave address PGE IE YLE I E 1 st O address 2 nd O address 12 8 hen to write continuous data of 2 bytes or more, simultaneous write is possible by page write cycle. By page write cycle, up to 8,192 bytes data can be written. hen data of the maximum bytes or higher is sent, data from the first byte is overwritten. rite data O P lave address I E 1 st O address 2 nd O address 12 8 rite data rite data O P UEN E E YLE urrent read cycle is a command to read data of internal address register without designating address, and is used when to verify just after write cycle. lave address E ead data O P N 5/16

6 NOM E YLE andom read cycle is a command to read data by designating address. start condition slave address with LB is (write) 1 st and 2 nd word address start condition slave address with LB is 1 (read) read out byte of data. to H stop condition EQUENIL E YLE hen signal L after is detected, and stop condition is not sent from master side, the next address data can be read in succession. lave address lave address I E 1 st O address 2 nd O address I E 1 st O address 2 nd O address UEN E E YLE ( H-MOE ) 8 8 he support a 3.4MHz high speed mode. hen H-mode operation is needed, the H-mode command is required before any command. fter the H-mode command is issued, will be the H-mode, until stop condition is issued. lave address lave address E E ead data N O P ead data N O P H-mode command lave address E ead data O P 1 X X X N N BYE IE YLE ( H-MOE ) I H-mode command lave address E 1 st O address 2 nd O address 1 X X X N rite data O P 6/16

7 ELEIL HEII BOLUE MXIMUM ING he application of stress (voltage, current, or temperature) that exceeds the absolute maximum rating may damage the device. herefore, do not allow actual characteristics to exceed any one parameter ratings PIN VOLGE Parameter ymbol Min. ating Max. Pin Voltage (Input ignal) V IN.5 V +.5 V Pin Voltage (Input/Output Voltage) V INQ, V OUQ.5 V +.5 V Power upply Voltage V.5 4. V Unit Note EMPEUE NGE Parameter ymbol Min. ating Max. Unit Note torage emperature (Extended emperature Version) Operating emperature (Extended emperature Version) stg opr 4 85 OHE Parameter ymbol ating Note =25 Power issipation P 1,m llowable Input urrent I IN +/- 2m a=25 llowable Output urrent I OU +/- 2m a=25 /16

8 EOMMENE OPEING ONIION POE UPPLY VOLGE Parameter ymbol Min. yp. Max. Unit Note Power upply Voltage V V Ground Voltage V V INPU VOLGE Parameter ymbol Min. Max. Unit Note Input High Voltage V IH V x. V +.3 V Input Low Voltage V IL.3 V x.3 V 8/16

9 HEII INPU/OUPU HEII Parameter ymbol ondition Min. Max. Unit Note Output Low Voltage V OL I OL =2m.4 V Input Leakage urrent I LI 1 1 µ Output Leakage urrent I LO 1 1 µ POE UPPLY UEN V =Max.to Min, a=opr Parameter ymbol ondition Max. Unit Note Power upply urrent (tandby) I L,= V, 2,1,= V or V 4 µ Power upply urrent (Operating) I V IN =.3V or V -.3V, fl=3.4mhz fl=4hz 1 6 m u 9/16

10 HEII V =Max. to Min., a=opr. Parameter ymbol F/-mode H-mode Min. Max. Min. Max. Unit Note lock frequency f L Hz lock Low time tlo ns lock High time thigh 6 6 ns Output ata delay time t 9 13 ns BU release time before transfer start tbuf 13 3 ns tart condition hold time th: 6 16 ns tart condition setup time tu: 6 16 ns Input data hold time th: ns Input data setup time tu: 1 1 ns, L rise time t 3 8 ns 1, L fall time tf 3 8 ns 1 top condition setup time tu:o 6 16 ns Output data hold time th ns Noise removal time (, L) Note: 1. Not 1% tested tp 5 5 ns Equivalent Load ircuit 3.3V 1kΩ Output 1pF 1/16

11 IMING 1/fL L t tf thigh tp tp (input) (output) t tf tu: tlo tbuf t th th: L (input) tu: th: tu:o BI OP BI 11/16

12 POE-ON N POE-OFF HEII (Under recommended operating conditions) Parameter ymbol Min. Max. Unit Note Power-On L, High Hold ime t VHEL 5 s 1, 2 Power-Off L, High Hold ime t EHVL 1 ns 1 Power-On Interval ime t VLVH 1 s 2 Notes: 1. o prevent an erroneous operation, be sure to maintain L=="H", and set the FeM in an inactive state (standby mode) before and after power-on and power-off. 2. Powering on at the intermediate voltage level will cause an erroneous operation; thus, be sure to power up from V. 3. Enter all signals at the same time as power-on or enter all signals after power-on. Power-On and Power-Off equences t EHVL t VHEL V V Min. V IH Min. V V Min. V IH Min. t VLVH V IL Max. L, V V IL Max. L, V 12/16

13 E/IE YLE N EENION (Under recommended operating conditions) Parameter Min. Max. Unit Note ead/rite ycle 1 12 ycle ata etention 1 Year PINE ignal ymbol Min. Max. Unit Note Input apacitance IN 1 pf 1 Input/Output apacitance OU 1 pf 1 Note1: ampling value. Measurement conditions are V IN = V OU = GN, f = 1MHz, and a = 25 13/16

14 PGE IMENION (Unit: mm) Notes for Mounting the urface Mount ype Package he surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. herefore, before you perform reflow mounting, contact OHM s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 14/16

15 EVIION HIOY ocument No. ate Previous Edition Page urrent Edition escription ep. 22, 213 Final edition 1 15/16

16 NOE No copying or reproduction of this document, in part or in whole, is permitted without the consent of LPI emiconductor o., Ltd. he content specified herein is subject to change for improvement without notice. he content specified herein is for the purpose of introducing LPI emiconductor's products (hereinafter "Products"). If you wish to use any such Product, please be sure to refer to the specifications, which can be obtained from LPI emiconductor upon request. Examples of application circuits, circuit constants and any other information contained herein illustrate the standard usage and operations of the Products. he peripheral conditions must be taken into account when designing circuits for mass production. Great care was taken in ensuring the accuracy of the information specified in this document. However, should you incur any damage arising from any inaccuracy or misprint of such information, LPI emiconductor shall bear no responsibility for such damage. he technical information specified herein is intended only to show the typical functions of and examples of application circuits for the Products. LPI emiconductor does not grant you, explicitly or implicitly, any license to use or exercise intellectual property or other rights held by LPI emiconductor and other parties. LPI emiconductor shall bear no responsibility whatsoever for any dispute arising from the use of such technical information. he Products specified in this document are intended to be used with general-use electronic equipment or devices (such as audio visual equipment, office-automation equipment, communication devices, electronic appliances and amusement devices). he Products specified in this document are not designed to be radiation tolerant. hile LPI emiconductor always makes efforts to enhance the quality and reliability of its Products, a Product may fail or malfunction for a variety of reasons. Please be sure to implement in your equipment using the Products safety measures to guard against the possibility of physical injury, fire or any other damage caused in the event of the failure of any Product, such as derating, redundancy, fire control and fail-safe designs. LPI emiconductor shall bear no responsibility whatsoever for your use of any Product outside of the prescribed scope or not in accordance with the instruction manual. he Products are not designed or manufactured to be used with any equipment, device or system which requires an extremely high level of reliability the failure or malfunction of which may result in a direct threat to human life or create a risk of human injury (such as a medical instrument, transportation equipment, aerospace machinery, nuclear-reactor controller, fuel-controller or other safety device). LPI emiconductor shall bear no responsibility in any way for use of any of the Products for the above special purposes. If a Product is intended to be used for any such special purpose, please contact a OHM sales representative before purchasing. If you intend to export or ship overseas any Product or technology specified herein that may be controlled under the Foreign Exchange and the Foreign rade Law, you will be required to obtain a license or permit under the Law. opyright LPI emiconductor o., Ltd. 16/16

MR44V064B GENERAL DESCRIPTION FEATURES 1/16. FEDR44V064B-01 Issue Date: Jan. 08, 2016

MR44V064B GENERAL DESCRIPTION FEATURES 1/16. FEDR44V064B-01 Issue Date: Jan. 08, 2016 M44V64B 64k(8,192-ord 8-Bit) FeM (Ferroelectric andom ccess Memory) I2 FE44V64B-1 Issue ate: Jan. 8, 216 GENEL EIPION he M44V64B is a nonvolatile 8,192-word x 8-bit ferroelectric random access memory (FeM)