Please Turn Your Mobile Phone Silent. August 29, 2017 CSc 242 1

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1 Please Turn Your Mobile Phone Silent August 29, 2017 CSc 242 1

2 CSc 242 Computer-Aided Systems Design and Verification Dr. Behnam Arad 5044 Riverside Hall (916) August 29, 2017 CSc 242 2

3 Online Access Instructor s Web Site: Course web site: August 29, 2017 CSc 242 3

4 Instructor: Dr. Behnam S. Arad Professor of Computer Science & Computer Engineering Phone: (916) Office: RVR Address: Office Hours: Updates August 29, 2017 CSc 242 4

5 Catalog description Design and verification methodology using hardware description and verification languages (HDVLs); Topics include: advances in IC chip design; introduction to HDVLs such as SystemVerilog; HDVL language basics including data types, arrays, structures, unions, procedural blocks, tasks, functions, and interface concept; design hierarchy; verification planning and productivity; verification infrastructure; guidelines for efficient verification of large designs; assertion-based verification; comprehensive computer-related design projects. Prerequisite: CSc 205; 3 units August 29, 2017 CSc 242 5

6 Textbooks SystemVerilog for Verification by Chris Spear & G. Tumbush, 3rd Edition, Springer 2013 SystemVerilog for Design by Stuart Sutherland, Simon Davidmann, and Peter Flake, 2 nd edition Springer 2006 August 29, 2017 CSc 242 6

7 Academic Honesty, Policy and Procedures htm minimum sanction no credit will be issued to all students involved Review information provided by the Office of Student Conduct August 29, 2017 CSc 242 7

8 Mailing List A mailing list has been set up for the course called csc242. The lists will be exclusively used by the instructor to send assignments and other important information to the students. Subscription to this list is required. Follow the instructions at the following link to subscribe to the mailing list: August 29, 2017 CSc 242 8

9 Grading Policy Term Project and Graded Assignments 20% Midterm Exam 40% Final Exam 40% August 29, 2017 CSc 242 9

10 Prerequisite CSc 205 CSc/EEE 273 August 29, 2017 CSc

11 Policies and Procedures Class attendance is required. Any adjustment to this syllabus or assignments will be announced in class. In addition, you must check your messages regularly for any important announcement distributed regarding this course. Exams will be closed book/closed notes. Prior to each exam, review guidelines will be provided. No make-up exam will be arranged unless there is a serious and compelling reason. The instructor must be notified prior to the exam, otherwise no make up will be given August 29, 2017 CSc

12 Use of laptop & other electronic devices You can use a laptop during the lecture only if it is used to take notes to view lecture slides for this course. Your laptop usage should not disturb other students. All cell phones, pagers, and similar devices should be on a silent during the lectures. No texting allowed during the lecture August 29, 2017 CSc

13 Projects & Assignments Graded assignments should be submitted as one PDF file through SacCT. You can learn about SacCT submission by visiting Each assignment should be typed and have a cover including the following information: Course number, Section, instructor, assignment number, due date, date submitted, and your name. Unless otherwise noted, late assignments submitted within one week of the due date will receive a %5 deduction. Late assignments will not be accepted once the solution has been provided. For certain assignments, a subset of problems may be graded at random. August 29, 2017 CSc

14 Riverside Key Access (FOB) You must obtain a Riverside Hall Key Access (FOB) to be able to access the labs. Contact your Department Office for an application form. You must deliver the approved forms to the Customer Service Center in the Facilities Services Office to pick up the key. August 29, 2017 CSc

15 Hardware Description and Verification Languages (HDVL s) Deal with complexity of large designs in terms maintaining code size and in keeping parity among specification (English) design (HDL) verification model (HDVL) August 29, 2017 CSc

16 System Verilog IEEE 1800 is a newly unified language intended for both hardware description and verification. An extension of Verilog HDL (IEEE 1364). Can be easily interfaced with C, C++ Supports object-oriented programming methodology for verification Supports assertion-based verification methodology. August 29, 2017 CSc

17 Tentative Topics to be Covered Overview of IC chip design process (2 hour) Review of design using hardware description languages (3 hour) Introduction to hardware description and verification languages (HDVLs) (1 hour) HDVL basics including data types, structures, unions, and arrays (5 hour) Procedural blocks (2 hours) Design Hierarchy (3 hours) Interface concept and its application (6 hour) Verification planning and productivity (1 hour) Verification Infrastructure (5 hour) Object oriented approach in verification (6 hour) Inter-process communication in SystemVerilog (2 hour) Verification methodology using HDVLs (5 hours) Case studies involving computer design (3 hours) August 29, 2017 CSc

18 Major Topics hour(s) References Introduction 1 Course Outline Overview of IC chip design process 1 lecture notes Review of design using hardware description languages 3 lecture notes Introduction to System Verilog 1 Sutherland Chapter 1 Spear Chapter 1 SystemVerilog Package 2 Sutherland Chapter 2 System Verilog basics including data types, structures, unions, and arrays 7 Sutherland Chapter 3 5 Spear Chapter 2 Procedural blocks & Statements 2 Sutherland Chapter 6-7 Spear Chapter 3 Interface concept and its application 6 Sutherland Chapter 10 Verification methodology using SystemVerilog 8 Spear Chapters 4 Object oriented approach in verification 5 Spear Chapter 5 Randomization 2 Spear Chapter 6 Functional Coverage 2 Spear Chapter 9 Case studies involving computer design 3 Exams and Review 2 August 29, 2017 CSc

19 Questions? August 29, 2017 CSc