ECEN/CSCI 4593 Computer Organization and Design Exam-2

Transcription

1 ECE/CSCI 4593 Computer Organization and Design Exam-2 ame: Write your initials at the top of each page. You are allowed one 8.5X11 page of notes. o interaction is allowed between students. Do not open this booklet until you are told to do so. Show all of your work for possible partial credit. Problem 1 Problem 2 Problem 3 Problem 4 Problem 5 Problem 6 Problem 7 30 pts 20 pts 30 pts 20 pts 15 pts 15 pts 30 pts Page 1 of??

2 Question 1. (30 points) Give a concise answer to each of the following questions. Limit your answers to 20 words. (a) What is the functionality of a BB? (b) If a compiler could fill all the delay slots of a machine, would there be any need for branch prediction? (c) What are the main functionalities of a page table? (d) Why does a two-level address translation algorithm require a smaller amount of main memory than a one-level algorithm? (e) What is set associativity? (f) What is the purpose of dirty (modified) bit in a cache tag store entry? Page 2 of??

3 (g) Describe the page faults that can potentially occur during a two-level address translation. (h) Which cache model has the fastest HI LAECY (fully-associative, set-associative, directmapped)? (i) Which cache design (write-back or write-through) uses a dirty bit? (j) When a item of data is written repeatedly, which has better memory system utilization, writeback or write-through cache? (k) What are the two localities (characteristics) that caches exploit? (l) What are the three types of cache misses? (m) rue/false - Capacity misses are generally eliminated by increasing the cache associativity? (n) rue/false - A 4-stage pipeline that uses a combined EXECUE and MEMORY stage will not have a LOAD-stall. Page 3 of??

4 Question 2. (20 points) his question covers cache and pipeline performance analysis. (Part A) Write the formula for the ideal number of cycles in a pipelined execution (use for instructions and P for pipestages within one instruction): (Part B) Write the formula for the average memory access time assuming one level of cache memory: (Part C) For a data cache with a 80% hit rate and a 1-cycle hit latency, calculate the average memory access latency. Assume that latency to memory and the cache miss penalty together is 100 cycles. ote: he cache must be accessed after memory returns the data. (Part D) Calculate the performance of a standard 5-stage pipeline with full register bypassing. he data cache (for loads and stores) is the same as described in Part C and 30% of instructions are loads and stores. he instruction cache has a hit rate of 90% with a miss penalty of 50 cycles. Calculate the CPI of the pipeline, assuming everything else is working perfectly. Assume the load never stalls a dependent instruction and assume the processor must wait for stores to finish when they miss the cache. Finally, assume that instruction cache misses and data cache misses never occur at the same time. Page 4 of??

5 Question 3. (30 points) (Part A) Dependence detection his question covers your understanding of dependences between instructions. Using the code below, list all of the dependence types (FLOW, AI, OUPU). You should list them in the table (example IS-X to IS-Y FLOW) instead of drawing a graph. I0: ADD R3 = R1 + R0; I1: SUB R0 = R3 - R4; I2: ADD R4 = R5 + R6; I3: MUL R4 = R3 + R1; I4: LDW R2 = MEM[R2 + 0]; I5: AD R2 = R2 & R1; From Instruction o Instruction ype of Dependence Page 5 of??

6 (Part B) Forwarding logic design For this problem you are to design a forwarding unit for a 5-stage pipeline processor. he forwarding unit returns the value to be forwarding to the current instruction. here are three places that the values for register RS and register R can come from: decode stage (register file), memory stage, and write-back stage. DECODE SAGE IFORMAIO RS IDEX(5 bits) RS REG VALUE (32bits) R IDEX(5 bits) R REG VALUE (32bits) MEMORY SAGE IFORMAIO REGISER IDEX (5 bits) VALUE (32 bits) WRIE_EABLE (1 bit) REGISER IDEX (5 bits) VALUE (32 bits) WRIE_EABLE (1 bit) WRIE BACK SAGE IFORMAIO FORWARDIG UI VALUE FOR RS VALUE FOR R he write-back and memory stage information consists of: IDEX- explaining which inflight register index is to be written VALUE- the value that is to be written EABLE- whether or not the instruction in the stage is writing. he decode stage simply states the register index (for RS and R) and the corresponding register value from the register file. Page 6 of??

7 Generally three values could exist, one of which the forwarding unit should choose for each of the RS and R register value requests. he memory stage has value MEM, the write-back stage has value WB, and the register file has value RS-REG or R-REG. Using the table below which contains information about all of the instruction stages, indicate which value should be forward to the current instruction: MEM, WB, RS-REG, or R-REG. Each line represents a Forwarding unit evaluation, there is no connection between evaluation lines in the table. You do not need to worry about hazard detection, only value bypassing. Mem Stage Write-Back Stage Register Stage RS Value R Value Evaluation Index Write Index Write RS-Index R-Index Page 7 of??

8 Question 4. (20 points) Question 4. (20 points) his problem covers your knowledge of branch prediction. he following figure illustrates three possible state machines LAS-AKE UP-DOW AUOMAO-A3 OES: Last taken predicts taken on 1 Up-Down predicts taken on 11 and 10 Automata A3 predicts taken on 11 and 10 Fill out the tables below for each branch predictor. he execution pattern for the branch is. Page 8 of??

9 Execution Branch State State Correct or ime Outcome Before After Incorrect able 1: able for last-taken branch predictor. Execution Branch State State Correct or ime Outcome Before After Incorrect able 2: able for up-down branch predictor. Execution Branch State State Correct or ime Outcome Before After Incorrect able 3: able for Automata-A3 branch predictor. Calculate the prediction rates of the three branch predictors: Page 9 of??

10 Predictor Last-taken Up-Down Automata-A3 Prediction accuracy Question 5. (15 points) his problem cover physical cache design and cache access. (Part A) Design a 32KB direct-mapped data cache that uses a 16-bit address and 4 bytes per block. Calculate the following: (a) How many bits are used for the byte offset? (b) How many bits are used for the set (index) field? (c) How many bits are used for the tag? (Part B) Cache access: Assume the following 6-bit physical address sequence generated by the microprocessor: ime Access he cache uses 2 bytes per block. Assume a 2-way set assocative cache design that uses the LRU algorithm. Assume that the cache is initially empty. Hint, first determine the AG, SE, and IDEX field. SE 0 SE 1 BLOCK 0 BLOCK (Part C) Derive the hit ratio for the access sequence in Part B. Page 10 of??

11 Question 6. (30 points) he memory architecture of a machine X is summarized in the following table. Virtual space Page size PE size 8GB space 16K bytes 4 bytes (Part A) Assume that there are 10 bits reserved for the operating system functions (protection, replacement, valid, modified, and Hit/Miss- All overhead bits) other than required by the hardware translation algorithm. Derive the largest physical memory size (in bytes) allowed by this PE format. Make sure you consider all the fields required by the translation algorithm. (Part B) How large (in bytes) is the page table? Page 11 of??

12 (Part C) In the picture below (the algorithm for a 1-level translation scheme), place the values for the known fields of the virtual memory and physical memory in the diagram. If the value to be used in a box is known, fill in the value. Otherwise, indicate the number of bits associated with each rectangular box. Assume that you answer from Part A defines the actual physical memory for the processor. (Hint: Determine how many page frames in your memory and how to index those page frames). VAD x + PBR PAPE access physical memory PE PAD access physical memory page fault OS brings data page no Data in PM D MBR Page 12 of??

13 Question 7. (20 points) his question covers virtual memory access. Assume a 5-bit virtual address and a memory system that uses 4 bytes per page. he physical memory has 16 bytes (four page frames). he page table used is a one-level scheme that can be found in memory at the PBR location. Initially the table indicates that no virtual pages have been mapped. Implementing a LRU page replacement algorithm, show the contents of physical memory after the following four virtual access: 11100, 01000, 00000, Show the contens of memory and the page table information after each access sucessfully completes in Figure A, B, C, and D. Each page table entry (PE) is 1 byte. virtual space page 000 page 001 page 010 page 011 page 100 page PBR physical (main) memory M M M M M M M M page frame 00 page frame 01 page frame 10 page frame 11 page page Figure 1: he initial contents of memory. Page 13 of??

14 physical (main) memory page frame 00 page frame 01 page frame 10 page frame 11 Figure 2: Figure A (after access 11100). physical (main) memory page frame 00 page frame 01 page frame 10 page frame 11 Figure 3: Figure B (after access 01000). Page 14 of??

15 physical (main) memory page frame 00 page frame 01 page frame 10 page frame 11 Figure 4: Figure C (after access 00000). physical (main) memory page frame 00 page frame 01 page frame 10 page frame 11 Figure 5: Figure D (after access 01000). Page 15 of??