1. Truthiness /8. 2. Branch prediction /5. 3. Choices, choices /6. 5. Pipeline diagrams / Multi-cycle datapath performance /11

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1 The University of Michigan - Department of EECS EECS 370 Introduction to Computer Architecture Midterm Exam 2 ANSWER KEY November 23 rd, 2010 Name: University of Michigan uniqname: (NOT your student ID number!) Open book, open notes. No laptops, PDAs, cell phones, etc. (calculators are ok). Questions vary in difficulty; it is strongly recommended that you do not spend too much time on any one question. For questions where a box is provided, please put your final answer in the box. The rules of the Honor Code of the University of Michigan - College of Engineering apply for this exam. Honor code pledge: I have neither given nor received aid on this examination, nor have I concealed any violations of the Honor Code. Signature: (Exams without a signed pledge will not be graded) Question Score/Point Value 1. Truthiness /8 2. Branch prediction /5 3. Choices, choices /6 4. Hazards /12 5. Pipeline diagrams /12 6. Multi-cycle datapath performance /11 7. A pipeline with cache /11 8. A simple cache for LC2K /10 9. Pipeline design / Cache misses /18 TOTAL /110 Page 1 of 12

2 1. Truthiness [8 points] For each of the following statements, indicate whether it is True or False. Circle your choice. [1 pt per correct answer] On caches: a) Capacity misses may occur due to the size of a block in a cache TRUE / FALSE b) Compulsory misses cannot be reduced by increasing the size of the cache, while keeping the block size the same TRUE / FALSE c) Compulsory misses may be reduced with a larger block size TRUE / FALSE d) Conflict misses may or may not occur depending on the replacement policy in use On datapaths: e) Resolving branches earlier in a pipeline will result in a faster clock frequency than if resolved in later pipelined stages TRUE / FALSE TRUE / FALSE f) A multi-cycle datapath is the cheapest one to implement compared to single-cycle and pipelined ones, as it reuses datapath elements TRUE / FALSE g) Pipelined execution produces the highest throughput compared to single-cycle and multi-cycle execution h) A single-cycle datapath processor has faster clock frequency than one implemented with a multi-cycle datapath, if everything else is the same TRUE / FALSE TRUE / FALSE 2. Branch Prediction [5 points] Consider the 2 bit saturating predictor as discussed in lecture. The predictor is initialized to 2; it is incremented when a branch is taken (T) and decremented when a branch is not taken (N). Given the execution sequence below for a single branch, fill in the table with the counter values and predictions at each branch occurrence. [0.5 pt per correct column] Prediction before branch resolves Counter after branch resolves Init N N T T N T T T T T N N N T N T T What is the accuracy of this branch predictor (provide your answer as a percentage)? [1pt] 3/8 = = 37.5% Answer: 37.5 % Page 2 of 12

3 3. Choices, Choices [6 points] For the two questions below, select the option(s) that best matches: [1pt per correct answer] a) Associate the characteristics below with one option among A, B or C at the right: Highest frequency of access: B Makes use of both temporal and spatial locality: C Largest access latency: A Located physically closest to the ALU: B A. Optical disk B. Register C. Cache b) Consider the following snippet of MIPS assembly: 1: lui $s1, 10 2*: add $zero, $s1, $s1 3: xor $s2, $s1, $s1 4: sw $s1, 0($sp) 5: lw $s3, 0($sp) 6: div $s3, $s2 * Remember that writing to register $zero is not an error and no exception will be triggered. The register write just fails silently. Which instruction (line number), if any, causes the processor to trigger an exception? [2pts] A. 3 B. 4 C. 5 D. 6 E. None Page 3 of 12

4 4. Hazards [12 points] Oh no! You are provided with a 5-stage LC2K pipeline which has neither hazard detection capabilities nor data forwarding paths. However, you are slightly relieved to learn that the register file does support internal forwarding, i.e., registers can be read and written in the same cycle (similar to what we have done in lecture). Given the LC2K code snippet showed on the right: LC2K code snippet: a) Draw arrows on the code snippet to indicate all the hazards present. For instance, if there were two hazards between registers C1 and A2 and between C1 and B2 for instructions 1 and 2 below, your answer should look like: 1: opcode1 A1 B1 C1 2: opcode2 A2 B2 C2 [3 pts] b) Use the boxed space below to show all dependencies among the instructions in the snippet. Whenever a particular instruction must complete before another instruction, use an arrow to indicate this constraint. As an example, a diagram like: indicates that instruction 3 must be executed after 2, instruction 4 must be executed after 3, and instruction 6 can only be performed after both 1 and 4 are completed. Instruction 5 is not shown anywhere in the example diagram, thus it can be executed at any time. [4 pts] Your diagram: 1:add :nand :lw 1 4 laba 4:sw 3 4 labb 5:nand :add c) Based on your answers in parts a) and b) above, reorder the snippet s instructions to achieve maximum performance, adding noops as necessary to ensure correctness. (Note: Your answer should not exceed 10 instructions) [5 pts] other 8-cycle solutions possible 1: add : lw 1 4 laba 3: noop 4: nand : add : noop 7: sw 3 4 labb 8: nand : 10: Page 4 of 12

5 5. Pipelined Diagrams [12 points] You are currently working on an 8-stage LC2K pipeline design, as follows: Fetch: Instructions are fetched ID1: Register values begin to be loaded ID2: Register values loading completes EX1: ALU operation begins for all instructions EX2: Branches are resolved EX3: ALU operation ends for all instructions MEM: Memory access WB: Write back Branches are predicted not taken and mispredicted branches are squashed. Note that they are resolved in EX2. In addition, the pipeline has full forwarding paths from EX3/MEM and MEM/WB back to EX1. If an instruction must be stalled, the stall should be at the latest possible pipeline stage. The design executes the following snippet of code: 0: lw 0 2 two 1: sw 0 3 six 2: add : beq : halt 5: six.fill 6 6: two.fill 2 Please complete the table below, indicating which instruction (use its opcode) is executing in which pipeline stage for the first 10 cycles of execution. Indicate stalls with a --. To get you started, we completed the first four cycles for you. [2 pts per correct cycle, total 12 pts] Cycle Fetch ID1 ID2 EX1 EX2 EX3 MEM WB 1 lw 2 sw lw 3 add sw lw 4 beq add sw lw 5 halt beq add sw lw 6 halt beq add - sw lw 7 halt beq add - - sw lw 8 halt beq add - - sw lw 9 halt beq - add - - sw 10 halt beq - - add - - Page 5 of 12

6 6. Multi-cycle Datapath Performance [11 points] The following code took 32.6 nanoseconds to execute: lw 0 1 init lw 0 2 one lw 0 4 end start beq 1 4 done add add beq 0 0 start done halt init.fill 0 one.fill 1 end.fill 10 a) How many times does this code go through the loop? [1pt] 10 times b) If this program was executed on the LC2K multicycle datapath discussed in class, how many cycles does it take to execute? To compute this number, fill in the table below with the number of times each type of instruction is executed and the total number of cycles it took to execute that instruction. Then provide your answer for the total number of cycles. Assume it takes 4 cycles for the halt instruction. As an example, in the code below the add instruction is executed twice. add [5pts, 1 for each correct row] add Instruction Number of times it is Total cycles for type executed instruction add lw 3 15 beq halt 1 4.fill 0 0 Total cycles executed for the entire program:[1 pt] 183 cycles c) What is the average CPI? [Show your calculation to receive credit for this part] [2 pts] 183/45 = CPI d) What is the frequency of this processor (in GHz)? [Show your calculation to receive credit for this part] [2 pts] 183/ (32.6 ns) 5.61 Ghz Page 6 of 12

7 7. A pipeline with cache [11 Points] Consider a 5-stage pipelined processor similar to the LC2K we have studied in class. All branches are predicted not taken and resolved in the memory stage. There are separate instruction and data caches. If there is a miss in any of the caches, the data will always be available in memory. The pipeline has the following instruction breakdown and statistics: 10% add 10% nand 25% lw 20% sw 30% beq 5% noop 15% of add and nand are followed by dependent instructions 25% of loads are followed by dependent instructions 5% of all stores are followed by a load instruction that loads from the same address as the preceding store 75% branches are taken 40% branches followed by another branch D-cache hits 95% of time, I-Cache hits 99.9% of time. Each memory access takes 150 cycles. Below is a list of possible factors that may impact the overall CPI of this pipelined datapath. Please calculate the amount of CPI increase (beyond the ideal CPI=1) due to each of these factors. If you believe that a factor does not impact this pipeline s CPI, simply indicate 0. [YOU **MUST SHOW YOUR WORK** TO RECEIVE ANY CREDIT FOR YOUR ANSWERS] a) Branch misprediction [2 pts] 0.3*0.75*3= CPI b) Adds and nands followed by dependent instructions [1 pt] 0 CPI c) Cache misses [2 pts, 1 per addendum] 1.00*0.001*150 + ( )*0.05*150= CPI d) Loads followed by dependent instructions [2 pts] 0.25*.25*1 = e) Stores to an address followed by loads to the same address [1 pt] CPI 0 CPI f) Branches followed by another branch [1 pt] 0 CPI TOTAL CPI for this datapath: [2 pts] Page 7 of 12

8 8. A simple cache for LC2K [10 points] We want to design a cache for our LC2k pipelined datapath. As you know, LC2k is wordaddressable with 16-bit addresses. Assume the memory has an average access time of 100ns. We would like to add a direct-mapped, 1KB cache with a block size of 4 words a) How many sets are in the cache? [2 pts] Answer: 64 b) What is the associativity of the cache? [2 pts] (direct-mapped also acceptable) Answer: 1-way c) Indicate below how many address bits must be reserved for tag, set index and block offset: Answer: [3 pts] tag set index block offset Now, we want to evaluate the performance improvement of the memory system of this LC2k design with our cache in place. Assume that the cache has an average access time of 4ns and a hit rate of 92% when running our greatest benchmark, the combination program from project 2. d) What is the average access time of the system with the cache in place? [2 pts] (show your work below to receive credit) 4ns * 100ns = 12ns (1 pt for 11.68ns, which assumes cache access overlaps memory access) Answer: 12 ns e) What is the performance improvement compared to the original system without the cache? (old access time / new access time) [1 pt] 100ns/12ns = 8.33 Answer: 8.33 times better Page 8 of 12

9 9. Pipeline Design [17 points] Your LC2K company sales are rapidly growing. Sales are doubling every year. The company programmer tells you that soon there will be a problem with the accounting software. Since the LC2K does not support floating point, all accounting is done in cents using signed two's complement integer arithmetic. With this data representation, the annual sales revenue for LC2K systems will no longer fit in a word three years from now. a) What is the current annual sales revenue for LC2K systems? (you can round the value to thousands of $). [2pts] will overflow when cents will not fit in a 32 bit signed integer, which happens at 2**31 cents. Sales double each year, and it will overflow in three years, so we are currently at 1/8 of this, 2**28 cents. $2,684 thousands Precise answer: current annual sales $2,684, Reasonable rounded answer: annual sales $2.7 million per year (also accept $3 million or $2.6 million or something more precise for full credit) You are feeling optimistic that long term sales of LC2K systems will continue to increase, so you decide that sales figures should be stored as single precision floating point numbers. To maintain acceptable performance of the accounting software, you create a floating point add instruction, "fadd" and you build a new pipelined machine that implements the traditional LC2K instruction set plus this instruction. However, you find that implementing "fadd" makes the ALU slower. As the ALU was already one part of the critical path that limited clock speed, you must slow the clock down as a result. The old ALU produced a result in 3 nanosec, while the new ALU produces a result in 4 nanosec, and the old machine had a maximum clock frequency of 250 MHz. b) What is the maximum clock frequency of the new machine? [2pts] Old clock was 250 MHz, so clock period was 4 nsec. ALU was said to be in the critical path, and it changed from 3 nsec to 4 nsec, which slows the critical path down by 1 nsec, so it must change from 4 nsec to 5 nsec. 5 nsec clock period implies clock frequency of 200 MHz 200 Mhz To avoid slowing the clock down, you decide to build a separate pipelined ALU just to handle "fadd". This ALU takes input from ID/EX and after two cycles it places a result into a new pipeline register in MEM/WB called "faluresult". This new ALU has an internal pipeline register so it can accept new input data on every cycle and it can also produce new output data on every cycle. Data hazards are resolved with "detect and forward". Assume that the pipeline behaves like the version in the lectures (register file has internal forwarding so new register values are read correctly on the same cycle that they are written). Page 9 of 12

10 Above we provide a figure showing the pipelined LC2K with the new floating point ALU (marked "falu"). However, we did not get a chance to complete all of the connections. Your job is to answer the question below. Questions c) and d) refer to the lettered locations, A through F, near the center of the figure. You should circle exactly one choice for each question. c) Where should the upper input of the new floating point ALU be connected? [1pt] A B C D E F F also works if they selected E for d) d) Where should the lower input of the new floating point ALU be connected? [1pt] A B C D E F E also works if they selected F for c) e) The five MUXes in the figure have been labeled M1 through M5. Circle below all of the MUXes that will need one or more additional input to support the new falu: [1pt] M1 M2 M3 M4 M5 Page 10 of 12

11 For the remaining parts of this question, consider each of the following instruction sequences. Assume there are no dependent instructions preceding or following these sequences. Sequence V Sequence W Sequence X Sequence Y Sequence Z fadd add fadd fadd lw fadd fadd add lw fadd For each statement below, list all sequences (out of V, W, X, Y, Z) for which the statement is true. The first one is completed for you as an example: [10pts, 2 for each sequence placed in all its correct slots] [EXAMPLE] This sequence modifies register 3: [ANSWER]: V W X f) No stall is needed: Answer: W g) A stall of exactly one cycle is needed: Answer: V, X, Y, Z h) A stall of two or more cycles is needed: Answer: NONE i) No forwarding is needed: Answer: NONE j) Forwarding from EX/MEM is needed: Answer: W k) Forwarding from MEM/WB is needed: Answer: V, X, Y, Z Sequences behave as follows: V: one cycle stall then register 3 forwards from MEM/WB W: no stall; register 3 forwards from EX/MEM X: onc cycle stall then register 3 forwards from MEM/WB Y: one cycle stall then register 5 forwards from MEM/WB Z: one cycle stall then register 5 forwards from MEM/WB Page 11 of 12

12 10. Cache Misses [18 points] Cache-pro incorporated has developed a new cache data replacement algorithm called leastfrequently used (LFU). LFU tracks how often an address has been accessed once it was loaded in the cache. The addresses in the cache that are accessed the least are evicted first. If there are multiple items in a block, the sum of each item in the block is used. We have a 16-byte cache using LFU in a system that uses 32-bit addresses. The cache has the following properties: byte-addressable memory, 2 byte block size, write-back, 2-way set associative. a) Indicate below how many address bits must be reserved for tag, set index and block offset: Answer: [3pts] 29 tag set index block offset b) Now we perform a sequence of memory accesses to this cache at the addresses and in the order reported in the table below: 12, 15,... Your job is to fill out the table. Make sure to provide the set and block numbers as decimal values. The #LFU field tracks the current access, as well as previous ones, to a same block. In the last two fields, circle whether the access is a hit or a miss and what type of miss. On the right, we drew a 16 bytes cache that you must partition in blocks and sets and use to indicate the values that you write or overwrite for each access in order. We started to fill the table for you. Make sure you report the first four addresses in the cache schematic on the right as well. [14pts,.5 for each Set/Block, LFU, Hit/Miss, type of miss] Cache schematic Dec Hex Set # Block # # LFU Hit/Miss Type of miss 12 0xC Miss Comp 15 0xF Miss Comp 33 0x Miss Comp 11 0xB Miss Comp 55 0x Hit / Miss Comp / Cap / Conf 14 0xE Hit / Miss Comp / Cap / Conf 87 0x Hit / Miss Comp / Cap / Conf 27 0x1B Hit / Miss Comp / Cap / Conf 13 0xD Hit / Miss Comp / Cap / Conf 63 0x3F Hit / Miss Comp / Cap / Conf 86 0x Hit / Miss Comp / Cap / Conf c) How many cache hits and cache misses occurred while accessing the memory addresses of part b)? [1pt] Hits: 2 Misses: Page 12 of 12