The University of Michigan - Department of EECS EECS 370 Introduction to Computer Architecture Midterm Exam 2 solutions April 5, 2011

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1 1. Performance Principles [5 pts] The University of Michigan - Department of EECS EECS 370 Introduction to Computer Architecture Midterm Exam 2 solutions April 5, 2011 For each of the following comparisons, indicate how the metric of interest differs between the two design approaches being considered using one of the following:, =, or. The first question is already answered in order to provide you with an example. These questions assume the common behavior and that only factors relevant to the design change being considered vary. (EXAMPLE) The CPI for a single-cycle processor is generally than that of a multi-cycle processor. a) [0.5 pts] The CPI for a single-cycle processor is generally than that of a pipelined processor. b) [0.5 pts] The CPI of a multi-cycle processor is generally than that of a pipelined processor. c) [0.5 pts] The cycle time for a single-cycle processor is generally than that of a multicycle processor. d) [0.5 pts] The cycle time for a single-cycle processor is generally than that of a pipelined processor. e) [0.5 pts] The cycle time for a multi-cycle processor is generally than that of a pipelined processor. f) [0.5 pts] The average number of stalls due to data hazards for a multi-cycle processor is generally than that for a pipelined processor. g) [0.5 pts] The memory access latency, in nanoseconds, for a multi-cycle processor is generally = than that for a pipelined processor. h) [0.5 pts] The number of misses incurred by a direct mapped cache is generally than that for a fully associative cache that is the same total size. i) [0.5 pts] The access time, in nanoseconds, of a direct mapped cache is generally than that for a fully associative cache that is the same total size. j) [0.5 pts] For programs with high spatial locality, the number of misses in a cache with a small block size is generally than that for the same-sized cache with a larger block size. Page 1 of 11

2 2. Branch Prediction [5 pts] Assume we are using a 2-bit saturated counter for a branch predictor, similar to the one that was discussed in lecture. The counter starts at a value of 1 (binary: 01). Please fill out for each column if the branch is predicted as taken or not taken. The actual taken/not taken for the branch is then given to you. Please also fill out the value of the counter after the branch is executed. Cycle Predicted As: N T T T T Actual Execution: T T T N N Counter: What is the branch predictor s hit rate: 40 % Page 2 of 11

3 3. A Buggy Multicycle Datapath [15 pts] You are working for Datapaths, Inc. and you are given a LC-2K multicycle datapath to test (luckily, it s the exact same datapath you studied in EECS 370). After much testing, you realize that there is a select line stuck-at fault in one of the MUXes, which means that the select line of a MUX is permanently stuck at either 0 or 1. To figure out which MUX is affected by the stuck-at fault, you run a short program and examine the initial and final register contents, which are shown below. Assume that all registers not listed in the table have initial and final values of 0. add lw nand noop noop noop halt.fill 0.fill 1337.fill 0.fill 5.fill 0.fill 0 Register Initial Value Final Value a.) [5 pts] If this program were run on a non-buggy datapath, what would the actual contents of the registers be? Fill in the table below. Register Correct value Page 3 of 11

4 b.) [7 pts] Which MUX is affected by the stuck-at fault? What values are the select line/lines stuck at? In the diagram, a working MUX s top input is associated with a select value of 0. Circle your answers. (A multicycle datapath is provided for reference.) Broken MUX: MUX addr MUX dest MUX rdata MUX alu1 MUX alu2 Stuck at: c.) [3 pts] Which instructions are affected by this bug? Circle all that apply. ADD NAND LW SW BEQ Page 4 of 11

5 4. Pipeline Performance [12 pts] You are given the following instruction breakdown: % Instructions Extra Information 10% add I-cache hit 90% 20% nand D-cache hit 98% 25% beq Branches not taken 45% 15% sw lw followed by dependent instruction 25% 30% lw Memory access time 75ns a) [6 pts] Assuming the above code is run on a standard 5 stage pipeline with branches predicted not taken and clocked at 200MHz, what is the CPI? Show your work. How many cycles for memory stall? 200 MHz = 5ns à 75ns / 5 ns = 15 cycle stall CPI = 1+(1.00)(0.10)(15)+( )(0.02)(15)+(.30)(0.25)(1)+(0.25)(0.55)(3) = b) [6 pts] This five stage pipeline is extended to a similar 15 stage pipeline with no additional hazards being introduced. The amount of noop s inserted after a lw followed by a dependent instruction does not change. The new frequency is 400MHz. Now the same code is run on the 15 stage pipeline where branches are resolved in the 11 th stage. What is the new CPI? Show your work. New branch stall à 11 1 = 10 noop inserted How many cycles for memory stall? 400 MHz = 2.5ns à 75ns / 2.5 ns = 30 cycle stall CPI = 1+(1.00)(0.10)(30)+( )(0.02)(30)+(.30)(0.25)(1)+(0.25)(0.55)(10) = 5.72 Page 5 of 11

6 5. Pipeline Design [18 pts] You work for XtremelyFast Computers, LLC, and have been tasked with building SuperSecure Processor, a processor based on the design of the pipelined LC-2K. Below is an unmodified LC-2K pipelined processor. Forwarding paths exist but are omitted from the diagram. The following table gives the latencies for various operations: Memory Accesses: Register File Accesses: ALU Operations: Encryption: Decryption: Other Operations (e.g., muxes, pipeline registers): 0.95 ns 0.20 ns 0.75 ns 1.75 ns 0.80 ns 0 ns The SuperSecure allows a programmer to encrypt ( Enc ) data before sending it to memory, and decrypt ( Dec ) data loaded from memory. Encryption and Decryption operations are done in hardware added to the datapath. To enable their functionality, two new instructions are added to the LC-2K ISA, as described below: sec-sw rega regb offset Effect: MEM[regA + offset] = Enc(regB) sec-lw rega regb offset Effect: regb = Dec(MEM[regA + offset]) a) [3 pts] What is the maximum clock frequency for which the datapath below will always produce correct results? Circle the stage that limits the clock frequency. You may assume forwarding paths exist which do not increase the cycle time. Fetch and Decode stages are unchanged, and have been omitted from the diagrams. Show all work. Critical path in EX = 1.75 ns for Encryption Max Clock = 1/ 1.75 ns 571 MHz Page 6 of 11

7 Problem 5 continued b) The following datapath modification allows a higher operating frequency. Note that we have pipelined the encryption unit, where each stage takes half the time as the original. Once again, fetch and decode are unmodified and omitted from this diagram. All necessary forwarding paths exist, but are omitted from this drawing. (i) [3 pts] Which stage(s) should we forward the result of a sec-lw to? Where do these forwarding path originate from? Forward from WB stage, to the EX stage (ii) [3 pts] How many cycles will this design stall if there is a sec-lw immediately followed by a use? 3 cycles (iii) [2 pts] How many cycles will this design stall if there is a lw immediately followed by a use? 2 cycles (iv) [7 pts] How would you redesign the pipeline so that a lw followed by a dependent instruction requires fewer noops? You may not add new stages, and clock cycle time cannot change. Please restrict your answer to no more than three sentences. One solution: move ALU to the Enc stage. This will reduce the # of noops required for lws followed by a dependent instruction to one. Page 7 of 11

8 6. Cache Policies [13 pts] Assume we have a cache described as follows: 8 byte total cache size 2 byte block size 2-way set associative cache 16-bit addresses a) [3 pts] Divide an address into its corresponding tag, set index, and block. How many bits are used for each section? Show all work. Tag Set Index Block 14 bits 1 bits 1 bits b) [10 pts] Compare the following address accesses for the given cache using the LRU replacement policy versus the MRU (Most Recently Used) replacement policy. The MRU replacement policy will fill up the set first if there are still empty blocks. Once the set is full, any replacements are done by evicting the Most Recently Used block in that set. For each address, determine whether the LRU and MRU replacement policy on the given cache produce a hit or a miss? The first row has been filled out for you. Show all work. Address LRU MRU Hit/Miss? 4 Miss miss 7 Miss Miss 8 Miss Miss 5 Hit Hit 1 Miss Miss 9 Miss Hit 4 Miss Miss 0 Miss Hit Page 8 of 11

9 7. Cache Performance [12 pts] Assume we have a cache described as follows: 50 bytes total cache size 10 byte block size Fully associative cache with a LRU replacement policy Write-back cache We would like to compare the following two code segments, in regards to their cache performance (assume the array x is initially filled with 0s in memory): Code Segment A for (int i=0; i<10; i++) { for (int j=0; j<100; j++) { x[j] = (i*j) + x[j]; } } Code Segment B for (int j=0; j<100; j++) { for (int i=0; i<10; i++) { x[j] = (i*j) + x[j]; } } a) [3 pts] How many reads from main memory to the cache will code segment A perform? 100 b) [3 pts] How many reads from main memory to the cache will code segment B perform? 10 c) [6 pts] Which code segment (A or B) performs better on this cache? Explain why in three or fewer sentences. B, less time spent going to main mem, more cache hits, etc Page 9 of 11

10 8. Cache Configuration [20 pts] You are given a 16 byte cache that is byte addressable with 8 bit memory addresses. The following addresses are referenced in the order below. Your goal is to configure the cache by specifying the block size (in bytes) and associativity. 0xBC 0x23 0xEA 0x4A 0x21 0x57 0xFF 0xBE a) [6 pts] How can you configure the cache so that there are no compulsory misses? If not possible, check not possible instead of filling in block size and associativity. Show your work. Block size: bytes Associativity: Not possible? _X_ b) [7 pts] How can you configure the cache so that there are 6 compulsory misses, 1 hit which occurs at reference 0x21, and 1 capacity miss? If not possible, check not possible instead of filling in block size and associativity. Show your work. Block size: 4 bytes Associativity:direct mapped or fully associative Not possible? Page 10 of 11

11 c) [7 pts] How can you configure the cache to have exactly 6 compulsory misses, 1 conflict miss, and 1 capacity miss? If not possible, check not possible instead of filling in block size and associativity. Show your work. Block size: 4 bytes Associativity: 2 Not possible? Page 11 of 11