ECE 411 Exam 1 Practice Problems

Transcription

1 ECE 411 Exam 1 Practice Problems Topics Single-Cycle vs Multi-Cycle ISA Tradeoffs Performance Memory Hierarchy Caches (including interactions with VM) 1.) Suppose a single cycle design uses a clock period of 5ns. A multicycle version of the same design will require a clock period of 1ns. In the multicycle design, an ALU operation will take 3 cycles, loads will take 5 cycles, stores will take 3 cycles, and branches will take 2 cycles. Suppose an example program 1000 instructions long contains 50% ALU instructions, 20% loads, 20% stores, and 10% branches. What is the speedup for the multicycle design over the single cycle design? 2.) In a particular system, ALU operations take 3 cycles, branches take 2 cycles, and stores take 3 cycles. Loads take 2 cycles plus a delay due to memory latency, which is 100 cycles. a.) You run a program that contains 1000 instructions. 40% are ALU instructions, 10% are branches, 20% are stores, and 30% are loads. How long (in cycles) does the program take to run? b.) Suppose you add a cache to the system. Hits have a latency of 1 cycle. A from memory will hit in the cache 90% of the time. Stores are buffered. How long does it take to run the program from part a.)? c.) What is the speedup for the system in part b.) over the system in part a.)?

2 3.) A hypothetical computer system has a 32GB byte-addressable virtual memory with a 4MB page size, but only supports 4 GB of physical memory. This system has a 2-level cache architecture with both the L1 and L2 cache using a line size of 32 bytes. The L2 cache is known to be 2-way set associative, with an LRU replacement policy, and 256 KB in size, but the organization of the L1 cache is not given to you. Finally this system employs a direct-mapped TLB consisting of 8 entries. Below is a schematic presenting the interaction between cache and virtual memory. Fill in the unknown bitfield sizes between the angle brackets < >. 4.) Outtel, the world s largest semiconductor chip manufacturer, is hiring you to create the LC3b-86, a complex and expensive variant of your MP2.1 design. They would like you to add support a PUSH instruction:

3 Syntax: Instruction format: Instruction operation: PUSH SR [ opcode ] [ SR ] [xxxxxxxxx] MEM[R6] <= SR; R6 <= R6 + 2; The stack pointer is always assumed to be in R6. a) What changes must be made to the MP1 datapath in order to support the PUSH instruction? Be specific. b) Show the state machine for PUSH, starting at the DECODE state. For each state, show all necessary control signals (state actions) and transition conditions. 5.) Two compilers generate instructions of several classes: A - 1 cycle B - 2 cycles C - 3 cycles D - 5 cycles E - 10 cycles Compiler one generates machine code for a program using: - 5 million A, 7 million B, 4 million C, 1 million D, and none of class E. Compiler two generates machine code for a program using: - 3 million A, 2 million B, 1 million C, 1 million D, and 2 million of class E. i. ) Which takes longer in terms of execution time? ii.) Which executes faster in terms of MIPS? Assume 1GHz clock speed. 6.) give one advantage and one disadvantage for each ISA choice: RISC and CISC 7.) Choose the best answer pair: To exploit more locality, the degree of associativity. a. Temporal/decrease c. Temporal/increase b. Spatial/decrease d. Spatial/increase

4 8.) What is the difference between a write-back and write-through cache 9.) a) For the LC-3b ISA, the LDR instruction requires an Execute phase: TRUE FALSE b) The function of the Instruction Register is to point to the next instruction to be processed: TRUE FALSE c) In normal execution, the Program Counter is updated in the Decode phase of instruction execution: TRUE FALSE d) The Dirty Bit is not needed in write-through caches: TRUE FALSE 10.) Which of the following instructions need an evaluate address step (other than PC auto-increment) for their execution? Circle all instructions that apply: (i) ADD (ii) LDR (iii) NOT (iv) JMP 11.) Cache A is set-associative, Cache B is direct-mapped. Both A and B have data stores that are the same size and use the same block/line size. The size of the tag store (only counting tag bits -do not count the LRU bits) for A is B s. a. Same size as c. Smaller b. Larger d. Depends on degree of associativity 12.) Consider a single-level virtual memory system with a byte-addressable address space of 2 48 locations. If the size of a page table entry is 8 bytes and each page is 64KB, how large is the page table?

5 a. 256MB c. 32GB b. 4GB d. 8GB 13.) We learned about four different types of machines. One type is called the Stack machine. The key feature of the machine is that it uses a stack, push/pop and other operations to carry out the computation within the stack. Describe the other three types of machines. For each machine, list the machine name and write one sentence to describe the key feature of that machine. 14.) In single-processor systems, cache misses can be divided into three categories. List the name of each category and use one sentence to describe what it is. 15.) Why are physically addressed, virtually tagged caches avoided? 16.) A system with a 16 bit address space and byte-addressable memory has a directmapped cache that consists of 16 lines of 16 bytes each. The cache has a write-back, write-allocate policy. a) Given the following assumptions, fill out the table of memory access below. Then, calculate the total number of clock cycles it will take to complete the memory access. Use the cache table below to keep track of the current state of the cache Cache is initially empty Each cache access is a 16-bit load () or store (write) Single cycle cache hits 100 clock cycle penalty on a cache miss that has to overwrite a clean or invalid line 200 clock cycle penalty on a cache mass that has to evict a dirty line

6 type address tag index hit? evict clean? evict dirty? compulsory miss? conflict miss? #clock cycles 0x0000 0x0002 0x0020 0x0006 0x0130 0x0008

7 0x0230 0x0010 write 0x0280 0x0012 write 0x0380 0x0132 0x0014 0x0232 0x0016 write 0x0282 0x0018 write 0x0382 Total Number of Clock Cycles: b) You are given the task to speed up the execution of this memory access pattern, with the only constraint being that you cannot use any more total bits of storage than the existing cache. How would you change the cache architecture and why? 17.) List an advantage and disadvantage of each of the following cache addressing: a) PIPT b) VIPT c) VIVT d) Why is PIVT caching never used?

8 18.) a) Discuss an advantage of using a writeback cache instead of a writethrough cache. b) Discuss an advantage of using a writethrough cache instead of a writeback cache. c) The x86 has the ability to specify whether a range of memory addresses uses writeback or writethrough caching. Why would the x86 have this ability? (Hint: The x86 can use memory-mapped IO.)