A Software Solution for Hardware Vulnerabilities
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1 A Software Solution for Hardware Vulnerabilities Komail Dharsee University of Rochester Ethan Johnson University of Rochester John Criswell University of Rochester 1 / 22
2 Hardware Bugs! AMD recently shipped new chips to fix the FMA3 bug. User-space workloads can cause system-wide denial of service Manufacturers can disable buggy hardware features Features (and associated instructions) become unavailable! 2 / 22
3 Hardware Bugs in All Shapes and Sizes Hand-written machine code may freely trigger hardware bugs User space code can cause system-wide disruption Current hardware-enforced privilege is insufficient Unsafe privileged (kernel mode) execution Control Flow Integrity and Corrupted Instruction Pointers 3 / 22
4 Our Contributions Hardware Bug Survey Bug Mitigation System Design *Image Copyright, 1995 Pixar 4 / 22
5 Outline 1. Background Software Mediation with Hardware Bugs Secure Virtual Architecture (SVA) SVA s Virtual Instruction Set (V-ISA) 2. Design Safe & Verified Code Generation Run-time Checks SVA-OS Configuration 3. Hardware Bug Survey Results 4. Conclusions 5 / 22
6 Security Critical Hardware Bugs Hardware can have bugs due to design or manufacturing flaws. Attackers can leverage hardware bugs to violate security policies. We analyze processor bugs triggered through system configuration or execution. 6 / 22
7 Software Mediation of Hardware Bugs Systems should not allow execution of arbitrary native code. Utilize a small layer of software to restrict code expressiveness. Such software can be designed in tandem with hardware. 7 / 22
8 Utilizing Secure Virtual Architecture (SVA) SVA is a compiler-based virtual machine All code on an SVA system is compiled to SVA s Virtual ISA SVA enforces security policies by inserting run-time checks. Control Flow Integrity Memory Safety Software Fault Isolation SVA-OS provides an interface to low level operations Context Switching MMU Configuration Applications OS Kernel Secure Virtual Architecture VM Processor Virtual Instruction Set Native Instruction Set 8 / 22
9 Benefits of SVA s Virtual Instruction Set Architecture (V-ISA) Translation from V-ISA to N-ISA done ahead-of-time or just-in-time Separation of program memory Local branches which are calculated at run-time cannot be expressed Local Control Flow Graph (CFG) doesn t need to be computed Single Static Assignment (SSA) enables efficient data flow analysis 9 / 22
10 Outline 1. Background Software Mediation with Hardware Bugs Secure Virtual Architecture (SVA) SVA s Virtual Instruction Set (V-ISA) 2. Design Safe & Verified Code Generation Run-time Checks SVA-OS Configuration 3. Hardware Bug Survey Results 4. Conclusions 10 / 22
11 Design Overview Three methods for SVA to thwart security critical processor bugs 1. Safe & Verified Code Generation 2. Run-time Checks 3. SVA-OS Configuration 11 / 22
12 Safe & Verified Code Generation Modify code generators, ensuring unsafe instructions are not generated All code running on the system is compiled to the SVA V-ISA FSINCOS FSIN, FCOS 12 / 22
13 Safe & Verified Code Generation: Example 1 fld qword ptr [ rbp + qword -24] 2 fsincos 3 fstp qword ptr [ qword % eax ] 13 / 22
14 Safe & Verified Code Generation: Example 1 fld qword ptr [ rbp + qword -24] 2 fsincos 3 fstp qword ptr [ qword % eax ] 13 / 22
15 Safe & Verified Code Generation: Example 1 fld qword ptr [ rbp + qword -24] 2 fsincos 3 fstp qword ptr [ qword % eax ] 13 / 22
16 Safe & Verified Code Generation: Example 1 fld qword ptr [ rbp + qword -24] 2 fsincos 3 fstp qword ptr [ qword % eax ] 13 / 22
17 Safe & Verified Code Generation: Example 1 fld qword ptr [ rbp + qword -24] 2 fsin 3 fcos 4 fstp qword ptr [ qword % eax ] 14 / 22
18 Safe & Verified Code Generation: Example 1 fld qword ptr [ rbp + qword -24] 2 fsin 3 fcos 4 fstp qword ptr [ qword % eax ] 14 / 22
19 Safe & Verified Code Generation: Example 1 fld qword ptr [ rbp + qword -24] 2 fsin 3 fcos 4 fstp qword ptr [ qword % eax ] 14 / 22
20 Safe & Verified Code Generation Code Verification through post-generation static analysis ProgramPDA BugTriggerPDA BugDescFSA 15 / 22
21 Run-time Checks Necessary to deter bugs unthwarted by static analysis Native code may put the processor into an unsafe state SVA can insert run-time checks during code generation Run-time checks can alter processor state Bug trigger mitigations Recovery Routines syscall Bug: Disallow breakpoint on syscall. 16 / 22
22 Run-time Checks: Example 1 movl $0, -4(% rbp ) 2 movl %edi, -8(% rbp ) 3 movq %rsi, -16(% rbp ) 4 movl $5, -24(% rbp ) 5 syscall 6 cmpl $0, -24(% rbp ) 7 jle. LBB0_2 17 / 22
23 Run-time Checks: Example 1 movl $0, -4(% rbp ) 2 movl %edi, -8(% rbp ) 3 movq %rsi, -16(% rbp ) 4 movl $5, -24(% rbp ) 5 syscall 6 cmpl $0, -24(% rbp ) 7 jle. LBB0_2 17 / 22
24 Run-time Checks: Example 1 movl $0, -4(% rbp ) 2 movl %edi, -8(% rbp ) 3 movq %rsi, -16(% rbp ) 4 movl $5, -24(% rbp ) 5 syscall 6 cmpl $0, -24(% rbp ) 7 jle. LBB0_2 17 / 22
25 Run-time Checks: Example 1 movl $0, -4(% rbp ) 2 movl %edi, -8(% rbp ) 3 movq %rsi, -16(% rbp ) 4 movl $5, -24(% rbp ) 5 syscall 6 cmpl $0, -24(% rbp ) 7 jle. LBB0_2 17 / 22
26 Run-time Checks: Example 1 movl $0, -4(% rbp ) 2 movl %edi, -8(% rbp ) 3 movq %rsi, -16(% rbp ) 4 movl $5, -24(% rbp ) 5 syscall 6 cmpl $0, -24(% rbp ) 7 jle. LBB0_2 17 / 22
27 Run-time Checks: Example 1 movl $0, -4(% rbp ) 2 movl %edi, -8(% rbp ) 3 movq %rsi, -16(% rbp ) 4 movl $5, -24(% rbp ) 5 syscall 6 cmpl $0, -24(% rbp ) 7 jle. LBB0_2 17 / 22
28 Run-time Checks: Example 1 movl $0, -4(% rbp ) 2 movl %edi, -8(% rbp ) 3 movq %rsi, -16(% rbp ) 4 movl $5, -24(% rbp ) 5 nop 6 syscall 7 cmpl $0, -24(% rbp ) 8 jle. LBB0_2 18 / 22
29 Run-time Checks: Example 1 movl $0, -4(% rbp ) 2 movl %edi, -8(% rbp ) 3 movq %rsi, -16(% rbp ) 4 movl $5, -24(% rbp ) 5 nop 6 syscall 7 cmpl $0, -24(% rbp ) 8 jle. LBB0_2 18 / 22
30 Run-time Checks: Example 1 movl $0, -4(% rbp ) 2 movl %edi, -8(% rbp ) 3 movq %rsi, -16(% rbp ) 4 movl $5, -24(% rbp ) 5 nop 6 syscall 7 cmpl $0, -24(% rbp ) 8 jle. LBB0_2 18 / 22
31 Run-time Checks: Example 1 movl $0, -4(% rbp ) 2 movl %edi, -8(% rbp ) 3 movq %rsi, -16(% rbp ) 4 movl $5, -24(% rbp ) 5 nop 6 syscall 7 cmpl $0, -24(% rbp ) 8 jle. LBB0_2 18 / 22
32 Run-time Checks: Example 1 movl $0, -4(% rbp ) 2 movl %edi, -8(% rbp ) 3 movq %rsi, -16(% rbp ) 4 movl $5, -24(% rbp ) 5 nop 6 syscall 7 cmpl $0, -24(% rbp ) 8 jle. LBB0_2 18 / 22
33 Run-time Checks: Example 1 movl $0, -4(% rbp ) 2 movl %edi, -8(% rbp ) 3 movq %rsi, -16(% rbp ) 4 movl $5, -24(% rbp ) 5 nop 6 syscall 7 cmpl $0, -24(% rbp ) 8 jle. LBB0_2 18 / 22
34 Run-time Checks: Example 1 movl $0, -4(% rbp ) 2 movl %edi, -8(% rbp ) 3 movq %rsi, -16(% rbp ) 4 movl $5, -24(% rbp ) 5 nop 6 syscall 7 cmpl $0, -24(% rbp ) 8 jle. LBB0_2 18 / 22
35 Run-time Checks: Example 1 movl $0, -4(% rbp ) 2 movl %edi, -8(% rbp ) 3 movq %rsi, -16(% rbp ) 4 movl $5, -24(% rbp ) 5 nop 6 syscall 7 cmpl $0, -24(% rbp ) 8 jle. LBB0_2 18 / 22
36 SVA-OS Configuration SVA-OS provides an interface to the kernel for low-level tasks. SVA-OS prevents OS from expressing unsafe system configurations AMD Erratum #744: Trap registers not restored on power state transition SVA-OS disables the trap registers; abstracts away enabling capabilities 19 / 22
37 Outline 1. Background Software Mediation with Hardware Bugs Secure Virtual Architecture (SVA) SVA s Virtual Instruction Set (V-ISA) 2. Design Safe & Verified Code Generation Run-time Checks SVA-OS Configuration 3. Hardware Bug Survey Results 4. Conclusions 20 / 22
38 Bug Mitigation Survey Results Run-time Checks 20% Grammar Checks 13% 47% SVA-OS SVA Cannot Mitigate 7% 13% Insufficient Documentation *Excludes bugs in unsupported hardware virtualization features 21 / 22
39 Conclusions Design mitigates 80% of supported processor bugs Bug Survey shows high SVA-OS implementation priority Address bugs which trigger under complex set[s] of internal timing conditions. [1] Evaluate performance overhead Experiment with highly verified minimalistic components 22 / 22
40 Advanced Micro Devices Inc. Revision guide for AMD family 11h processors, December / 22
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