Handling of Interrupts & Exceptions

Transcription

1 CSE 2421: Systems I Low-Level Programming and Computer Organization Handling of Interrupts & Exceptions Read/Study: Bryant Presentation O Gojko Babić Computer Architecture (repeat) A modern meaning of the term computer architecture covers three aspects of computer design: instruction set architecture, computer organization and computer hardware. Instruction set architecture - ISA refers to the actual programmer visible machine interface such as instruction set, data representation, addressing, registers, memory organization and exception (i.e. interrupt) handling. One can think of a ISA as a hardware functionality of a given computer. A computer organization and computer hardware are two components of the implementation of a machine. g. babic Presentation O 2 1

2 Dual-Mode of CPU Operation CPU mode bit in Status register indicate the current CPU mode: 0 (=kernel) or 1 (=user). When an interrupt occurs, CPU hardware switches to the kernel mode. Switching to user mode (from kernel mode) done by setting CPU mode bit by some privilege instruction. Exception/Interrupt kernel user A priviledge instruction Privileged instructions can be executed only in kernel mode. g. babic Presentation O 3 Interrupt/Exception Classes There are two general classes of causes for an interrupt/exceptions. Notice that somehow different classifications could be also made and even different terminology can be used. Our classification includes all possible causes. 1. Interrupts caused by external signals (interrupts): Hardware Interrupts: Interrupt requests made via asserting signal on any of special external pins. Interrupt request lines IRQ s. Usually used by I/O controllers to signal normal I/O completion or a variety of error conditions. These interrupts also called I/O interrupts. g. babic Presentation O 4 2

3 Interrupts by External Signals Reset IRQ 1 IRQ 0 Timer g. babic Presentation O 5 Interrupt/Exception Classes (continued) 2. Interrupts as result of instruction execution (these are also called exceptions); There are two types of those interrupts: Type A caused by problems during instruction execution (faults): Address Error: a reference to a nonexistent or illegal memory address; Reserved Instruction: An instruction with undefined opcode field or a privileged instruction in User mode; Integer division by zero Floating Point Error Type B caused by special interrupt causing instructions (these are also called traps): MIPS processors: Syscall or any trap instruction executed; Intel processors: INT n instruction executed; g. babic Presentation O 6 3

4 MIPS Processor (repeat) Memory Main Processor Coprocessor 1 (FPU) Registers $0 Registers $0 $31 $31 Control A rithm e tic Logic unit Program Counter Lo Multiply divide Hi A rith m e tic unit Coprocessor 0 (traps and memory) Registers BadVAddr Status Cause EPC g. babic Presentation O 7 Coprocessor 0 Registers Coprocessor 0 CP0 is incorporated on the MIPS CPU chip and it provides functions necessary to support operating system: exception handling, memory management scheduling and control of critical resources. Coprocessor 0 (CP0) registers (partial list): Status register (CP0reg12) processor status and control; Cause register (CP0reg13) cause of the most recent interrupt; EPC register (CP0reg14) program counter at the last interrupt; BadVAddr register (CP0reg08) the address for the most recent address related exception; g. babic Presentation O 8 4

5 CPU Modes and Memory Address Space There are two modes MIPS CPU can operate in: kernel mode and user mode. The processor enters Kernel Mode at power-up, or as result of an interrupt or exception. The processor leaves Kernel Mode and enters User Mode when ERET instruction is executed. Memory address space is divided in two ranges (simplified): User address space: address range [0 7FFFFFFF 16 ] Kernel address space: address range [ FFFFFFFF 16 ] g. babic Presentation O 9 MIPS Privilege Instructions With CPU in User Mode, the program in execution has access only to the CPU and FPU registers, while when CPU operates in Kernel Mode, the program has access to the full capabilities of processor including CP0 registers. Privileged instructions will not be executed when the processor is in User mode and they will be considered (by CPU) as instructions with illegal op code. Examples of MIPS privileged instructions: any instruction that accesses Kernel address space, instructions that access CP0 registers, e.g. MFC0 and MTC0, ERET instruction. What about I/O instructions g. babic Presentation O 10 5

6 MIPS Interrupt Processing When any of the interrupts previously listed occurs, hardware should perform some predefined (by its ISA) tasks. Here we describe in some level of details how MIPS processor processes interrupts. MIPS does hardware interrupt processing in three steps. Step 1. (Saving content of PC) EPC register gets a value equal to either: the address of a faulty instruction if the instruction itself caused problems (e.g. address error, reserved instruction) or hardware malfunctioning detected (e.g. memory parity error), the address of the next instructions which would have been executed in all other cases, i.e. for interrupts caused by external causes or by those interrupt causing instructions. g. babic Presentation O 11 MIPS Interrupt Processing (continued) Step 2. (PC gets new value and interrupt cause code is saved) PC Thus, the next instruction is fetched from location Cause register a code of the interrupt Each interrupt has its code, e.g.: hardware interrupt = 0 address error exception (load/fatch or store) = 4 or 5 bus error exception (fetch or load/store)= 6 or 7 syscall execution = 8 illegal op-code or reserved instruction exception= 10 trap exception floating point exception = 15 Step 3. (Mode of CPU operation set to kernel mode) CPU mode bit 0; g. babic Presentation O 12 6

7 Hardware Interrupt Processing in General Hardware interrupt processing first saves the address of the interrupted instruction. Intel x86-64 architecture uses a system stack (in memory) to save the address, while in MIPS architecture, EPC register is used. Hardware interrupt processing then loads PC with the new address. In Intel x86-64 architecture, new content of PC comes from one of special memory locations (for each of interrupt/exception case) through special tables that have to be setup in advance. In MIPS architecture, PC always gets the value , while Cause register indicates a type of interrupt or exception. Hardware interrupt processing sets CPU into kernel mode. g. babic Presentation O 13 Compiling hello.c #include <stdio.h> int main() { printf("hello World"); return 0; } Compilation command: gcc -O1 S hello.c generated this x86-64 assembly code (with minor changes in red):.file "hello.c".lc0:.string "hello World".text.globl main.type main: subq $8, %rsp movq $.LC0, %rdi movq $0, %rax call printf movq $0, %rax addq $8, %rsp ret g. babic Presentation K 14 7

8 Source: Bryant & O Hallaron: Computer Systems, 2 nd edition System calls are provided on IA32 via a exception causing instruction int n, where n can be 0-255, although historically system calls are provided through exception 128 (0x80). By convention, register %eax contains the system call number, and registers %ebx, %ecx, %edx, %esi, %edi and %ebp contain up to 6 arguments. Examples of system call numbers: exit: 1 fork 2 read 3 write 4 open: 5 Linux/IA32 System Calls close: 6 wait: 7 creat: 8 unlink: 10 execve: 11 lseek: 19 getpid: 20 kill: 37 pipe: 42 umask: 60 dup2: 63 gettimeofday: 78 g. babic Presentation B 15 int main() { write (1, hello world,11); return 0 } /*This is a version of the familiar hello program*/ On the right, we have an implementation of the hello program directly with Linux system calls. Linux/IA32 System Calls.section.data string:.ascii "hello world string_end:.equ len, string_end - string.section.text.globl main main: # system call: write(1, "hello, world\n", 11) movl $4, %eax # System call number 4 movl $1, %ebx # stdout has descriptor 1 movl $string, %ecx # hello world string movl $len, %edx # String length int $0x80 # System call code movl $0, %eax ret g. babic 16 8