Lecture 38 VHDL Description: Addition of Two [5 5] Matrices
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1 Lecture 38 VHDL Description: Addition of Two [5 5] Matrices -- First, write a package to declare a two-dimensional --array with five elements library IEEE; use IEEE.STD_LOGIC_1164.all; package twodm_array is constant N : integer := 4; -- N+1 is the number of elements in the array. -- This is an NxN matrix with N rows and N columns. subtype wordg is integer; type strng1 is array (N downto 0) of wordg; type strng2 is array (N downto 0) of strng1; end twodm_array; --Second, write the code for addition library IEEE; use IEEE.STD_LOGIC_1164.ALL; use work.twodm_array.all; entity matrices is Port (x, y : strng2; z : out strng2); --strng2 type is 5x5 matrix end matrices; architecture sum of matrices is com : process (x, y) variable t : integer := 0; for i in 0 to 4 loop for j in 0 to 4 loop t := x(i)(j) + y(i)(j); z(i)(j) <= t;
2 end loop; end loop; end process com; end sum; MIXED - TYPE DESCRIPTION EXAMPLES HDL Description of an ALU VHDL and Verilog FIGURE7.3 Block diagram of the arithmetic - logic unit.
3 VHDL ALU Description --Here we write the code for a package for user-defined --type and function. library ieee; use ieee.std_logic_1164.all; use IEEE.STD_LOGIC_1164.ALL,IEEE.NUMERIC_STD.ALL; package codes_arithm is type op is (add, mul, divide, none); -- type op is for the operation codes for the ALU. The operations we -- need are: addition, multiplication, division, and no operation function TO_UNSIGN (b : integer) return unsigned; end; package body codes_arithm is function TO_UNSIGN (b : integer) return unsigned is --The function converts integer numbers to unsigned. This function --can be omitted if it is included in a vendor's package. The vendor's -- package, if available, should be attached. variable temp : integer; variable bin : unsigned (5 downto 0); temp := b; for j in 0 to 5 loop if (temp MOD 2 = 1) then bin (j) := '1'; else bin (j) := '0'; end if;
4 temp := temp/2; end loop; return bin; end TO_UNSIGN; end codes_arithm; --Now we write the code for the ALU library IEEE; use IEEE.STD_LOGIC_1164.ALL; use ieee.numeric_std.all; use work.codes_arithm.all; --The above use statement is to make the user- --defined package "codes_arithm.all" visible to this module. entity ALU_mixed is port (a, b : in unsigned (2 downto 0); cin : in std_logic; opc : in op; z : out unsigned (5 downto 0)); --opc is of type "op"; type op is defined in the --user-defined package "codes_arithm" end ALU_mixed; architecture ALU_mixed of ALU_mixed is signal c0, c1 : std_logic; signal p, g : unsigned (2 downto 0); signal temp1 : unsigned (5 downto 0); --The following is a data flow-description of a 3-bit lookahead --adder. The sum is stored in the three least significant bits of --temp1. The carry out is stored in temp1(3).
5 g(0) <= a(0) and b(0); g(1) <= a(1) and b(1); g(2) <= a(2) and b(2); p(0) <= a(0) or b(0); p(1) <= a(1) or b(1); p(2) <= a(2) or b(2); c0 <= g(0) or (p(0) and cin); c1 <= g(1) or (p(1) and g(0)) or (p(1) and p(0) and cin); temp1(3) <= g(2) or (p(2) and g(1)) or (p(2) and p(1) and g(0)) or (p(2) and p(1) and p(0) and cin); --temp1(3) is the final carryout of the adders temp1(0) <= (p(0) xor g(0)) xor cin; temp1(1) <= (p(1) xor g(1)) xor c0; temp1(2) <= (p(2) xor g(2)) xor c1; temp1 (5 downto 4) <= "00"; process (a, b, cin, opc, temp1) --The following is a behavioral description for the multiplication --and division functions of the ALU. variable temp : unsigned (5 downto 0); variable a1, a2, a3 : integer; a1 := TO_INTEGER (a); a2 := TO_INTEGER (b); --The predefined function "TO_INTEGER" --converts unsigned to integer. --The function is a member of the VHDL package IEEE.numeric. case opc is when mul => a3 := a1 * a2; temp := TO_UNSIGN(a3); --The function "TO_UNSIGN" is a user-defined function --written in the user-defined package "codes_arithm." when divide =>
6 a3 := a1 / a2; temp := TO_UNSIGN(a3); when add => temp := temp1; when none => null; end case; z <= temp; end process; end ALU_mixed; Verilog ALU Description module ALU_mixed (a, b, cin, opc, z); parameter add = 0; parameter mul = 1; parameter divide = 2; parameter nop = 3; input [2:0] a, b; input cin; input [1:0] opc; output [5:0] z; reg [5:0] z; wire [5:0] temp1; wire [2:0] g, p; wire c0, c1; // The following is data-flow description // for 3-bit lookahead adder assign g[0] = a[0] & b[0]; assign g[1] = a[1] & b[1]; assign g[2] = a[2] & b[2]; assign p[0] = a[0] b[0]; assign p[1] = a[1] b[1]; assign p[2] = a[2]
7 b[2]; assign c0 = g[0] (p[0] & cin); assign c1 = g[1] (p[1] & g[0]) (p[1] & p[0] & cin); assign temp1[3] = g[2] (p[2] & g[1]) (p[2] & p[1] & g[0]) (p[2] & p[1] & p[0] & cin); // temp1[3] is the final carryout of the adders assign temp1[0] = (p[0] ^ g[0]) ^ cin; assign temp1[1] = (p[1] ^ g[1]) ^ c0; assign temp1[2] = (p[2] ^ g[2]) ^ c1; assign temp1[5:4] = 2'b00; //The following is behavioral description (a, b, cin, opc, temp1) case (opc) mul : z = a * b; add : z = temp1; end divide : z = a / b; nop : z = z; endcase endmodule
8 FIGURE Simulation output of the ALU
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