Basic Language Constructs of VHDL
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1 Basic Language Constructs of VHDL Chapter 3 1
2 Outline 1. Basic VHDL program 2. Lexical elements and program format 3. Objects 4. Data type and operators Chapter 3 2
3 1. Basic VHDL program Chapter 3 3
4 Design unit Building blocks in a VHDL program Each design unit is analyzed and stored independently Types of design unit: entity declaration architecture body package declaration package body configuration Chapter 3 4
5 Entity declaration Simplified syntax Chapter 3 5
6 mode: in: flow into the circuit out: flow out of the circuit inout: bi-directional E.g. Chapter 3 6
7 A common mistake with mode Chapter 3 7
8 Fix: use an internal signal Chapter 3 8
9 Architecture body Simplified syntax An entity declaration can be associated with multiple architecture bodies Chapter 3 9
10 E.g. Chapter 3 10
11 Other design units Package declaration/body: collection of commonly used items, such as data types, constants, subprograms and components Configuration: specify which architecture body is to be bound with the entity declaration Chapter 3 11
12 VHDL Library A place to store the analyzed design units Normally mapped to a directory in the host computer Software defines the mapping between the symbolic library and physical location Default library: work Library ieee is used for many ieee packages Chapter 3 12
13 E.g. Line 1: invoke a library named ieee Line 2: makes std_logic_1164 package visible to the subsequent design units The package is normally needed for the std_logic/std_logic_vector data type Chapter 3 13
14 Processing of VHDL code Analysis Performed on design unit basis Check the syntax and translate the unit into an intermediate form Store it in a library Elaboration Bind architecture body with entity Substitute the instantiated components with architecture description Create a flattened ' description Execution Simulation or synthesis Chapter 3 14
15 2. Lexical elements and program format Chapter 3 15
16 Lexical element: Lexical elements Basic syntactical units in a VHDL program Types of Lexical elements: Comments Identifiers Reserved words Numbers Characters Strings Chapter 3 16
17 Starts with - - Just for clarity e.g., Comments Chapter 3 17
18 Identifier Identifier is the name of an object Basic rules: Can only contain alphabetic letters, decimal digits and underscore The first character must be a letter The last character cannot be an underscore Two successive underscores are not allowed Chapter 3 18
19 Valid examples: A10, next_state, NextState, mem_addr_enable Invalid examples: sig#3, _X10, 7segment, X10_, hi there VHDL is case insensitive: Following identifiers are the same: nextstate, NextState, NEXTSTATE, nextstate Chapter 3 19
20 Reserved words Chapter 3 20
21 Numbers, characters and strings Numbers Integer: 0, 1234, 98E7 Real: 0.0, or 9.87E6 Base 2: 2#101101# Characters A, Z, 1 Strings Hello, Note 0 and 0 are different 2#101101# and are different Chapter 3 21
22 Program format VHDL is free-format : blank space, tab, new-line can be freely inserted e.g., the following are the same Chapter 3 22
23 Chapter 3 23
24 A good header Chapter 3 24
25 3. Objects Chapter 3 25
26 Objects A named item that hold a value of specific data type Four kinds of objects Signal Variable Constant File (cannot be synthesized) Related construct Alias Chapter 3 26
27 Signal Declared in the architecture body's declaration section Signal declaration: signal signal_name, signal_name,... : data_type Signal assignment: signal_name <= projected_waveform; Ports in entity declaration are considered as signals Can be interpreted as wires or wires with memory (i.e., FFs, latches etc.) Chapter 3 27
28 Variable Declared and used inside a process Variable declaration: variable variable_name,... : data_type Variable assignment: variable_name := value_expression; Contains no timing info (immediate assignment) Used as in traditional PL: a symbolic memory location where a value can be stored and modified No direct hardware counterpart Chapter 3 28
29 Constant Value cannot be changed Constant declaration: constant const_name,... : data_type := value_expression Used to enhance readability E.g., Chapter 3 29
30 It is a good idea to avoid hard literals Chapter 3 30
31 Alias Not an object Alternative name for an object Used to enhance readability E.g., Chapter 3 31
32 4. Data type and operators Standard VHDL IEEE1164_std_logic package IEEE numeric_std package Chapter 3 32
33 Data type Definition of data type A set of values that an object can assume A set of operations that can be performed on objects of this data type VHDL is a strongly-typed language an object can only be assigned with a value of its type only the operations defined with the data type can be performed on the object Chapter 3 33
34 Data types in standard VHDL integer: Minimal range: -(2^31-1) to 2^31-1 Two subtypes: natural, positive boolean: (false, true) bit: ('0', '1') Not capable enough bit_vector: a one-dimensional array of bit Chapter 3 34
35 Operators in standard VHDL Chapter 3 35
36 Chapter 3 36
37 IEEE std_logic_1164 package What s wrong with bit? New data type: std_logic, std_logic_vector std_logic: 9 values: ('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-') '0', '1': forcing logic 0 and forcing logic 1 'Z': high-impedance, as in a tri-state buffer. 'L', 'H': weak logic 0 and weak logic 1, as in wiredlogic 'X', 'W': unknown and weak unknown 'U': for uninitialized '-': don't-care. Chapter 3 37
38 std_logic_vector an array of elements with std_logic data type Imply a bus E.g., signal a: std_logic_vector(7 downto 0); Another form (less desired) signal a: std_logic_vector(0 to 7); Need to invoke package to use the data type: library ieee; use ieee.std_logic_1164.all; Chapter 3 38
39 Overloaded operator IEEE std_logic_1164 package Which standard VHDL operators can be applied to std_logic and std_logic_vector? Overloading: same operator of different data types Overloaded operators in std_logic_1164 package Chapter 3 39
40 Type conversion function in std_logic_1164 package: Chapter 3 40
41 E.g., Chapter 3 41
42 Operators over an array data type Relational operators for array operands must have the same element type but their lengths may differ Two arrays are compared element by element, form the left most element All following returns true "011"="011", "011">"010", "011">"00010", "0110">"011" Chapter 3 42
43 Concatenation operator (&) e.g., y <= "00" & a(7 downto 2); y <= a(7) & a(7) & a(7 downto 2); y <= a(1 downto 0) & a(7 downto 2); Chapter 3 43
44 Array aggregate Aggregate is a VHDL construct to assign a value to an array-typed object E.g., a <= " "; a <= (7=>'1', 6=>'0', 0=>'0', 1=>'0', 5=>'1', 4=>'0', 3=>'0', 2=>'1'); a <= (7 5=>'1', =>'0'); a <= (7 5=>'1', others=>'0'); E.g., a <= " " a <= (others=>'0'); Chapter 3 44
45 IEEE numeric_std package How to infer arithmetic operators? In standard VHDL: signal a, b, sum: integer;... sum <= a + b; What s wrong with integer data type? Chapter 3 45
46 IEEE numeric_std package: define integer as a an array of elements of std_logic Two new data types: unsigned, signed The array interpreted as an unsigned or signed binary number E.g., signal x, y: signed(15 downto 0); Need to invoke the package to use the data type library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; Chapter 3 46
47 Overloaded operators in IEEE numeric_std package Chapter 3 47
48 E.g., Chapter 3 48
49 New functions in IEEE numeric_std package Chapter 3 49
50 Type conversion Std_logic_vector, unsigned, signed are defined as an array of element of std_logic They considered as three different data types in VHDL Type conversion between data types: type conversion function Type casting (for closely related data types) Chapter 3 50
51 Type conversion between numberrelated data types Chapter 3 51
52 E.g. library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;... signal s1, s2, s3, s4, s5, s6: std_logic_vector(3 downto 0); signal u1, u2, u3, u4, u6, u7: unsigned(3 downto 0); signal sg: signed(3 downto 0); Chapter 3 52
53 E.g. library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;... signal s1, s2, s3, s4, s5, s6: std_logic_vector(3 downto 0); signal u1, u2, u3, u4, u6, u7: unsigned(3 downto 0); signal sg: signed(3 downto 0); Chapter 3 53
54 Ok u3 <= u2 + u1; --- ok, both operands unsigned u4 <= u2 + 1; --- ok, operands unsigned and natural Wrong u5 <= sg; -- type mismatch u6 <= 5; -- type mismatch Fix u5 <= unsigned(sg); -- type casting u6 <= to_unsigned(5,4); -- conversion function Chapter 3 54
55 Wrong u7 <= sg + u1; -- + undefined over the types Fix u7 <= unsigned(sg) + u1; -- ok, but be careful Wrong s3 <= u3; -- type mismatch s4 <= 5; -- type mismatch Fix s3 <= std_logic_vector(u3); -- type casting s4 <= std_logic_vector(to_unsigned(5,4)); Chapter 3 55
56 Wrong s5 <= s2 + s1; + undefined over std_logic_vector s6 <= s2 + 1; + undefined Fix s5 <= std_logic_vector(unsigned(s2) + unsigned(s1)); s6 <= std_logic_vector(unsigned(s2) + 1); Chapter 3 56
57 Non-IEEE package Package by Synopsys std_logic_arith: Similar to numeric_std New data types: unsigned, signed Details are different std_logic_unsigned/ std_logic_signed Treat std_logic_vector as unsigned and signed numbers i.e., overload std_logic_vector with arith operations Chapter 3 57
58 Software vendors frequently store them in ieee library: E.g., library ieee; use ieee.std_logic_1164.all; use ieee.std_arith_unsigned.all;... signal s1, s2, s3, s4, s5, s6: std_logic_vector(3 downto 0);... s5 <= s2 + s1; -- ok, + overloaded with std_logic_vector s6 <= s2 + 1; -- ok, + overloaded with std_logic_vector Chapter 3 58
59 Only one of the std_logic_unsigned and std_logic_signed packages can be used The std_logic_unsigned/std_logic_signed packages beat the motivation behind a strongly-typed language Numeric_std is preferred Chapter 3 59
60 Guidelines for VHDL (Synth) Use std_logic_vector and std_logic (not bit_vector or bit) Use numeric_std (not std_logic_arith) Use descending ranges Parenthesis Avoid new user-defined types Don t use := to assign initial signal values Relational ops with identical length Chapter 3 60
61 Formatting Guidelines Use headers Be consistent with case Use space, blank lines, parenthesis Comments Symbolic names (not hard literals) Meaningful identifiers Suffixes for signal properties (e.g. _n) Avoid lines > 72 chars Chapter 3 61
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