Register Allocation Amitabha Sanyal Department of Computer Science & Engineering IIT Bombay

Transcription

1 Register Allocation Amitabha Sanyal Department of Computer Science & Engineering IIT Bombay

2 Global Register Allocation Register Allocation : AS 1

3 Possible Approaches Approach 1: Divide the register set into two parts. Local register set: For evaluating expressions. Global register set: For holding frequently used variables across longer stretches of code. A global register allocation phase allocates register to variables over certain regions. A Sethi-Ullman or Aho-Johnson like algorithm generates code for expressions Variables at leaf are either in global registers, or can be loaded in local registers if available, or operated from memory interior nodes are evaluated and held in registers, or spilled and operated from memory. Register Allocation : AS 2

4 Possible Approaches Approach 2: No partitioning of register set. Generate code for expression using Sethi-Ullman or Aho-Johnson or BURG. However, think of the registers as being symbolic registers. A global register allocation strategy assigns physical registers to to both, variables and symbolic registers. Using Sethi-Ullman or Aho-Johnson ensures good order of evaluation. Results in short live ranges - good for register allocation. Using Sethi-Ullman, Aho-Johnson or BURS ensures great code selection. Register Allocation : AS 3

5 Global Register Allocation Problem To decide: which variables values should be held in registers, and in what regions of the program so as to ensure that heavily used variables are operated out of registers, and minimize register spills into memory. Best known solution is register allocation through graph coloring. Register Allocation : AS 4

6 A Motivating Example Consider the program shown below: x = 2; y = 4; w = x + y z = x + w u = x * y x = z * 2 s1 s2 s3 s4 s5 s6 Identify webs (defined later) in the program. Each web is held in a symbolic register. s1 = 2; s2 = 4; s3 = s1 + s2 s4 = s1 + 1 s5 = s1 * s2 s6 = s4 * 2 Register Allocation : AS 5

7 A Motivating Example Next, build an interference graph. Color interference graph with the same number of colors as registers. R2 s3 R1 s1 R1 s5 s2 R3 s4 R2 s6 R2 Replace symbolic registers by real registers. R1 = 2; R3 = 4; R2 = R1 + R3 R2 = R1 + 1 R1 = R1 * R3 R2 = R2 * 2 Register Allocation : AS 6

8 Register Allocation by Graph Coloring Major steps Identifying units of allocation web identification. Representing webs - rewriting using symbolic registers. Reducing the number of live ranges (symbolic) register coalescing. Explicating allocation constraints constructing the interference graph. Estimating penalties of non-allocation spill cost estimation. The coloring logic Reducing the problem size pruning obviously colorable edges. Running out of colors selecting registers for spilling. Register Allocation : AS 7

9 A Running Example Original program B1: a := b+c*d d := d*b a e := a+f B2: f := a*d e B3: b := d+f e := a c*b B4: b := d+c Register Allocation : AS 8

10 A Running Example After Sethi-Ullman B1: t1 = b t2 = c t2 = t2 * d t1 = t1 + t2 a = t1 t1 = d t1 = t1 * b t1 = t1 a d = t1 t1 = a t1 = t1 + f e = t1 B2: t1 = a B3: t1 = d t1 = t1 * d t1 = t1 e f = t1 t1 = t1 + f b = t1 t1 = a t2 = c t2 = t2 * b t1 = t1 t2 e = t1 B4: t1 = d t1 = t1 + c b = t1 Register Allocation : AS 9

11 Candidates for Allocation Webs A variable is not a good candidate for allocation of register. a variable can be used for different purposes in different parts of the program. forcing the variable to be in the same register unnecessary constraint. A good candidate for register is a web. A web consists of intersecting du-chains. x = 1 x = 2 z = x + 3 x = 4 y = x + 1 p = x + 7 q = y + z Register Allocation : AS 10

12 Representing Webs by Symbolic Registers Variables corresponding to webs are replaced by symbolic registers. B1: s1 = sb1 s2 = sc s3 = s2 * sd1 s4 = s1 + s3 sa = s4 s5 = sd1 s6 = s5 * sb1 s7 = s6 sa sd2 = s7 s8 = sa s9 = s8 + sf1 se1 = s9 B2: s10 = sa s11 = s10 * sd2 s12 = s11 se1 sf2 = s12 B3: s13 = sd2 s14 = s13 + sf1 sb2 = s14 s15 = sa s16 = sc s17 = s16 * sb2 s18 = s15 s17 se2 = s18 B4: s19 = sd2 s20 = s19 + sc sb3 = s20 Register Allocation : AS 11

13 Register coalescing Number of live ranges can be decreased by the transformation illustrated below sj si si = sj Neither si nor sj defined along this path sj No other definition... =..si.. of si reaches here... =..sj..... =..sj..... =..sj.. Example of situation where copy statements can be generated following Sethi- Ullman algorithm, loading a left leaf into a register. Register Allocation : AS 12

14 Running Example After Register Coalescing B1: s3 = sc * sd1 s4 = sb1 + s3 s6 = sd1 * sb1 s7 = s6 s4 s9 = s4 + sf1 e = s9 B2: s11 = s4 * s7 s12 = s11 s9 f = s12 B3: s14 = s7 + sf1 s17 = sc * s14 s18 = s4 s17 e = s18 B4: s20 = s7 + sc b = s20 Register Allocation : AS 13

15 What is interference? Naive definition: two webs interfere if they are live (are present) at a common point in the program. 2n+1 interfering webs by this definition. Better definition: two webs interfere when the definition point of one intersects with the other. n interfering webs in the example. cond a1 =... a2 = an =... b1 =... b2 = bn =... cond 2n webs live at this point... = a1... = a = an... = b1... = b = bn Register Allocation : AS 14

16 Estimating Spill Costs Spilling a web means inserting a store after each definition of the web variable. inserting a load before each use of the web variable d1: x =... d2: x =... u1:...=..x.. u2:...=..x.. d1: x =... d2: x =... m = x m = x x = m u1:...=..x.. x = m u2:...=..x.. spilling converts a large web into many very small webs. Register Allocation : AS 15

17 Estimating Spill Costs The spill cost of a web is the average of spill costs along all the paths in the web. The spill cost along a path p is (loads p LOADCOST + stores p STORECOST) 10 d where: loads p is the number of loads introduced in the path p due to spilling. stores p is the number of stores, and d is the nesting depth of the web. Register Allocation : AS 16

18 The coloring logic Chaitin allocator While stack is not empty, do: Prune: If there is a node whose degree is less than the total number of colors (registers), remove the node and stack it. Such a node is always colorable. Spill: If there is no such node available, spill a web with least spill cost, and readjust the interference graph. Take out elements from the stack and color them in turn. Register Allocation : AS 17

19 The coloring logic Chaitin allocator cannot color the diamond graph with two colors. R B B It is true that not colorable degree more than available colors However, Chaitin s allocator assumes that degree more than available colors not colorable which need not be true. R Register Allocation : AS 18

20 The coloring logic Chaitin allocator spills more than necessary for the following example: subroutine SVD(M, N,..) do I = 1,N do J = 1, M A(I,J) = B(I,J) end endo do deeply nested loops endo do deeply nested loops endo do deeply nested loops endo do deeply nested loops endo N I M J It takes an early spilling decision which it cannot reverse later Register Allocation : AS 19

21 The coloring logic Preston-Briggs allocator While stack is not empty, do: Prune: If there is a node whose degree is less than the total number of colors (registers), remove the node and stack it. Such a node is always colorable. Spill: If there is no such node available, choose a web with least spill cost, mark it as a candidate for spilling and stack it. Examine elements from the stack. If the element is a colorable node, assign it a color If it is a candidate for spilling, spill, readjust the interference graph and repeat the entire process Register Allocation : AS 20

22 Running Example Rewriting code with allocated registers B1: r2 := r7 * r3 r5 := r4 + r2 /* r5(a)=b+c*d */ r2 := r3 * r4 r4 := r2 r5 /* r4(d)=d*b a */ r3 := r5 + r6 e := r3 /* e=a+f */ B2: r2 := r5 * r4 r2 := r2 r3 f := r2 /* f=a*d e */ B3: r2 := r4 + r6 /* r2(b)=d+f */ r3 := r7 * r2 r2 := r5 r3 e := r2 /* e=a c*b*/ B4: r2 := r4 + r7 b := r2 /* b=d+c*/ Register Allocation : AS 21

23 Shaping the code Many processors require the code to be of the form: ri = ri op rj, or ri = ri op m we can apply the following transformations: 1. Replace ri := rj op rk by rj := rj op rk provided rj is not live beyond this instruction. Replace ri := rj op rk by rk := rk op rj provided op is commutative, and rk is not live beyond this instruction. Replace each subsequent use of ri by rj or rk. 2. Otherwise, replace each instruction ri := rj op rk by the pair of instructions ri := rj and ri := ri op rk. Register Allocation : AS 22

24 Running Example After shaping code B1: r2 := r7 r2 := r2 * r3 r5 := r4 r5 := r5 + r2 r4 := r4 * r3 r4 := r4 r5 r3 := r5 r3 := r3 + r6 e := r3 # # * # B3: r6 := r6 + r4 r6 := r6 * r7 r5 := r5 r6 e := r5 * * * B2: r5 := r5 * r4 r5 := r5 r3 f := r5 * * B4: r4 := r4 + r7 b := r4 * Register Allocation : AS 23