Register Allocation. Ina Schaefer Selected Aspects of Compilers 100. Register Allocation

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1 Efficient code has to use the available registers on the target machine as much as possible: Accessing registers is much faster then accessing memory (the same holds for cache). Two Aspects: : Determine which variables are implemented by registers at which positions. Register Assignment: Determine which register implements which variable at which positions. With register allocation, we mean both aspects. Ina Schaefer Selected Aspects of Compilers 100 (2) Goals of 1. Generate code that requires as little registers as possible 2. Avoid unnecessary memory accesses, i.e., not only temporaries, but also program variables are implemented by registers. 3. Allocate registers such that they can be used as much as possible, i.e., registers should not be used for variables that are only rarely accessed. 4. Obey programmer s requirements. Ina Schaefer Selected Aspects of Compilers 101

2 (3) Outline Algorithm interleaving code generation and register allocation for nested expressions (cf. Goal 1) Algorithm for procedure-local register allocation (cf. Goals 2 and 3) Combination and other aspects Ina Schaefer Selected Aspects of Compilers 102 The algorithm by Sethi and Ullmann is an example of an integrated approach for register allocation and code generation. (cf. Wilhelm, Maurer, Sect , p. 584 ff) Input: An assignment with a nested expression on the right hand side Assign ( Var, Exp ) Exp = BinExp Var BinExp ( Exp, Op, Exp ) Var ( Ident ) Ina Schaefer Selected Aspects of Compilers 103

3 (2) Output: Machine or intermediate language code with assigned registers. We consider two-address code, i.e., code with one memory access at maximum. The machine has r registers represented by R 0,..., R r 1. Ri := M[V] M[V] := Ri Ri := Ri op M[V] Ri := Ri op Rj Ina Schaefer Selected Aspects of Compilers 104 Example: Code Generation w/ Consider f := (a + b) (c (d + e)) Assume that there are two registers R0 and R1 available for the translation. Result of direct translation: R0 := M[a] R0 := R0 + M[b] R1 := M[d] R1 := R1 + M[e] M[t1] := R1 R1 := M[c] R1 := R1 M[t1] R0 := R0 R1 M[f] := R0 Ina Schaefer Selected Aspects of Compilers 105

4 Example: Code Generation w/ (2) Result of Sethi-Ullmann-Algorithm: R0 := M[c] R1 := M[d] R1 := R1 + M[e] R0 := R0 R1 R1 := M[a] R1 := R1 + M[b] R1 := R1 R0 M[f] := R1 More efficient, because it uses one instruction less and does not need to store intermediate results. Ina Schaefer Selected Aspects of Compilers 106 Sethi-Ullmann Algorithm Goal: Minimize number of registers and number of temporaries. Idea: Generate code for subexpression requiring more registers first. Procedure: Define function regbed that computes the number of registers needed for an expression Generate code for an expression E = BinExp(L,OP,R); Ina Schaefer Selected Aspects of Compilers 107

5 Sethi-Ullmann Algorithm (2) We use the following notations: v_reg(e): the set of available registers for the translation of E v_tmp(e): the set of addresses where values can be stored temporarily when translating E cell(e): register/memory cell where the result of E is stored vr = v_reg(e) denotes the number of available registers Ina Schaefer Selected Aspects of Compilers 108 Sethi-Ullmann Algorithm (3) We distinguish the following cases: 1. regbed(l) < vr 2. regbed(l) vr and regbed(r) < vr 3. regbed(l) vr and redbed(r) vr Ina Schaefer Selected Aspects of Compilers 109

6 Sethi-Ullmann Algorithm (4) Case 1: regbed(l) < vr Generate code for R using v_reg(e) and v_tmp(e) with result in cell(r) Generate code for L using v_reg(e) \{ cell(r) } and v_tmp(e) with result in cell(l) Generate code for the operation cell(l) := cell(l) OP cell(r) Set cell(e) = cell(l) Ina Schaefer Selected Aspects of Compilers 110 Sethi-Ullmann Algorithm (5) Case 2: regbed(l) vr and regbed(r) < vr Generate code for L using v_reg(e) and v_tmp(e) with result in cell(l) Generate code for R using v_reg(e) \{ cell(l) } and v_tmp(e) with result in cell(r) Generate code for the operation cell(l) := cell(l) OP cell(r) Set cell(e) = cell(l) Ina Schaefer Selected Aspects of Compilers 111

7 Sethi-Ullmann Algorithm (6) Case 3: regbed(l) vr and redbed(r) vr Generate code for R using v_reg(e) and v_tmp(e) with result in cell(r) Generate code M[first(v_tmp(E))] := cell(r) Generate code for L using v_reg(e) and rest(v_tmp(e)) with result in cell(l) Generate code for the operation cell(l) := cell(l) OP M[first(v_tmp(E))] Set cell(e) = cell(l) Ina Schaefer Selected Aspects of Compilers 112 Sethi-Ullmann Algorithm (7) Function regbed in MAX Notation (can be realized by S-Attribution): ATT regbed( Exp@ E ) Nat: IF Assign@<_,Var@ E> : 0 BinExp@< Var@ E,_,_> : 1 BinExp@<_,_,Var@ E > : 0 BinExp@< L,_, R > E : IF regbed(l)=regbed(r) THEN regbed(l) + 1 ELSE max( regbed(l), regbed(r) ) ELSE nil // Fall kommt nicht vor Ina Schaefer Selected Aspects of Compilers 113

8 Example: Sethi-Ullman Algorithm Consider f:= (( a + b ) - (c + d)) * (a - (d+e)) Attributes: v_reg v_tmp regbed zelle 12T Ina Schaefer Selected Aspects of Compilers 114 Example: Sethi-Ullman Algorithm (2) Assign Var f 12T BinExp * (3.) 3 1 T BinExp 12T BinExp (1.) (1.) 2 BinExp 2 12 BinExp 1 Var 12T BinExp a (2.) (1.) (1.) Var a Var Var Var Var Var 1 b 0 c 1 d 0 d 1 e 0 Ina Schaefer Selected Aspects of Compilers 115

9 Example: Sethi-Ullman Algorithm (3) For formalizing the algorithm, we realize the set of available registers and addresses for storing temporaries with lists, where the list RL of registers is non-empty the list AL of addresses is long enough the result cell is always a register which is the first in RL, i.e., first(rl) the function exchange switches the first two elements of a list, fst returns the first element of the list, rest returns the tail of the list Ina Schaefer Selected Aspects of Compilers 116 Example: Sethi-Ullman Algorithm (4) Remarks: The algorithm generates 2AC which is optimal with respect to the number of instructions and the number of temporaries if the expression has no common subexpressions. The algorithm shows the dependency between code generation and register allocation and vice versa. In a procedural implementation, register and address lists can be realized by a global stack. Ina Schaefer Selected Aspects of Compilers 117

10 Example: Sethi-Ullman Algorithm (5) In the following, the function expcode for code generation is given in MAX Notation (functional). Note: The application of the functions exchange, fst and expcode satisfy their preconditions length(rl) > 1 or length(rl) > 0, resp. Ina Schaefer Selected Aspects of Compilers 118 Example: Sethi-Ullman Algorithm (6) FCT expcode( Exp@ E, RegList RL, AdrList AL ) CodeList: // pre: length(rl)>0 IF Var@<ID> E: [ fst(rl) := M[adr(ID)] ] BinExp@< L,OP,Var@<ID> > E: expcode(l,rl,al) ++ [ fst(rl) := fst(rl) OP M[adr(ID)] ] BinExp@< L,OP,R > E: LET vr == length( RL ) : IF regbed(l) < vr : expcode(r,exchange(rl),al) ++ expcode(l,rst(exchange(rl)),al) ++ [ fst(rl):= fst(rl) OP fst(rst(rl))] regbed(l)>=vr AND regbed(r)<vr : expcode(l,rl,al) ++ expcode(r,rst(rl),al) ++ [ fst(rl):= fst(rl) OP fst(rst(rl))] regbed(l)>=vr AND regbed(r)>=vr : expcode(r,rl,al) ++ [ M[ fst(al) ] := fst(rl) ] ++ expcode(l,rl,rst(al)) ++ [ fst(rl):= fst(rl) OP M[fst(AL)] ] ELSE nil ELSE [] Ina Schaefer Selected Aspects of Compilers 119

11 by Graph Coloring by Graph Coloring Register allocation by graph coloring is a procedure (with many variants) for allocation of registers beyond expressions and basic blocks. for 3AC Input: 3AC in SSA with temporary variables Output: Structurally the same SSA with registers instead of temporary variables additional instructions for storing intermediate results on the stack, if applicable Ina Schaefer Selected Aspects of Compilers 120 by Graph Coloring by Graph Coloring (2) Remarks: The SSA representation is not necessary, but simplifies the formulation of the algorithm (e.g.,wilhelm/maurer in Sect do not use SSA) It is no restriction that only temporary variables are implemented by registers. We assume that program variables are assigned to temporary variables as well, if appropriate. Ina Schaefer Selected Aspects of Compilers 121

12 Life Range and Interference Graph by Graph Coloring Definition (Life Range) The life range of a temporary variable is the set of program positions at which it is live. Definition (Interference) Two temporary variables interfere if their life ranges have a non-empty intersection Definition (Interference Graph) Let P be a program part in 3AC/SSA. The interference graph of P is an undirected graph G =(N, E), where N is the set of temporary variables E is an edge (n 1, n 2 ) iff n 1 and n 2 interfere. Ina Schaefer Selected Aspects of Compilers 122 by Graph Coloring by Graph Coloring Goal: Reduce number of temporary variables with the available registers. Idea: Translate the problem to graph coloring (NP-complete). Color the interference graph, such that neighboring nodes have differing colors. no more colors are used than available registers. Ina Schaefer Selected Aspects of Compilers 123

13 by Graph Coloring by Graph Coloring (2) General Procedure: For coloring the graph, we have two cases: If a coloring is found, terminate. If nodes could not be colored, choose a non-colored node k modify the 3AC program such that the value of k is stored temporarily and is first loaded when it is applied try to find a new coloring Termination: The procedure terminates, because by temporarily storing the life ranges and the interferences are reduced. In practice, two or three iterations are sufficient. Ina Schaefer Selected Aspects of Compilers 124 by Graph Coloring by Graph Coloring (3) Coloring Procedure: Let rd be the number of available registers, i.e., for coloring, maximally rn colors may be used. The coloring procedure consists of the steps: (a) Simplify by Marking (b) Coloring Ina Schaefer Selected Aspects of Compilers 125

14 Simplify by Marking by Graph Coloring Remove iteratively nodes with less than rn neighbors from the graph and put them on the stack. Case 1: The current simplification steps leads to an empty graph. Continue with coloring. Case 2: The graph contains only nodes with rn and more than rn neighbors. Choose a suitable node as candidate for storing it temporarily, mark it, put it on the stack and continue simplification. Ina Schaefer Selected Aspects of Compilers 126 Coloring by Graph Coloring The nodes are pushed from the stack in their order and, if possible, colored and put back into the graph. Let k be the node taken from the stack. Case1: k is not marked. Thus, it has less than rn neighbors. Then, k can be colored with a new color. Case2: k is marked. a) the rn or more neighbors have less than rn-1 different colors. Then, color k appropriately. b) there are rn or more colors in the neighborhood. Leave k uncolored. Ina Schaefer Selected Aspects of Compilers 127

15 Example - Graph Coloring by Graph Coloring For simplicity, we only consider one basic block. In the beginning, t0 and t2 are live t1 := a + t0 t3 := t2 1 t4 := t1 * t3 t5 := b + t0 t6 := c + t0 t7 := d + t4 t8 := t5 + 8 t9 := t8 t2 := t6 + 4 t0 := t7 In the end, t0, t2, t9 are live. Ina Schaefer Selected Aspects of Compilers 128 Example - Graph Coloring (2) Interference graph: by Graph Coloring Assumption: 4 available registers Simplification: Remove (in order) t1, t3, t2, t9, t0, t5, t4, t7, t8, t6 Ina Schaefer Selected Aspects of Compilers 129

16 Example - Graph Coloring (3) Possible Coloring: by Graph Coloring t4 t5 t0 t3 t2 t7 t8 t6 t1 t9 Ina Schaefer Selected Aspects of Compilers 130 Example - Graph Coloring (4) by Graph Coloring Remarks: There are several extensions of the procedure: Elimination of move instructions Specific heuristics for simplification (What is a suitable node?) Consider pre-colored nodes Recommended Reading: Appel, Sec Ina Schaefer Selected Aspects of Compilers 131

17 Further Aspects of Further Aspects of The introduced algorithms consider subproblems. In practice, there are further aspects, that have to be dealt with for register allocation: Interaction with other compiler phases (in particular optimization and code generation) Relation between temporaries and registers Source/Intermediate/Target Language Number of applications (Is a variable inside an inner loop?) Ina Schaefer Selected Aspects of Compilers 132 Further Aspects of Further Aspects of (2) Possible global procedure Allocate registers for standard tasks (registers for stack and argument pointers, base registers) Decide which variables and parameters should be stored in registers Evaluate application frequency of temporaries (Occurrences in inner loops, distribution of accesses over life range) Use evaluation together with heuristics of register allocation algorithm If applicable, optimize again Ina Schaefer Selected Aspects of Compilers 133

18 Code Generation Code Generation Code generation can be split into four independent machine-dependent tasks: Memory allocation Instruction selection and addressing Instruction scheduling Code optimization Ina Schaefer Selected Aspects of Compilers 134 Memory Allocation Code Generation Modern machines have the following memory hierarchy: Registers Primary Cache (Instruction Cache, Data Cache) Secondary Cache Main Memory (Page/Segment Addressing) Different from registers, the cache is controlled by the hardware. Efficient usage of the cache means in particular to align data objects and instructions to borders of cache blocks (cf. Appel, Chap. 21). The same holds for main memory. Ina Schaefer Selected Aspects of Compilers 135

19 Instruction Selection Code Generation Instruction selection aims at the best possible translation of expressions and basic blocks using the instruction set of the machine, for instance, using complex addressing modes considering the sizes of constants or the locality of jumps Instruction selection is often formulated as a tree pattern matching problem with costs. (cf. Wilhelm/Maurer, Chap.11) Ina Schaefer Selected Aspects of Compilers 136 Instruction Scheduling Code Generation Modern machines allow processor-local parallel processing (pipeline, super-scalar, VLIW). In order to use this parallel processing, code has to comply toadditional requirements that have to be considered for code generation. (see Appel, Chap. 20; Wilhelm/Maurer, Sect. 12.6) Ina Schaefer Selected Aspects of Compilers 137

20 Code Optimization Code Generation Optimizations of the assembler or machine code may allow an additional increase in program efficiency. (see Wilhelm/Maurer, Sect. 6.9) Ina Schaefer Selected Aspects of Compilers 138