K9XXG08XXM INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE.

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1 K9XXG08XXM INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.. For updates or additional information about Samsung products, contact your nearest Samsung office. 2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where Product failure could result in loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply. * Samsung Electronics reserves the right to change products or specification without notice.

2 Document Title 2G x 8 Bit / 4G x 8 Bit / 8G x 8 Bit NAND Flash Memory Revision History Revision No History Draft Date Remark 0.0. Initial issue Dec, 26th 2006 Advance 0.. Add random data output after Read for copy 2. Add read for copy-back with data output timing guide 3. Modify 2-plane copy-back program operation 4. Modify 2KB program operation timing guide Feb. 2nd 2007 Preliminary.0. Interleave two plane copy-back program timing is added. 2. QDP LGA package is added. 3. tcsd is changed. (0ns -> 0ns) Mar. 3st 2007 Final The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have any questions, please contact the SAMSUNG branch office near your office. 2

3 2G x 8 Bit / 4G x 8 Bit / 8G x 8 Bit NAND Flash Memory PRODUCT LIST Part Number Vcc Range Organization PKG Type K9KAG08U0M-P K9WBG08UM-P K9WBG08UM-I K9NCG08U5M-P 2.7V ~ 3.6V X8 TSOP 52TLGA TSOP-DSP FEATURES Voltage Supply - 3.3V Device(K9XXG08UXM) : 2.7V ~ 3.6V Organization - Memory Cell Array : (2G + 64M) x 8bit - Data Register : (4K + 28) x 8bit Automatic Program and Erase - Page Program : (4K + 28)Byte - Block Erase : (256K + 8K)Byte Page Read Operation - Page Size : (4K + 28)Byte - Random Read : 25µs(Max.) - Serial Access : 25ns(Min.) * K9NCG08U5M : 50ns(Min.) Fast Write Cycle Time - Page Program time : 200µs(Typ.) - Block Erase Time :.5ms(Typ.) Command/Address/Data Multiplexed I/O Port Hardware Data Protection - Program/Erase Lockout During Power Transitions Reliable CMOS Floating-Gate Technology -Endurance : 00K Program/Erase Cycles(with bit/52byte ECC) - Data Retention : 0 Years Command Driven Operation Intelligent Copy-Back with internal bit/528byte EDC Unique ID for Copyright Protection Package : - K9KAG08U0M-PCB0/PIB0 : Pb-FREE PACKAGE 48 - Pin TSOP (2 x 20 / 0.5 mm pitch) - K9WBG08UM-PCB0/PIB0 : Pb-FREE PACKAGE 48 - Pin TSOP (2 x 20 / 0.5 mm pitch) - K9WBG08UM-ICB0/IIB Pin TLGA (2 x 7 /.0 mm pitch) - K9MCG08U5M-PCB0/PIB0 : Pb-FREE PACKAGE 48 - Pin TSOP (2 x 20 / 0.5 mm pitch) GENERAL DESCRIPTION Offered in 2Gx8bit, the K9KAG08U0M is a 6G-bit NAND Flash Memory with spare 52M-bit. The device is offered in 3.3V vcc. Its NAND cell provides the most cost-effective solution for the solid state application market. A program operation can be performed in typical 200µs on the (4K+28)Byte page and an erase operation can be performed in typical.5ms on a (256K+8K)Byte block. Data in the data register can be read out at 25ns(K9NCG08U5M: 50ns) cycle time per Byte. The I/O pins serve as the ports for address and data input/output as well as command input. The on-chip write controller automates all program and erase functions including pulse repetition, where required, and internal verification and margining of data. Even the write-intensive systems can take advantage of the K9KAG08U0M s extended reliability of 00K program/erase cycles by providing ECC(Error Correcting Code) with real time mapping-out algorithm. The K9KAG08U0M is an optimum solution for large nonvolatile storage applications such as solid state file storage and other portable applications requiring non-volatility. An ultra high density solution having two 6Gb stacked with two chip selects is also available in standard 32Gb TSOPI package and another ultra high density solution having two 32Gb TSOPI package stacked with four chip selects is also available in 64Gb TSOPI- DSP. 3

4 PIN CONFIGURATION (TSOP) K9KAG08U0M-PCB0/PIB0 RE CE Vcc Vss CLE ALE WE WP pin TSOP Standard Type 2mm x 20mm I/O7 I/O6 I/O5 I/O4 Vcc Vss I/O3 I/O2 I/O I/O0 PACKAGE DIMENSIONS 48-PIN LEAD FREE PLASTIC THIN SMALL OUT-LINE PACKAGE TYPE(I) 48 - TSOP - 220F Unit :mm/inch 20.00± ± # # MAX MAX ( 0.25 ) 0.00 #24 #25.00± ± MIN 0~ TYP 8.40± ± MAX 0.45~ ~0.030 ( 0.50 )

5 PIN CONFIGURATION (TSOP) K9WBG08UM-PCB0/PIB0 2 RE CE CE2 Vcc Vss CLE ALE WE WP pin TSOP Standard Type 2mm x 20mm I/O7 I/O6 I/O5 I/O4 Vcc Vss I/O3 I/O2 I/O I/O0 K9WBG08UM PACKAGE DIMENSIONS 48-PIN LEAD FREE PLASTIC THIN SMALL OUT-LINE PACKAGE TYPE(I) 48 - TSOP - 220F Unit :mm/inch 20.00± ± # # MAX MAX ( 0.25 ) 0.00 #24 #25.00± ± MIN 0~ TYP 8.40± ± MAX 0.45~ ~0.030 ( 0.50 )

6 K9WBG08UM- ICB0 / IIB0 A B C D E F G H J K L M N NC NC NC NC NC NC NC /RE 2 IO7-2 IO6-2 IO5-2 NC Vcc /RE2 Vss IO7- IO5- Vcc /CE /CE2 /WP2 IO6- IO4- IO4-2 CLE CLE2 /WE IO0- IO2- Vss IO3-2 Vss ALE2 /WP IO- IO3- Vss NC ALE /WE2 IO0-2 IO-2 IO2-2 NC NC NC NC NC NC NC PACKAGE DIMENSIONS 52-TLGA (measured in millimeters) Top View Bottom View 2.00± ± A B #A 7.00±0.0 (Datum A) A B C D (Datum B) E F G H J K L M N ±0.0 Side View 7.00± ± ± M C AB 0. M C AB.0(Max.) 0.0 C 6

7 PIN CONFIGURATION (TSOP-DSP) K9NCG08U5M-PCB0/PIB RE CE CE2 Vcc Vss CE3 CE4 CLE ALE WE WP pin TSOP Dual Stacked Package 2mm x 20mm I/O7 I/O6 I/O5 I/O4 Vcc Vss I/O3 I/O2 I/O I/O0 PACKAGE DIMENSIONS 48-PIN LEAD FREE PLASTIC THIN SMALL OUT-LINE PACKAGE TYPE(I) 48 - TSOP - 220AF Unit :mm/inch 8.80 MAX REF SEATING PLANE -A- # # MAX REF 0.3~0.23 Pin # 0.50 TYP #24 #25 (0.0) A TYP BOTH SIDES BOTTOM TSOP ONLY 2.35 MAX (0.0) A (0.249) BASIC GAGE PLANE 0.399~ ± MIN 7

8 PIN DESCRIPTION Pin Name I/O0 ~ I/O7 CLE ALE CE / CE CE2 RE WE WP / Vcc Vss Pin Function DATA INPUTS/OUTPUTS The I/O pins are used to input command, address and data, and to output data during read operations. The I/ O pins float to high-z when the chip is deselected or when the outputs are disabled. COMMAND LATCH ENABLE The CLE input controls the activating path for commands sent to the command register. When active high, commands are latched into the command register through the I/O ports on the rising edge of the WE signal. ADDRESS LATCH ENABLE The ALE input controls the activating path for address to the internal address registers. Addresses are latched on the rising edge of WE with ALE high. CHIP ENABLE The CE / CE input is the device selection control. When the device is in the Busy state, CE / CE high is ignored, and the device does not return to standby mode in program or erase operation. Regarding CE / CE control during read operation, refer to Page Read section of Device operation. CHIP ENABLE The CE2 input enables the second K9K8G08U0A READ ENABLE The RE input is the serial data-out control, and when active drives the data onto the I/O bus. Data is valid trea after the falling edge of RE which also increments the internal column address counter by one. WRITE ENABLE The WE input controls writes to the I/O port. Commands, address and data are latched on the rising edge of the WE pulse. WRITE PROTECT The WP pin provides inadvertent program/erase protection during power transitions. The internal high voltage generator is reset when the WP pin is active low. READY/BUSY OUTPUT The / output indicates the status of the device operation. When low, it indicates that a program, erase or random read operation is in process and returns to high state upon completion. It is an open drain output and does not float to high-z condition when the chip is deselected or when outputs are disabled. POWER VCC is the power supply for device. GROUND NO CONNECTION Lead is not internally connected. NOTE Connect all VCC and VSS pins of each device to common power supply outputs. Do not leave VCC or VSS disconnected. There are two CE pins (CE & CE2) in the K9WBG08UM and four CE pins (CE & CE2 & CE3 & CE4) in the K9NCG08U5M. There are two pins ( & 2) in the K9WBG08UMK9WBG08UMK9NCG08U5M and four pins ( & 2 & R/ B3 & 4) in the K9NCG08U5M. 8

9 Figure. K9KAG08U0M Functional Block Diagram VCC VSS A3 - A3 X-Buffers Latches & Decoders 6,384M + 52M Bit NAND Flash ARRAY A0 - A2 Y-Buffers Latches & Decoders (4, )Byte x 524,288 Data Register & S/A Y-Gating Command Command Register I/O Buffers & Latches VCC VSS CE RE WE Control Logic & High Voltage Generator Global Buffers Output Driver I/0 0 I/0 7 CLE ALE WP Figure 2. K9KAG08U0M Array Organization Block = 64 Pages (256K + 8K) Byte 52K Pages (=8,92 Blocks) Page = (4K + 28)Bytes Block = (4K + 28)B x 64 Pages = (256K + 8K) Bytes Device = (4K+28)B x 64Pages x 8,92 Blocks = 6,896 Mbits 8 bit 4K Bytes 28 Bytes Page Register 4K Bytes 28 Bytes I/O 0 ~ I/O 7 I/O 0 I/O I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 st Cycle A0 A A2 A3 A4 A5 A6 A7 2nd Cycle A8 A9 A0 A A2 *L *L *L 3rd Cycle A3 A4 A5 A6 A7 A8 A9 A20 4th Cycle A2 A22 A23 A24 A25 A26 A27 A28 5th Cycle A29 A30 A3 *L *L *L *L *L Column Address Column Address Row Address Row Address Row Address NOTE : Column Address : Starting Address of the Register. * L must be set to "Low". * The device ignores any additional input of address cycles than required. 9

10 Product Introduction The K9KAG08U0M is a 6,896Mbit(7,76,740,096 bit) memory organized as 524,288 rows(pages) by 4,224x8 columns. Spare 28x8 columns are located from column address of 4,096~4,223. A 4,224-byte data register is connected to memory cell arrays accommodating data transfer between the I/O buffers and memory during page read and page program operations. The memory array is made up of 32 cells that are serially connected to form a NAND structure. Each of the 32 cells resides in a different page. A block consists of two NAND structured strings. A NAND structure consists of 32 cells. Total 2,62,688 NAND cells reside in a block. The program and read operations are executed on a page basis, while the erase operation is executed on a block basis. The memory array consists of 8,92 separately erasable 256K-byte blocks. It indicates that the bit by bit erase operation is prohibited on the K9KAG08U0M. The K9KAG08U0M has addresses multiplexed into 8 I/Os. This scheme dramatically reduces pin counts and allows system upgrades to future densities by maintaining consistency in system board design. Command, address and data are all written through I/O's by bringing WE to low while CE is low. Those are latched on the rising edge of WE. Command Latch Enable(CLE) and Address Latch Enable(ALE) are used to multiplex command and address respectively, via the I/O pins. Some commands require one bus cycle. For example, Reset Command, Status Read Command, etc require just one cycle bus. Some other commands, like page read and block erase and page program, require two cycles: one cycle for setup and the other cycle for execution. The 2,2M byte physical space requires 32 addresses, thereby requiring five cycles for addressing : 2 cycles of column address, 3 cycles of row address, in that order. Page Read and Page Program need the same five address cycles following the required command input. In Block Erase operation, however, only the three row address cycles are used. Device operations are selected by writing specific commands into the command register. Table defines the specific commands of the K9KAG08U0M. In addition to the enhanced architecture and interface, the device incorporates copy-back program feature from one page to another page without need for transporting the data to and from the external buffer memory. Since the time-consuming serial access and data-input cycles are removed, system performance for solid-state disk application is significantly increased. 0

11 Table. Command Sets Function st Cycle 2nd Cycle Acceptable Command during Busy Read 00h 30h Read for Copy Back 00h 35h Read ID 90h - Two-Plane Page Read 60h----60h 30h Two-Plane Read for Copy-Back 60h----60h 35h Reset FFh - O Page Program 80h 0h Page Program with 2KB Data 80h----h 80h----0h Two-Plane Page Program 80h---h 8h---0h Copy-Back Program 85h 0h Copy-Back Program with 2KB Data 85h----h 85h----0h Two-Plane Copy-Back Program (2) 85h---h 8h---0h Block Erase 60h D0h Two-Plane Block Erase 60h---60h D0h Random Data Input () 85h - Random Data Output () 05h E0h Two Plane Random Data Output (), (5) 00h----05h E0h Read Status 70h O Read EDC Status (3) 7Bh O Chip Status (4) Fh O Chip2 Status (4) F2h O NOTE :. Random Data Input/Output can be executed in a page. 2. Any command between h and 80h/8h/85h is prohibited except 70h/F/F2 and FFh. 3. Read EDC Status is only available on Copy Back operation. 4. Interleave-operation between two chips is allowed. It s prohibited to use Fh and F2h commands for other operations except interleave-operation. 5. Two-Plane Random Data Output msut be used after Two-Plane Read operation Caution : Any undefined command inputs are prohibited except for above command set of Table.

12 Memory Map K9KAG08U0M is arranged in four 4Gb memory planes. Each plane contains 2,048 blocks and 4,224 byte page registers. This allows it to perform simultaneous page program and block erase by selecting one page or block from each plane. The block address map is configured so that two-plane program/erase/read operations can be executed by dividing the memory array into plane 0~ or plane 2~3 separately. For example, two-plane program/erase/read operation into plane 0 and plane 2 is prohibited. That is to say, two-plane program/erase/ read operation into plane 0 and plane or into plane 2 and plane 3 is allowed Plane 0 Plane Plane 2 Plane 3 (2048 Block) (2048 Block) (2048 Block) (2048 Block) Block 0 Block Block 4096 Block 4097 Page 0 Page Page 0 Page Page 0 Page Page 0 Page Page 62 Page 63 Page 62 Page 63 Page 62 Page 63 Page 62 Page 63 Block 2 Block 3 Block 4098 Block 4099 Page 0 Page Page 0 Page Page 0 Page Page 0 Page Page 62 Page 63 Page 62 Page 63 Page 62 Page 63 Page 62 Page 63 Block 4092 Block 4093 Block 888 Block 889 Page 0 Page Page 0 Page Page 0 Page Page 0 Page Page 62 Page 63 Page 62 Page 63 Page 62 Page 63 Page 62 Page 63 Block 4094 Block 4095 Block 890 Block 89 Page 0 Page Page 0 Page Page 0 Page Page 0 Page Page 62 Page 63 Page 62 Page 63 Page 62 Page 63 Page 62 Page byte Page Registers 4224byte Page Registers 4224byte Page Registers 4224byte Page Registers 2

13 ABSOLUTE MAXIMUM RATINGS Parameter Symbol Rating Unit Voltage on any pin relative to VSS Temperature Under Bias VCC -0.6 to VIN -0.6 to VI/O -0.6 to Vcc (< 4.6V) K9XXG08UXM-XCB0 TBIAS -0 to +25 K9XXG08UXM-XIB0-40 to +25 Storage Temperature K9XXG08UXM-XCB0 TSTG -65 to +50 C K9XXG08UXM-XIB0 Short Circuit Current IOS 5 ma V C NOTE :. Minimum DC voltage is -0.6V on input/output pins. During transitions, this level may undershoot to -2.0V for periods <30ns. Maximum DC voltage on input/output pins is VCC+0.3V which, during transitions, may overshoot to VCC+2.0V for periods <20ns. 2. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect reliability. RECOMMENDED OPERATING CONDITIONS (Voltage reference to GND, K9XXG08UXM-XCB0 :TA=0 to 70 C, K9XXG08UXM-XIB0:TA=-40 to 85 C) Parameter Symbol K9XXG08UXM(3.3V) Unit Min Typ. Max Supply Voltage VCC V Supply Voltage VSS V DC AND OPERATING CHARACTERISTICS(Recommended operating conditions otherwise noted.) Operating Current Parameter Symbol Test Conditions Page Read with Serial Access ICC trc=25ns, (K9NCG08U5M: trc=50ns) CE=VIL, IOUT=0mA K9XXG08UXM 3.3V Min Typ Max Program ICC Erase ICC3 - Stand-by Current(TTL) ISB CE=VIH, WP=0V/VCC - - Stand-by Current(CMOS) ISB2 CE=VCC-0.2, WP=0V/VCC Input Leakage Current ILI VIN=0 to Vcc(max) - - ±20 Output Leakage Current ILO VOUT=0 to Vcc(max) - - ±20 Input High Voltage VIH () - 0.8x Vcc - Vcc +0.3 Input Low Voltage, All inputs VIL () x Vcc Output High Voltage Level VOH IOH=-400µA V Output Low Voltage Level VOL IOL=2.mA Output Low Current() IOL() VOL=0.4V ma Unit ma µa NOTE :. V IL can undershoot to -0.4V and V IH can overshoot to V CC +0.4V for durations of 20 ns or less. 2. Typical value is measured at V CC =3.3V, TA=25 C. Not 00% tested. 3. The typical value of the K9WBG08UM s ISB2 is 40µA and the maximum value is 200µA. 4. The typical value of the K9NCG08U5M s ISB2 is 80µA and the maximum value is 400µA. 5. The maximum value of K9WBG08UM-P s ILI and ILO is ±40µA, the maximum value of K9WAG08UM-I s ILI and ILO is ±20µA. 6. The maximum value of K9NCG08U5M s ILI and ILO is ±80µA. 3

14 VALID BLOCK Parameter Symbol Min Typ. Max Unit K9KAG08U0M NVB 8,032-8,92 Blocks K9WBG08UM NVB 6,064* - 6,384* Blocks K9NCG08U5M NVB 32,28* - 32,768* Blocks NOTE :. The device may include initial invalid blocks when first shipped. Additional invalid blocks may develop while being used. The number of valid blocks is presented with both cases of invalid blocks considered. Invalid blocks are defined as blocks that contain one or more bad bits. Do not erase or program factory-marked bad blocks. Refer to the attached technical notes for appropriate management of invalid blocks. 2. The st block, which is placed on 00h block address, is guaranteed to be a valid block up to K program/erase cycles with bit/52byte ECC. 3. The number of valid blocks is on the basis of single plane operations, and this may be decreased with two plane operations. * : Each K9KAG08U0M chip in the K9WBG08UM and K9NCG08U5M has Maximum 60 invalid blocks. AC TEST CONDITION (K9XXG08XXM-XCB0 :TA=0 to 70 C,K9XXG08XXM-XIB0:TA=-40 to 85 C,K9XXG08UXM: Vcc=2.7V ~ 3.3V, unless otherwise noted) Parameter Input Pulse Levels Input Rise and Fall Times Input and Output Timing Levels Output Load K9XXG08UXM 0V to Vcc 5ns Vcc/2 TTL GATE and CL=50pF (K9KAG08U0M-P, K9WBG08UM-I) TTL GATE and CL=30pF (K9WBG08UM-P, K9NCG08U5M-P) CAPACITANCE(TA=25 C, VCC=3.3V, f=.0mhz) Item Symbol Test Max Min Condition K9KAG08U0M K9WBG08UM K9NCG08U5M Unit Input/Output Capaci- CI/O VIL=0V pf Input Capacitance CIN VIN=0V pf NOTE : Capacitance is periodically sampled and not 00% tested. K9WBG08UM-IXB0 s capacitance(i/o, Input) is 0pF. MODE SELECTION CLE ALE CE WE RE WP Mode H L L H X Read Command Input L H L H X Mode Address Input(5clock) H L L H H Write Command Input L H L H H Mode Address Input(5clock) L L L H H Data Input L L L H X Data Output X X X X H X During Read(Busy) X X X X X H During Program(Busy) X X X X X H During Erase(Busy) X X () X X X L Write Protect X X H X X 0V/VCC (2) Stand-by NOTE :. X can be VIL or VIH. 2. WP should be biased to CMOS high or CMOS low for standby. 4

15 Program / Erase Characteristics Parameter Symbol Min Typ Max Unit Program Time tprog µs Dummy Busy Time for Two-Plane Page Program tdbsy µs Number of Partial Program Cycles Nop cycles Block Erase Time tbers ms NOTE :. Typical value is measured at Vcc=3.3V, TA=25 C. Not 00% tested. 2. Typical program time is defined as the time within which more than 50% of the whole pages are programmed at 3.3V Vcc and 25 C temperature. AC Timing Characteristics for Command / Address / Data Input Parameter Symbol K9NCG08U5M NOTES :. The transition of the corresponding control pins must occur only once while WE is held low 2. tadl is the time from the WE rising edge of final address cycle to the WE rising edge of first data cycle Min K9KAG08U0M K9WBG08UM K9NCG08U5M Max K9KAG08U0M K9WBG08UM CLE Setup Time tcls () ns CLE Hold Time tclh ns CE Setup Time tcs () ns CE Hold Time tch ns WE Pulse Width twp ns ALE Setup Time tals () ns ALE Hold Time talh ns Data Setup Time tds () ns Data Hold Time tdh ns Write Cycle Time twc ns WE High Hold Time twh ns Address to Data tadl (2) Loading Time ns Unit 5

16 AC Characteristics for Operation Parameter Symbol K9NCG08U5M Min K9KAG08U0M K9WBG08UM K9NCG08U5M Max K9KAG08U0M K9WBG08UM Data Transfer from Cell to Register tr µs ALE to RE Delay tar ns CLE to RE Delay tclr ns Ready to RE Low trr ns RE Pulse Width trp ns WE High to Busy twb ns Read Cycle Time trc ns RE Access Time trea ns CE Access Time tcea ns RE High to Output Hi-Z trhz ns CE High to Output Hi-Z tchz ns CE High to ALE or CLE Don t Care tcsd RE High to Output hold trhoh ns RE Low to Output hold trloh ns CE High to Output hold tcoh ns RE High Hold Time treh ns Output Hi-Z to RE Low tir ns RE High to WE Low trhw ns WE High to RE Low twhr ns Device Resetting Time(Read/ Program/Erase) trst - - 5/0/500 () 5/0/500 () µs WP High to WE Low tww ns Unit NOTE:. If reset command(ffh) is written at Ready state, the device goes into Busy for maximum 5µs. 6

17 NAND Flash Technical Notes Initial Invalid Block(s) Initial invalid blocks are defined as blocks that contain one or more initial invalid bits whose reliability is not guaranteed by Samsung. The information regarding the initial invalid block(s) is called the initial invalid block information. Devices with initial invalid block(s) have the same quality level as devices with all valid blocks and have the same AC and DC characteristics. An initial invalid block(s) does not affect the performance of valid block(s) because it is isolated from the bit line and the common source line by a select transistor. The system design must be able to mask out the initial invalid block(s) via address mapping. The st block, which is placed on 00h block address, is guaranteed to be a valid block up to K program/erase cycles with bit/52byte ECC. Identifying Initial Invalid Block(s) All device locations are erased(ffh) except locations where the initial invalid block(s) information is written prior to shipping. The initial invalid block(s) status is defined by the st byte in the spare area. Samsung makes sure that either the st or 2nd page of every initial invalid block has non-ffh data at the column address of Since the initial invalid block information is also erasable in most cases, it is impossible to recover the information once it has been erased. Therefore, the system must be able to recognize the initial invalid block(s) based on the original initial invalid block information and create the initial invalid block table via the following suggested flow chart(figure 3). Any intentional erasure of the original initial invalid block information is prohibited. Start Set Block Address = 0 Increment Block Address Create (or update) Initial Invalid Block(s) Table No * Check "FFh" Yes Check "FFh" at the column address 4096 of the st and 2nd page in the block No Last Block? Yes End Figure 3. Flow chart to create initial invalid block table 7

18 NAND Flash Technical Notes (Continued) Error in write or read operation Within its life time, additional invalid blocks may develop with NAND Flash memory. Refer to the qualification report for the actual data.the following possible failure modes should be considered to implement a highly reliable system. In the case of status read failure after erase or program, block replacement should be done. Because program status fail during a page program does not affect the data of the other pages in the same block, block replacement can be executed with a page-sized buffer by finding an erased empty block and reprogramming the current target data and copying the rest of the replaced block. In case of Read, ECC must be employed. To improve the efficiency of memory space, it is recommended that the read or verification failure due to single bit error be reclaimed by ECC without any block replacement. The said additional block failure rate does not include those reclaimed blocks. Write Failure Mode Erase Failure Program Failure Detection and Countermeasure sequence Status Read after Erase --> Block Replacement Status Read after Program --> Block Replacement Read Single Bit Failure Verify ECC -> ECC Correction ECC : Error Correcting Code --> Hamming Code etc. Example) bit correction & 2bit detection Program Flow Chart Start Write 80h Write Address Write Data Write 0h Read Status Register I/O 6 =? or =? No * Program Error No Yes I/O 0 = 0? Yes Program Completed * : If program operation results in an error, map out the block including the page in error and copy the target data to another block. 8

19 NAND Flash Technical Notes (Continued) Erase Flow Chart Read Flow Chart Start Start Write 60h Write 00h Write Block Address Write Address Write D0h Write 30h Read Status Register Read Data I/O 6 =? or =? No ECC Generation * Erase Error No Yes I/O 0 = 0? Reclaim the Error No Verify ECC Yes Yes Page Read Completed Erase Completed * : If erase operation results in an error, map out the failing block and replace it with another block. Block Replacement st (n-)th nth (page) { Block A an error occurs. Buffer memory of the controller. st (n-)th nth (page) { Block B 2 * Step When an error happens in the nth page of the Block A during erase or program operation. * Step2 Copy the data in the st ~ (n-)th page to the same location of another free block. (Block B ) * Step3 Then, copy the nth page data of the Block A in the buffer memory to the nth page of the Block B. * Step4 Do not erase or program Block A by creating an invalid block table or other appropriate scheme. 9

20 NAND Flash Technical Notes (Continued) Copy-Back Operation with EDC & Sector Definition for EDC Generally, copy-back program is very powerful to move data stored in a page without utilizing any external memory. But, if the source page has one bit error due to charge loss or charge gain, then without EDC, the copy-back program operation could also accumulate bit errors. K9KAG08U0M supports copy-back with EDC to prevent cumulative bit errors. To make EDC valid, the page program operation should be performed on either whole page(4224byte) or sector(528byte). Modifying the data of a sector by Random Data Input before Copy-Back Program must be performed for the whole sector and is allowed only once per each sector. Any partial modification smaller than a sector corrupts the on-chip EDC codes. A 4,224-byte page is composed of 8 sectors of 528-byte and each 528-byte sector is composed of 52-byte main area and 6-byte spare area. Main Field (4,096 Byte) Spare Field (28 Byte) "A" area "B" area "C" area "D" area "E" area "F" area "G" area "H" area "I" "J" "K" "L" "M" "N" "O" "P" ( st sector) (2 nd sector) (3 rd sector) (4 th sector) (5 th sector) (6 th sector) (7 th sector) (8 th sector) ( st )(2 nd ) (3 rd ) (4 th ) (5 th )(6 tht ) (7 th ) (8 th ) 52 Byte 52 Byte 52 Byte 52 Byte Byte 52 Byte 52 Byte 52 Byte Byte Byte 6 Byte 6 Byte 6 Byte 6 Byte 6 Byte 6 Byte Table 2. Definition of the 528-Byte Sector Sector Main Field (Column 0~2,047) Spare Field (Column 2,048~2,) Area Name Column Address Area Name Column Address st 528-Byte Sector "A" 0 ~ 5 "I" 4,096 ~ 4, 2 nd 528-Byte Sector "B" 52 ~,023 "J" 4,2 ~ 4,27 3 rd 528-Byte Sector "C",024 ~,535 "K" 4,28 ~ 4,43 4 th 528-Byte Sector "D",536 ~ 2,047 "L" 4,4 ~ 4,59 5 th 528-Byte Sector "E" 2,048 ~ 2,559 "M" 4,60 ~ 4,75 6 th 528-Byte Sector "F" 2,560 ~ 3,07 "N" 4,76 ~ 4,9 7 th 528-Byte Sector "G" 3,072 ~ 3,583 "O" 4,92 ~ 4,207 8 th 528-Byte Sector "H" 3,584 ~ 4,095 "P" 4,208 ~ 4,223 20

21 Addressing for program operation Within a block, the pages must be programmed consecutively from the LSB (least significant bit) page of the block to MSB (most significant bit) pages of the block. Random page address programming is prohibited. In this case, the definition of LSB page is the LSB among the pages to be programmed. Therefore, LSB doesn t need to be page 0. Page 63 (64) Page 63 (64) : : Page 3 (32) Page 3 () : : Page 2 Page Page 0 (3) (2) () Page 2 Page Page 0 (3) (32) (2) Data register Data register From the LSB page to MSB page DATA IN: Data () Data (64) Ex.) Random page program (Prohibition) DATA IN: Data () Data (64) Interleave Page Program K9KAG08U0M is composed of two K9F8G08U0Ms. K9KAG08U0M provides interleaving operation between two K9F8G08U0Ms. This interleaving page program improves the system throughput almost twice compared to non-interleaving page program. At first, the host issues page program command to one of the K9F8G08U0M chips, say K9F8G08X0M(chip #). Due to this K9KAG08U0M goes into busy state. During this time, K9F8G08U0M(chip #2) is in ready state. So it can execute the page program command issued by the host. After the execution of page program by K9F8G08U0M(chip #), it can execute another page program regardless of the K9F8G08U0M(chip #2). Before that the host needs to check the status of K9F8G08U0M(chip #) by issuing Fh command. Only when the status of K9F8G08U0M(chip #) becomes ready status, host can issue another page program command. If the K9F8G08U0M(chip #) is in busy state, the host has to wait for the K9F8G08U0M(chip #) to get into ready state. Similarly, K9F8G08U0M chip(chip #2) can execute another page program after the completion of the previous program. The host can monitor the status of K9F8G08U0M(chip #2) by issuing F2h command. When the K9F8G08U0M(chip #2) shows ready state, host can issue another page program command to K9F8G08U0M(chip #2). This interleaving algorithm improves the system throughput almost twice. The host can issue page program command to each chip individually. This reduces the time lag for the completion of operation. NOTE: During interleave operations, 70h command is prohibited. 2

22 Interleave Page Program I/OX 80h Add & Data 0h 80h Add & Data 0h Command A3 : Low A3 : High Fh or F2h another page program on Chip # R/ B (#) internal only busy of Chip # (#2) internal only busy of Chip #2 A B C D State A : Chip # is executing a page program operation and chip #2 is in ready state. So the host can issue a page program command to chip #2. State B : Both chip # and chip #2 are executing page program operation. State C : Page program on chip # is terminated, but page program on chip #2 is still operating. And the system should issue Fh command to detect the status of chip #. If chip # is ready, status I/O6 is "" and the system can issue another page program command to chip #. State D : Chip # and Chip #2 are ready. According to the above process, the system can operate page program on chip # and chip #2 alternately. Status Operation Status Command / Data Fh F2h A Chip : Busy, Chip 2 : Ready 8xh Cxh B Chip : Busy, Chip 2 : Busy 8xh 8xh C Chip : Ready, Chip 2 : Busy Cxh 8xh D Chip : Ready, Chip 2 : Ready Cxh Cxh 22

23 Interleave Block Erase I/OX 60h Add D0h 60h Add D0h Command A3 : Low A3 : High Fh or F2h another Block Erase on Chip # R/ B (#) internal only busy of Chip # (#2) internal only busy of Chip #2 A B C D State A : Chip # is executing a block erase operation, and chip #2 is in ready state. So the host can issue a block erase command to chip #2. State B : Both chip # and chip #2 are executing block erase operation. State C : Block erase on chip # is terminated, but block erase on chip #2 is still operating. And the system should issue Fh command to detect the status of chip #. If chip # is ready, status I/O6 is "" and the system can issue another block erase command to chip #. State D : Chip # and Chip #2 are ready. According to the above process, the system can operate block erase on chip # and chip #2 alternately. Status Operation Status Command / Data Fh F2h A Chip : Busy, Chip 2 : Ready 8xh Cxh B Chip : Busy, Chip 2 : Busy 8xh 8xh C Chip : Ready, Chip 2 : Busy Cxh 8xh D Chip : Ready, Chip 2 : Ready Cxh Cxh 23

24 Interleave Two-Plane Page Program I/OX 80h Add & Data h 8h Add & Data 0h 80h Add & Data h 8h Add & Data 0h A3 : Low A3 :Low A3: High A3 :High (#) t DBSY internal only t PROG of chip # (#2) internal only t DBSY tprog of Chip #2 I/OX Command Fh or F2h* R/nB (#) internal only (#2) internal only tprog of Chip #2 A B C D State A : Chip # is executing a page program operation, and chip #2 is in ready state. So the host can issue a page program command to chip #2. State B : Both chip # and chip #2 are executing page program operation. State C : Page program on chip # is completed and chip # is ready for the next operation. Chip #2 is still executing page program operation. State D : Both chip # and chip #2 are ready. Note : *Fh command is required to check the status of chip # to issue the next page program command to chip #. F2h command is required to check the status of chip #2 to issue the next page program command to chip #2. According to the above process, the system can operate two-plane page program on chip # and chip #2 alternately. 24

25 Interleave Two-Plane Block Erase I/OX 60h Add 60h Add D0h 60h Add 60h Add D0h A3 : Low A3 :Low A3 : High A3 :High (#) internal only t BERS of chip # (#2) internal only t BERS of chip #2 I/OX Command (#) internal only Fh or F2h* (#2) internal only tbers of chip #2 C D A B State A : Chip # is executing a block erase operation, and chip #2 is in ready state. So the host can issue a block erase command to chip #2. State B : Both chip # and chip #2 are executing block erase operation. State C : Block erase on chip # is completed and chip # is ready for the next operation. Chip #2 is still executing block erase operation. State D : Both chip # and chip #2 are ready. Note : *Fh command is required to check the status of chip # to issue the next block erase command to chip #. F2h command is required to check the status of chip #2 to issue the next block erase command to chip #2. As the above process, the system can operate two-plane block erase on chip # and chip #2 alternatively. 25

26 Interleave Read to Page Program Operation I/OX 80h Add Data in 0h 00h Add 30h Data out A3 : Low A3 : High (#) internal only tprog of chip # (#2) internal only tr of chip #2 A B I/OX Command Fh or F2h* (#) internal only tprog of chip # (#2) internal only C D State A : Chip # is executing a page program operation, and chip #2 is in ready state. So the host can issue a read command to chip #2. State B : Both chip # is executing page program operation and chip #2 is executing read operation. State C : Read operation on chip #2 is completed and chip #2 is ready for the next operation. Chip # is still executing page program operation. State D : Both chip # and chip #2 are ready. Note : *Fh command is required to check the status of chip # to issue the next command to chip #. F2h command is required to check the status of chip #2 to issue the next command to chip #2. As the above process, the system can operate Interleave read to page porgram on chip # and chip #2 alternatively. 26

27 Interleave Copy-Back Program Operation I/OX 85h Add 0h 00h Add 35h Command A3 : Low A3 : High Fh or F2h* (#) internal only tprog of chip # (#2) internal only tr of chip #2 A B C I/OX 85h Add 0h 00h Add 35h Command A3 : High A3 : Low Fh or F2h* (#) internal only tr of chip # (#2) internal only tprog of chip #2 D E F G H State A : Chip # is executing a copy-back program operation, and chip #2 is in ready state. So the host can issue a read for copy-back command to chip #2. State B : Both chip # is executing copy-back program operation and chip #2 is executing read for copy-back operation. State C : Read for copy-back operation on chip #2 is completed and chip #2 is ready for the next operation. Chip # is still executing copy-back program operation. State D : Both chip # and chip #2 are ready. State E : Chip #2 is executing a copy-back program operation, and chip # is in ready state. So the host can issue a read for copy-back command to chip #. State F : Both chip #2 is executing copy-back program operation and chip # is executing read for copy-back operation. State C : Read for copy-back operation on chip # is completed and chip # is ready for the next operation. Chip #2 is still executing copy-back program operation. State D : Both chip # and chip #2 are ready. Note : *Fh command is required to check the status of chip # to issue the next command to chip #. F2h command is required to check the status of chip #2 to issue the next command to chip #2. As the above process, the system can operate Interleave copy-back program on chip # and chip #2 alternatively. 27

28 Interleave Two-Plane Copy Back Program I/OX 60h Add 60h Add 35h 00h Add 05h Add E0h Data Out 00h Add 05h Add E0h Data Out A9 : Low A3 : Low A9 : High A3 : Low A9 : Low A3 : Low A9 : High A3 : Low (#) internal only tr (#2) internal only I/OX 85h Add h 8h Add 0h 60h Add 60h Add 35h 00h Add 05h Add E0h Data Out A9 : Low A3 : Low A9 : High A3 : Low A9 : Low A3 : High A9 : High A3 : High A9 : Low A3 : High (#) internal tdbsy tprog of Chip # only (#2) internal only tr A 2 28

29 Interleave Two-Plane Copy Back Program I/OX 00h Add 05h Add E0h Data Out 85h Add h 8h Add 0h Command Fh or F2h* A9 : High A3 : High A9 : Low A3 : High A9 : High A3 : Hgih (#) internal only (#2) internal only tdbsy 2 I/OX (#) internal only tprog of Chip # (#2) internal only tprog of Chip #2 3 C D State A : Chip # is executing a page program operation, and chip #2 is in ready state. So the host can issue a page program command to chip #2. State B : Both chip # and chip #2 are executing page program operation. State C : Page program on chip # is completed and chip # is ready for the next operation. Chip #2 is still executing page program operation. State D : Both chip # and chip #2 are ready. Note : *Fh command is required to check the status of chip # to issue the next page program command to chip #. F2h command is required to check the status of chip #2 to issue the next page program command to chip #2. According to the above process, the system can operate two-plane page program on chip # and chip #2 alternately. tprog of Chip #2 B 3 29

30 System Interface Using CE don t-care. For an easier system interface, CE may be inactive during the data-loading or serial access as shown below. The internal 4,224byte data registers are utilized as separate buffers for this operation and the system design gets more flexible. In addition, for voice or audio applications which use slow cycle time on the order of µ-seconds, de-activating CE during the data-loading and serial access would provide significant savings in power consumption. Figure 4. Program Operation with CE don t-care. CLE CE WE ALE CE don t-care 80h Address(5Cycles) Data Input Data Input 0h tcs tch tcea CE CE trea WE twp RE I/O0~7 out Figure 5. Read Operation with CE don t-care. CLE CE RE ALE tr CE don t-care WE 00h Address(5Cycle) 30h Data Output(serial access) 30

31 NOTE Device I/O DATA ADDRESS Data In/Out Col. Add Col. Add2 Row Add Row Add2 Row Add3 K9KAG08U0M I/O 0 ~ I/O 7 4,224byte A0~A7 A8~A2 A3~A20 A2~A28 A29~A3 Command Latch Cycle CLE tcls tclh CE tcs tch WE twp ALE tals talh tds tdh Command Address Latch Cycle tcls CLE tcs CE twc twc twc twc WE tals twp twh talh twp tals twh talh twp tals twh talh twp tals twh talh tals talh ALE tds tdh tds tdh tds tdh tds tdh tds tdh Col. Add Col. Add2 Row Add Row Add2 Row Add3 3

32 Input Data Latch Cycle CLE tclh CE tch ALE twc WE tals twp twp twh twp tds tdh tds tdh tds tdh DIN 0 DIN DIN final * Serial Access Cycle after Read(CLE=L, WE=H, ALE=L) CE trc trea treh trea trea tchz tcoh RE trhz trhz trhoh Dout Dout Dout trr NOTES :. Transition is measured at ±200mV from steady state voltage with load. This parameter is sampled and not 00% tested. 2. trloh is valid when frequency is higher than 33MHz. trhoh starts to be valid when frequency is lower than 33MHz. 32

33 Serial Access Cycle after Read(EDO Type, CLE=L, WE=H, ALE=L) CE trp trc treh tchz tcoh RE trea tcea trea trloh Dout trhz trhoh Dout trr NOTES :. Transition is measured at ±200mV from steady state voltage with load. This parameter is sampled and not 00% tested. 2. trloh is valid when frequency is higher than 33MHz. trhoh starts to be valid when frequency is lower than 33MHz. Status Read Cycle & EDC Status Read Cycle CLE tcls tclh tclr CE tcs WE twp tch tcea tchz twhr tcoh RE tdh tds 70h/7Bh F/F2 tir trea trhz trhoh Status Output 33

34 Read Operation tclr CLE CE twc WE twb tcsd tar ALE tr trc trhz RE trr 00h Col. Add Col. Add2 Row Add Row Add2 Row Add3 30h Dout N Dout N+ Dout M Column Address Row Address Busy Read Operation(Intercepted by CE) tclr CLE CE tcsd WE twb tchz tar tcoh ALE tr trc RE trr 00h Col. Add Col. Add2 Row Add Row Add2 Row Add3 30h Dout N Dout N+ Dout N+2 Column Address Row Address Busy 34

35 twb K9WBG08UM Random Data Output In a Page CLE CE WE trhw tar ALE trc tr RE trr 00h 30h/35h Dout N Dout N+ 05h Col. Add Col. Add2 Row Add Row Add2 Row Add3 Col Add Col Add2 E0h Column Address Row Address Column Address Busy tclr twhr trea Dout M Dout M+ 35

36 Page Program Operation CLE CE twc twc twc WE ALE tadl twb tprog twhr RE Din Din 80h Co.l Add Col. Add2 Row Add Row Add2 Row Add3 N 0h 70h I/O0 M SerialData Input Command Column Address Row Address up to m Byte Program Read Status Serial Input Command Command I/O0=0 Successful Program I/O0= Error in Program NOTES : tadl is the time from the WE rising edge of final address cycle to the WE rising edge of first data cycle. 36

37 Page Program Operation with Random Data Input CLE CE WE ALE twc twc tadl twc RE Din Din Din Din 80h Col. Add Col. Add2 Row Add Row Add2 Row Add3 N 0h 70h I/O0 M 85h Col. Add Col. Add2 J K Serial Data Input Command Column Address Row Address Serial Input Random Data Program Column Address Read Status Serial Input Input Command Command Command tadl twb tprog twhr I/O0=0 Successful Program I/O0= Error in Program NOTES :. tadl is the time from the WE rising edge of final address cycle to the WE rising edge of first data cycle. 2. For EDC operation, only one time random data input is possible at the same address. 37

38 Copy-Back Program Operation With Random Data Input CLE CE twc WE ALE twb tprog twb twhr tr RE tadl 00h Col Add Col Add2 Row Add Row Add2 Row Add3 35h 85h Col Add Col Add2 Row Add Row Add2 Row Add3 Data Data N 0h 70h/7Bh Column Address Row Address Column Address Row Address Read EDC Status or Read Status Command Busy Copy-Back Data Input Command Busy I/O0=0 Successful Program I/O0= Error in Program I/O ~ I/O2 : EDC Status (7Bh only) NOTES :. tadl is the time from the WE rising edge of final address cycle to the WE rising edge of first data cycle. 2. For EDC operation, only one time random data input is possible at the same address. 38

39 Block Erase Operation CLE CE twc WE ALE twb tbers twhr RE 60h Row Add Row Add2 Row Add3 D0h 70h I/O 0 Row Address Auto Block Erase Setup Command Erase Command Busy Read Status Command I/O0=0 Successful Erase I/O0= Error in Erase 39

40 Two-Plane Page Read Operation with Two-Plane Random Data Out CLE CE twc twc WE twb ALE tr RE 60h Row Address A 3 ~A 20 A2~A28 A29~A3 60h Row Address A 3 ~A 20 A2~A28 A 29 ~A 3 30h A3 ~ A8 : Fixed Low A9 : Fixed Low A20 ~ A30 : Fixed Low A3 : Valid A3 ~ A8 : Valid A9 : Fixed High A20 ~ A30 : Valid A3 : Must be same as previous A3 Busy CLE tclr tclr CE twc twc WE twhr twhr trea trhw trea ALE trc trc RE 00h A0~A7 A8~A2 Column Address A 3~A20 A2~A28 A29~A3 Row Address 05h A 0 ~A 7 A 8 ~A 2 Dout Column Address E0h N Dout N+ 00h A 0 ~A 7 A 8 ~A 2 Column Address A 3 ~A 20 A 2 ~A 28 A 29 ~A 3 Row Address 05h A 0 ~A 7 A 8 ~A 2 E0h Dout Column Address M A0 ~ A2 : Fixed Low A3 ~ A8 : Fixed Low A9 : Fixed Low A20 ~ A30: Fixed Low A3 : Must be same as previous A3 A0 ~ A2 : Valid A0 ~ A2 : Fixed Low A3 ~ A8 : Fixed Low A9 : Fixed High A20 ~ A30 : Fixed Low A3 : Must be same as previous A3 A0 ~ A2 : Valid Dout M+ 40

41 Two-Plane Page Program Operation CLE CE twc WE tdbsy twb twb tprog twhr ALE RE 80h Serial Data Column Address Input Command Din Din Din Din Col Add Col Add2 Row Add Row Add2 Row Add3 h 8h Col Add Col Add2 Row Add Row Add2 Row Add3 0h 70h N M Program Command (Dummy) N Program Confirm Command (True) I/O Page Row Address up to 4224 Byte Data Serial Input tdbsy : typ. 500ns max. µs M Read Status Command I/O 0 = 0 Successful Erase I/O 0 = Error in Erase Ex.) Two-Plane Page Program tdbsy tprog I/O0~7 80h Address & Data Input h 8h Address & Data Input 0h 70h Note Col Add,2 & Row Add,2, Byte Data Col Add,2 & Row Add,2, Byte Data A0 ~ A2 : Valid A3 ~ A8 : Fixed Low A9 : Fixed Low A0 ~ A : Valid A3 ~ A8 : Valid A9 : Fixed High A20 ~ A30 : Fixed Low A20 ~ A30 : Valid A3 : Must be same as previous A3 A3 : Valid Note: Any command between h and 8h is prohibited except 70h/Fh/F2h and FFh. 4

42 Two-Plane Block Erase Operation CLE CE twc twc WE twb tbers twhr ALE RE I/OX 60h Row Add Row Add2 Row D0h Add3 60h Row Add Row Add2 Row Add3 D0h 70h I/O 0 Row Address Row Address Block Erase Setup Command Block Erase Setup Command2 Erase Confirm Command Busy Read Status Command I/O 0 = 0 Successful Erase I/O 0 = Error in Erase Ex.) Address Restriction for Two-Plane Block Erase Operation tbers I/O0~7 60h Address 60h A9 Address D0h ~ A25 D0h 70h Row Add,2,3 Row Add,2,3 A3 ~ A8: Fixed Low A9 : Fixed Low A2 ~ A8 : Fixed Low A9 : Fixed High A20 ~ A30 : Valid A20 ~ A30 : Fixed Low A3 : Valid A3 : Must be same as previous A3 42

43 Read ID Operation CLE CE WE tar ALE RE trea 90h 00h ECh Device Code 3rd cyc. 4th cyc. 5th cyc. Read ID Command Address cycle Maker Code Device Code Device Device Code (2nd Cycle) 3rd Cycle 4th Cycle 5th Cycle K9KAG08U0M D5h 5h A6h 68h K9WBG08UM Same as K9KAG08U0M in it K9NCG08U5M 43

44 ID Definition Table 90 ID : Access command = 90H st Byte 2 nd Byte 3 rd Byte 4 th Byte 5 th Byte Description Maker Code Device Code Internal Chip Number, Cell Type, Number of Simultaneously Programmed Pages, Etc Page Size, Block Size,Redundant Area Size, Organization, Serial Access Minimum Plane Number, Plane Size 3rd ID Data Internal Chip Number Description I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O I/O Cell Type 2 Level Cell 4 Level Cell 8 Level Cell 6 Level Cell Number of Simultaneously Programmed Pages Interleave Program Between multiple chips Not Support Support 0 Cache Program Not Support Support 0 4th ID Data Page Size (w/o redundant area ) KB 2KB 4KB 8KB Description I/O7 I/O6 I/O5 I/ I/O3 I/O2 I/O I/O Block Size (w/o redundant area ) 64KB 28KB 256KB 52KB Redundant Area Size ( byte/52byte) Organization x8 x6 0 Serial Access Minimum 50ns/30ns 25ns Reserved Reserved

45 5th ID Data Plane Number Description I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O I/O Plane Size (w/o redundant Area) 64Mb 28Mb 256Mb 52Mb Gb 2Gb 4Gb 8Gb Reserved

46 Device Operation PAGE READ Page read is initiated by writing 00h-30h to the command register along with five address cycles. After initial power up, 00h command is latched. Therefore only five address cycles and 30h command initiates that operation after initial power up. The 4,224 bytes of data within the selected page are transferred to the data registers in less than 20µs(tR). The system controller can detect the completion of this data transfer(tr) by analyzing the output of pin. Once the data in a page is loaded into the data registers, they may be read out in 25ns(K9NC08U5M:50ns) cycle time by sequentially pulsing RE. The repetitive high to low transitions of the RE clock make the device output the data starting from the selected column address up to the last column address. The device may output random data in a page instead of the consecutive sequential data by writing random data output command. The column address of next data, which is going to be out, may be changed to the address which follows random data output command. Random data output can be operated multiple times regardless of how many times it is done in a page. Figure 6. Read Operation CLE CE WE ALE RE tr 00h Address(5Cycle) 30h Data Output(Serial Access) Col. Add.,2 & Row Add.,2,3 Data Field Spare Field 46

47 Figure 7. Random Data Output In a Page tr RE Address 00h 5Cycles 30h/35h Data Output 05h Address 2Cycles E0h Data Output Col. Add.,2 & Row Add.,2,3 Col. Add.,2 Data Field Spare Field Data Field Spare Field PAGE PROGRAM The device is programmed basically on a page basis, but it does allow multiple partial page programming of a word or consecutive bytes up to 4,224, in a single page program cycle. The number of consecutive partial page programming operation within the same page without an intervening erase operation must not exceed 4 times for a single page. The addressing should be done in sequential order in a block. A page program cycle consists of a serial data loading period in which up to 4,224bytes of data may be loaded into the data register, followed by a non-volatile programming period where the loaded data is programmed into the appropriate cell. The serial data loading period begins by inputting the Serial Data Input command(80h), followed by the five cycle address inputs and then serial data loading. The data other than those to be programmed do not need to be loaded. The device supports random data input in a page. The column address for the next data, which will be entered, may be changed to the address which follows random data input command(85h). Random data input may be operated multiple times regardless of how many times it is done in a page. Modifying the data of a sector by Random Data Input before Copy-Back Program must be performed for the whole sector and is allowed only once per each sector. Any partial modification smaller than a sector corrupts the on-chip EDC codes. The Page Program confirm command(0h) initiates the programming process. Writing 0h alone without previously entering the serial data will not initiate the programming process. The internal write state controller automatically executes the algorithms and timings necessary for program and verify, thereby freeing the system controller for other tasks. Once the program process starts, the Read Status Register command may be entered to read the status register. The system controller can detect the completion of a program cycle by monitoring the output, or the Status bit(i/o 6) of the Status Register. Only the Read Status commands and Reset command are valid while programming is in progress. When the Page Program is complete, the Write Status Bit(I/O 0) may be checked(figure 8). The internal write verify detects only errors for ""s that are not successfully programmed to "0"s. The command register remains in Read Status command mode until another valid command is written to the command register. Figure 8. Program & Read Status Operation tprog 80h "0" Address & Data Input 0h 70h I/O0 Pass Col. Add.,2 & Row Add.,2,3 "" Data Fail 47