CMOS SRAM. K6T4008C1B Family. Document Title. Revision History. 512Kx8 bit Low Power CMOS Static RAM. Revision No. History. Remark. Draft Date 0.

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1 Document Title 512Kx8 bit Low Power CMOS Static RAM Revision History Revision No. History Draft Date Remark 0.0 Initial Draft December 7, 1996 Advance 0.1 Revise - Changed Operating current by reticle revision ICC at write : 35mA 45mA ICC1 at read/write : 15/35mA 10/45mA March 6, 1997 Preliminary 1.0 Finalize - Changed Operating current ICC1 at write : 45mA 40mA ICC2; 90mA 80mA - Change test load at 55ns : 100pF 50pF October 9, 1997 Final 2.0 Revise - Change datasheet format February 17, 1998 Final 3.0 Revise - Industrial product speed bin change:70/100ns 55/70ns September 8, 1998 Final The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices. 1

2 512Kx8 bit Low Power CMOS Static RAM FEATURES Process Technology: TFT Organization: 512Kx8 Power Supply Voltage: 4.5~5.5V Low Data Retention Voltage: 2V(Min) Three state output and TTL Compatible Package Type: 32-DIP-600, 32-SOP TSOP2-400F/R GENERAL DESCRIPTION The K6T4008C1B families are fabricated by SAMSUNG s advanced CMOS process technology. The families support various operating temperature ranges and various package types for user flexibility of system design. The family also support low data retention voltage for battery back-up operation with low data retention current. PRODUCT FAMILY Product Family Operating Temperature Vcc Range Speed K6T4008C1B-L Commercial (0~70 C) K6T4008C1B-B 4.5~5.5V 55 1) /70ns K6T4008C1B-P Inderstrial (-40~85 C) K6T4008C1B-F 1. The parameter is measured with 50pF test load. Power Dissipation Standby (ISB1, Max) 100µA 20µA 100µA 50µA Operating (ICC2, Max) 80mA PKG Type 32-DIP-600, 32-SOP TSOP2-400F/R 32-SOP TSOP2-400F/R PIN DESCRIPTION FUNCTIONAL BLOCK DIAGRAM A VCC VCC 32 1 A18 Clk gen. Precharge circuit. A A15 A A16 A A17 A A14 A18 A A12 A16 A7 A6 A5 A4 A3 A2 A DIP 32-SOP 32-TSOP2 (Forward) A13 A8 A9 A11 OE A10 A13 A8 A9 A11 OE A TSOP2 (Reverse) A7 A6 A5 A4 A3 A2 A1 A14 A12 A7 A6 A5 A4 A1 A0 Row select Memory array 1024 rows columns A0 I/O1 I/O I/O8 I/O7 I/O6 I/O8 I/O7 I/O A0 I/O1 I/O2 I/O1 I/O8 Data cont I/O Circuit Column select I/O3 VSS I/O5 I/O4 I/O5 I/O I/O3 VSS Data cont Pin Name Function A9 A8 A13A17 A15 A10 A11 A3 A2 Write Enable Input OE A0~A18 I/O1~I/O8 Chip Select Input Output Enable Input Address Inputs Data Inputs/Outputs OE Control logic Vcc Power Vss Ground SAMSUNG ELECTRONI CO., LTD. reserves the right to change products and specifications without notice. 2

3 PRODUCT LIST Commercial Temperature Products(0~70 C) Industrial Temperature Products(-40~85 C) Part Name Function Part Name Function K6T4008C1B-DL55 K6T4008C1B-DB55 K6T4008C1B-DL70 K6T4008C1B-DB70 K6T4008C1B-GL55 K6T4008C1B-GB55 K6T4008C1B-GL70 K6T4008C1B-GB70 K6T4008C1B-VB55 K6T4008C1B-VB70 K6T4008C1B-MB55 K6T4008C1B-MB70 32-DIP, 55ns, L-pwr 32-DIP, 55ns, LL-pwr 32-DIP, 70ns, L-pwr 32-DIP, 70ns, LL-pwr 32-SOP, 55ns, L-pwr 32-SOP, 55ns, LL-pwr 32-SOP, 70ns, L-pwr 32-SOP, 70ns, LL-pwr 32-TSOP2-F, 55ns, LL-pwr 32-TSOP2-F, 70ns, LL-pwr 32-TSOP2-R, 55ns, LL-pwr 32-TSOP2-R, 70ns, LL-pwr K6T4008C1B-GP55 K6T4008C1B-GF55 K6T4008C1B-GP70 K6T4008C1B-GF70 K6T4008C1B-VF55 K6T4008C1B-VF70 K6T4008C1B-MF55 K6T4008C1B-MF70 32-SOP, 55ns, L-pwr 32-SOP, 55ns, LL-pwr 32-SOP, 70ns, L-pwr 32-SOP, 70ns, LL-pwr 32-TSOP2-F, 55ns, LL-pwr 32-TSOP2-F, 70ns, LL-pwr 32-TSOP2-R, 55ns, LL-pwr 32-TSOP2-R, 70ns, LL-pwr FUNCTIONAL DESCRIPTION OE I/O Pin Mode Power H X 1) X 1) High-Z Deselected Standby L H H High-Z Output disbaled Active L L H Dout Read Active L X 1) L Din Write Active 1. X means don t care.( Must be in low or high state.) ABSOLUTE IMUM RATINGS 1) Item Symbol Ratings Unit Remark Voltage on any pin relative to Vss VIN,VOUT -0.5 to 7.0 V - Voltage on Vcc supply relative to Vss VCC -0.5 to 7.0 V - Power Dissipation PD 1.0 W - Storage temperature TSTG -65 to 150 C - Operating Temperature TA 0 to 70 C K6T4008C1B-L/-B -40 to 85 C K6T4008C1B-P/-F Soldering temperature and time TSOLDER 260 C, 10sec(Lead Only) Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 3

4 RECOMMENDED DC OPERATING CONDITIONS 1) Item Symbol Min Typ Max Unit Supply voltage Vcc V Ground Vss V Input high voltage VIH Vcc+0.5 2) V Input low voltage VIL ) V Note: 1. Commercial Product: TA=0 to 70 C, otherwise specified Industrial Product: TA=-40 to 85 C, otherwise specified 2. Overshoot: VCC+3.0V in case of pulse width 30ns 3. Undershoot: -3.0V in case of pulse width 30ns 4. Overshoot and undershoot are sampled, not 100% tested. CAPACITANCE 1) (f=1mhz, TA=25 C) Item Symbol Test Condition Min Max Unit Input capacitance CIN VIN=0V - 8 pf Input/Output capacitance CIO VIO=0V - 10 pf 1. Capacitance is sampled, not 100% tested DC AND OPERATING CHARACTERISTI Item Symbol Test Conditions Min Typ Max Unit Input leakage current ILI VIN=Vss to Vcc -1-1 µa Output leakage current ILO =VIH or OE=VIH or =VIL, VIO=Vss to Vcc -1-1 µa Operating power supply ICC IIO=0mA, =VIL, VIN=VIL or VIH, Read ma Average operating current ICC1 Cycle time=1µs, 100% duty, IIO=0mA 0.2V, VIN 0.2V or VIN Vcc-0.2V Read Write ICC2 Cycle time=min, 100% duty, IIO=0mA, =VIL, VIN=VIH or VIL ma Output low voltage VOL IOL=2.1mA V Output high voltage VOH IOH=-1.0mA V Standby Current(TTL) ISB =VIH, Other inputs = VIL or VIH ma Standby Current(CMOS) ISB1 Vcc-0.2V, Other inputs=0~vcc ma K6T4008C1B-L µa K6T4008C1B-B µa K6T4008C1B-P µa K6T4008C1B-F µa 4

5 AC OPERATING CONDITIONS TEST CONDITIONS (Test Load and Test Input/Output Reference) Input pulse level: 0.8 to 2.4V Input rising and falling time: 5ns Input and output reference voltage: 1.5V Output load (See right): CL=100pF+1TTL CL=50pF+1TTL CL 1) 1. Including scope and jig capacitance AC CHARACTERISTI (Vcc=4.5~5.5V, Commercial product: TA=0 to 70 C, Industrial product: TA=-40 to 85 C) Read Write Speed Bins Parameter List Symbol 55*ns 70ns Units Min Max Min Max Read cycle time trc ns Address access time taa ns Chip select to output tco ns Output enable to valid output toe ns Chip select to low-z output tlz ns Output enable to low-z output tolz ns Chip disable to high-z output thz ns Output disable to high-z output tohz ns Output hold from address change toh ns Write cycle time twc ns Chip select to end of write tcw ns Address set-up time tas ns Address valid to end of write taw ns Write pulse width twp ns Write recovery time twr ns Write to output high-z twhz ns Data to write time overlap tdw ns Data hold from write time tdh ns End write to output low-z tow ns DATA RETENTION CHARACTERISTI Item Symbol Test Condition Min Typ Max Unit Vcc for data retention VDR Vcc-0.2V V K6T4008C1B-L Data retention current IDR Vcc=3.0V, Vcc-0.2V K6T4008C1B-B µa K6T4008C1B-P K6T4008C1B-F Data retention set-up time tsdr See data retention waveform ms Recovery time trdr

6 TIMING DIAGRAMS TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, =OE=VIL, =VIH) Address trc toh Data Out Previous Data Valid Data Valid taa TIMING WAVEFORM OF READ CYCLE(2) (=VIH) trc Address taa toh tco1 toe thz OE tolz tohz Data out High-Z tlz Data Valid NOTES (READ CYCLE) 1. thz and tohz are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. At any given temperature and voltage condition, thz(max.) is less than tlz(min.) both for a given device and from device to device interconnection. 6

7 TIMING WAVEFORM OF WRITE CYCLE(1) ( Controlled) Address twc tcw(2) twr(4) taw twp(1) tas(3) tdw tdh Data in Data Valid twhz tow Data out Data Undefined TIMING WAVEFORM OF WRITE CYCLE(2) ( Controlled) twc Address tas(3) tcw(2) twr(4) taw twp(1) tdw tdh Data in Data Valid Data out High-Z High-Z NOTES (WRITE CYCLE) 1. A write occurs during the overlap of a low and a low. A write begins at the latest transition among going Low and going low : A write end at the earliest transition among going high and going high, twp is measured from the begining of write to the end of write. 2. tcw is measured from the going low to the end of write. 3. tas is measured from the address valid to the beginning of write. 4. twr is measured from the end of write to the address change. twr applied in case a write ends as or going high. DATA RETENTION WAVE FORM controlled VCC tsdr Data Retention Mode trdr 4.5V 2.2V VDR GND VCC - 0.2V 7

8 PACKAGE DIMENSIONS Units: millimeter(inch) 32 PIN DUAL INLINE PACKAGE (600mil) #32 # ± ± #1 #16 0~ ± ± ± ± ± ± ± ± ± ± MIN 32 PIN PLASTIC SMALL OUTLINE PACKAGE (525mil) #32 #17 0~ ± ± ± ± # ± ±0.008 # ± ± ± ± MIN 8

9 PACKAGE DIMENSIONS Units: millimeter(inch) 32 PIN THIN SMALL OUTLINE PACKAGE TYPE II (400F) ~8 #32 # ~ ~ ± ± # ± ±0.004 # ( 0.50 ) ± ± ± ± MIN PIN THIN SMALL OUTLINE PACKAGE TYPE II (400R) 0~8 #1 # ~ ~ ± ± # ± ±0.004 # ± ± ± ± MIN

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