IA-32 Intel Architecture Software Developer s Manual

Transcription

1 IA-32 Intel Architecture Software Developer s Manual Volume 1: Basic Architecture NOTE: The IA-32 Intel Architecture Software Developer s Manual consists of four volumes: Basic Architecture, Order Number ; Instruction Set Reference A-M, Order Number ; Instruction Set Reference N-Z, Order Number ; and the System Programming Guide, Order Number Refer to all four volumes when evaluating your design needs. 2004

2 INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. INTEL PRODUCTS ARE NOT INTENDED FOR USE IN MEDICAL, LIFE SAVING, OR LIFE SUSTAINING APPLICATIONS. Intel may make changes to specifications and product descriptions at any time, without notice. Developers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Improper use of reserved or undefined features or instructions may cause unpredictable behavior or failure in developer's software code when running on an Intel processor. Intel reserves these features or instructions for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from their unauthorized use. The Intel IA-32 architecture processors (e.g., Pentium 4 and Pentium III processors) may contain design defects or errors known as errata. Current characterized errata are available on request. Hyper-Threading Technology requires a computer system with an Intel Pentium 4 processor supporting Hyper- Threading Technology and an HT Technology enabled chipset, BIOS and operating system. Performance will vary depending on the specific hardware and software you use. See for more information including details on which processors support HT Technology. Intel, Intel386, Intel486, Pentium, Intel Xeon, Intel NetBurst, Intel SpeedStep, MMX, Celeron, and Itanium are trademarks or registered trademarks of Intel Corporation and its subsidiaries in the United States and other countries. *Other names and brands may be claimed as the property of others. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtained from: Intel Corporation P.O. Box 5937 Denver, CO or call or visit Intel s website at COPYRIGHT INTEL CORPORATION

3 CONTENTS PAGE CHAPTER 1 ABOUT THIS MANUAL 1.1. IA-32 PROCESSORS COVERED IN THIS MANUAL OVERVIEW OF THE IA-32 INTEL ARCHITECTURE SOFTWARE DEVELOPER S MANUAL, VOLUME 1: BASIC ARCHITECTURE NOTATIONAL CONVENTIONS Bit and Byte Order Reserved Bits and Software Compatibility Instruction Operands Hexadecimal and Binary Numbers Segmented Addressing Exceptions RELATED LITERATURE CHAPTER 2 INTRODUCTION TO THE IA-32 INTEL ARCHITECTURE 2.1. BRIEF HISTORY OF THE IA-32 ARCHITECTURE bit Processors and Segmentation (1978) The Intel 286 Processor (1982) The Intel386 Processor (1985) The Intel486 Processor (1989) The Intel Pentium Processor (1993) The P6 Family of Processors ( ) The Intel Pentium 4 Processor (2000) and the Intel Pentium 4 Processor Supporting Hyper-Threading Technology (2003) The Intel Xeon Processor ( ) The Intel Pentium M Processor (2003) MORE ON MAJOR TECHNICAL ADVANCES The P6 Family Microarchitecture The Intel NetBurst Microarchitecture The Front End Pipeline Out-Of-Order Execution Core Retirement Unit SIMD INSTRUCTIONS Hyper-Threading Technology Notes on Implementation MOORE S LAW AND IA-32 PROCESSOR GENERATIONS CHAPTER 3 BASIC EXECUTION ENVIRONMENT 3.1. MODES OF OPERATION OVERVIEW OF THE BASIC EXECUTION ENVIRONMENT MEMORY ORGANIZATION Modes of Operation vs. Memory Model Bit vs. 16-Bit Address and Operand Sizes Extended Physical Addressing BASIC PROGRAM EXECUTION REGISTERS General-Purpose Registers iii

4 CONTENTS PAGE Segment Registers EFLAGS Register Status Flags DF Flag System Flags and IOPL Field INSTRUCTION POINTER OPERAND-SIZE AND ADDRESS-SIZE ATTRIBUTES OPERAND ADDRESSING Immediate Operands Register Operands Memory Operands Specifying a Segment Selector Specifying an Offset Assembler and Compiler Addressing Modes I/O Port Addressing CHAPTER 4 DATA TYPES 4.1. FUNDAMENTAL DATA TYPES Alignment of Words, Doublewords, Quadwords, and Double Quadwords NUMERIC DATA TYPES Integers Unsigned Integers Signed Integers Floating-Point Data Types POINTER DATA TYPES BIT FIELD DATA TYPE STRING DATA TYPES PACKED SIMD DATA TYPES Bit SIMD Packed Data Types Bit Packed SIMD Data Types BCD AND PACKED BCD INTEGERS REAL NUMBERS AND FLOATING-POINT FORMATS Real Number System Floating-Point Format Normalized Numbers Biased Exponent Real Number and Non-number Encodings Signed Zeros Normalized and Denormalized Finite Numbers Signed Infinities NaNs Operating on SNaNs and QNaNs Using SNaNs and QNaNs in Applications QNaN Floating-Point Indefinite Rounding Rounding Control (RC) Fields Truncation with SSE/SSE2 Conversion Instructions OVERVIEW OF FLOATING-POINT EXCEPTIONS Floating-Point Exception Conditions Invalid Operation Exception (#I) Denormal Operand Exception (#D) iv

5 CONTENTS PAGE Divide-By-Zero Exception (#Z) Numeric Overflow Exception (#O) Numeric Underflow Exception (#U) Inexact-Result (Precision) Exception (#P) Floating-Point Exception Priority Typical Actions of a Floating-Point Exception Handler CHAPTER 5 INSTRUCTION SET SUMMARY 5.1. GENERAL-PURPOSE INSTRUCTIONS Data Transfer Instructions Binary Arithmetic Instructions Decimal Arithmetic Instructions Logical Instructions Shift and Rotate Instructions Bit and Byte Instructions Control Transfer Instructions String Instructions I/O Instructions Enter and Leave Instructions Flag Control (EFLAG) Instructions Segment Register Instructions Miscellaneous Instructions X87 FPU INSTRUCTIONS x87 FPU Data Transfer Instructions x87 FPU Basic Arithmetic Instructions x87 FPU Comparison Instructions x87 FPU Transcendental Instructions x87 FPU Load Constants Instructions x87 FPU Control Instructions X87 FPU AND SIMD STATE MANAGEMENT INSTRUCTIONS MMX INSTRUCTIONS MMX Data Transfer Instructions MMX Conversion Instructions MMX Packed Arithmetic Instructions MMX Comparison Instructions MMX Logical Instructions MMX Shift and Rotate Instructions MMX State Management Instructions SSE INSTRUCTIONS SSE SIMD Single-Precision Floating-Point Instructions SSE Data Transfer Instructions SSE Packed Arithmetic Instructions SSE Comparison Instructions SSE Logical Instructions SSE Shuffle and Unpack Instructions SSE Conversion Instructions SSE MXCSR State Management Instructions SSE 64-Bit SIMD Integer Instructions SSE Cacheability Control, Prefetch, and Instruction Ordering Instructions v

6 CONTENTS PAGE 5.6. SSE2 INSTRUCTIONS SSE2 Packed and Scalar Double-Precision Floating-Point Instructions SSE2 Data Movement Instructions SSE2 Packed Arithmetic Instructions SSE2 Logical Instructions SSE2 Compare Instructions SSE2 Shuffle and Unpack Instructions SSE2 Conversion Instructions SSE2 Packed Single-Precision Floating-Point Instructions SSE2 128-Bit SIMD Integer Instructions SSE2 Cacheability Control and Ordering Instructions SSE3 INSTRUCTIONS SSE3 x87-fp Integer Conversion Instruction SSE3 Specialized 128-bit Unaligned Data Load Instruction SSE3 SIMD Floating-Point Packed ADD/SUB Instructions SSE3 SIMD Floating-Point Horizontal ADD/SUB Instructions SSE3 SIMD Floating-Point LOAD/MOVE/DUPLICATE Instructions SSE3 Agent Synchronization Instructions SYSTEM INSTRUCTIONS CHAPTER 6 PROCEDURE CALLS, INTERRUPTS, AND EXCEPTIONS 6.1. PROCEDURE CALL TYPES STACK Setting Up a Stack Stack Alignment Address-Size Attributes for Stack Accesses Procedure Linking Information Stack-Frame Base Pointer Return Instruction Pointer CALLING PROCEDURES USING CALL AND RET Near CALL and RET Operation Far CALL and RET Operation Parameter Passing Passing Parameters Through the General-Purpose Registers Passing Parameters on the Stack Passing Parameters in an Argument List Saving Procedure State Information Calls to Other Privilege Levels CALL and RET Operation Between Privilege Levels INTERRUPTS AND EXCEPTIONS Call and Return Operation for Interrupt or Exception Handling Procedures Calls to Interrupt or Exception Handler Tasks Interrupt and Exception Handling in Real-Address Mode INT n, INTO, INT 3, and BOUND Instructions Handling Floating-Point Exceptions PROCEDURE CALLS FOR BLOCK-STRUCTURED LANGUAGES ENTER Instruction LEAVE Instruction vi

7 CONTENTS PAGE CHAPTER 7 PROGRAMMING WITH THE GENERAL-PURPOSE INSTRUCTIONS 7.1. PROGRAMMING ENVIRONMENT FOR THE GENERAL-PURPOSE INSTRUCTIONS SUMMARY OF THE GENERAL-PURPOSE INSTRUCTIONS Data Transfer Instructions General Data Movement Instructions Exchange Instructions Stack Manipulation Instructions Type Conversion Instructions Binary Arithmetic Instructions Addition and Subtraction Instructions Increment and Decrement Instructions Comparison and Sign Change Instruction Multiplication and Divide Instructions Decimal Arithmetic Instructions Packed BCD Adjustment Instructions Unpacked BCD Adjustment Instructions Logical Instructions Shift and Rotate Instructions Shift Instructions Double-Shift Instructions Rotate Instructions Bit and Byte Instructions Bit Test and Modify Instructions Bit Scan Instructions Byte Set on Condition Instructions Test Instruction Control Transfer Instructions Unconditional Transfer Instructions Conditional Transfer Instructions Software Interrupt Instructions String Operations Repeating String Operations I/O Instructions Enter and Leave Instructions Flag Control (EFLAG) Instructions Carry and Direction Flag Instructions EFLAGS Transfer Instructions Interrupt Flag Instructions Segment Register Instructions Segment-Register Load and Store Instructions Far Control Transfer Instructions Software Interrupt Instructions Load Far Pointer Instructions Miscellaneous Instructions Address Computation Instruction Table Lookup Instructions Processor Identification Instruction No-Operation and Undefined Instructions vii

8 CONTENTS PAGE CHAPTER 8 PROGRAMMING WITH THE X87 FPU 8.1. X87 FPU EXECUTION ENVIRONMENT x87 FPU Data Registers Parameter Passing With the x87 FPU Register Stack x87 FPU Status Register Top of Stack (TOP) Pointer Condition Code Flags x87 FPU Floating-Point Exception Flags Stack Fault Flag Branching and Conditional Moves on Condition Codes x87 FPU Control Word x87 FPU Floating-Point Exception Mask Bits Precision Control Field Rounding Control Field Infinity Control Flag x87 FPU Tag Word x87 FPU Instruction and Data (Operand) Pointers Last Instruction Opcode Fopcode Compatibility Mode Saving the x87 FPU s State with the FSTENV/FNSTENV and FSAVE/FNSAVE Instructions Saving the x87 FPU s State with the FXSAVE Instruction X87 FPU DATA TYPES Indefinites Unsupported Double Extended-Precision Floating-Point Encodings and Pseudo-Denormals X86 FPU INSTRUCTION SET Escape (ESC) Instructions x87 FPU Instruction Operands Data Transfer Instructions Load Constant Instructions Basic Arithmetic Instructions Comparison and Classification Instructions Branching on the x87 FPU Condition Codes Trigonometric Instructions Pi Logarithmic, Exponential, and Scale Transcendental Instruction Accuracy x87 FPU Control Instructions Waiting Vs. Non-waiting Instructions Unsupported x87 FPU Instructions X87 FPU FLOATING-POINT EXCEPTION HANDLING Arithmetic vs. Non-arithmetic Instructions X87 FPU FLOATING-POINT EXCEPTION CONDITIONS Invalid Operation Exception Stack Overflow or Underflow Exception (#IS) Invalid Arithmetic Operand Exception (#IA) Denormal Operand Exception (#D) Divide-By-Zero Exception (#Z) Numeric Overflow Exception (#O) Numeric Underflow Exception (#U) viii

9 CONTENTS PAGE Inexact-Result (Precision) Exception (#P) X87 FPU EXCEPTION SYNCHRONIZATION HANDLING X87 FPU EXCEPTIONS IN SOFTWARE Native Mode MS-DOS* Compatibility Mode Handling x87 FPU Exceptions in Software CHAPTER 9 PROGRAMMING WITH THE INTEL MMX TECHNOLOGY 9.1. OVERVIEW OF MMX TECHNOLOGY THE MMX TECHNOLOGY PROGRAMMING ENVIRONMENT MMX Registers MMX Data Types Memory Data Formats Single Instruction, Multiple Data (SIMD) Execution Model SATURATION AND WRAPAROUND MODES MMX INSTRUCTIONS Data Transfer Instructions Arithmetic Instructions Comparison Instructions Conversion Instructions Unpack Instructions Logical Instructions Shift Instructions EMMS Instruction COMPATIBILITY WITH X87 FPU ARCHITECTURE MMX Instructions and the x87 FPU Tag Word WRITING APPLICATIONS WITH MMX CODE Checking for MMX Technology Support Transitions Between x87 FPU and MMX Code Using the EMMS Instruction Mixing MMX and x87 FPU Instructions Interfacing with MMX Code Using MMX Code in a Multitasking Operating System Environment Exception Handling in MMX Code Register Mapping Effect of Instruction Prefixes on MMX Instructions CHAPTER 10 PROGRAMMING WITH THE STREAMING SIMD EXTENSIONS (SSE) OVERVIEW OF SSE EXTENSIONS SSE PROGRAMMING ENVIRONMENT XMM Registers MXCSR Control and Status Register SIMD Floating-Point Mask and Flag Bits SIMD Floating-Point Rounding Control Field Flush-To-Zero Denormals Are Zeros Compatibility of the SSE Extensions with SSE2 and SSE3 Extensions, MMX Technology, and the x87 FPU Programming Environments SSE DATA TYPES SSE INSTRUCTION SET ix

10 CONTENTS PAGE SSE Packed and Scalar Floating-Point Instructions SSE Data Movement Instructions SSE Arithmetic Instructions SSE Logical Instructions SSE Comparison Instructions SSE Shuffle and Unpack Instructions SSE Conversion Instructions SSE 64-bit SIMD Integer Instructions MXCSR State Management Instructions Cacheability Control, Prefetch, and Memory Ordering Instructions Cacheability Control Instructions Caching of Temporal Vs. Non-Temporal Data PREFETCHh Instructions SFENCE Instruction FXSAVE AND FXRSTOR INSTRUCTIONS HANDLING SSE INSTRUCTION EXCEPTIONS WRITING APPLICATIONS WITH THE SSE EXTENSIONS CHAPTER 11 PROGRAMMING WITH THE STREAMING SIMD EXTENSIONS 2 (SSE2) OVERVIEW OF SSE2 EXTENSIONS SSE2 PROGRAMMING ENVIRONMENT Compatibility of SSE2 Extensions with SSE, MMX Technology, and x87 FPU Programming Environments Denormals-Are-Zeros Flag SSE2 DATA TYPES SSE2 INSTRUCTIONS Packed and Scalar Double-Precision Floating-Point Instructions Data Movement Instructions SSE2 Arithmetic Instructions SSE2 Logical Instructions SSE2 Comparison Instructions SSE2 Shuffle and Unpack Instructions SSE2 Conversion Instructions SSE2 64-Bit and 128-Bit SIMD Integer Instructions Bit SIMD Integer Instruction Extensions Cacheability Control and Memory Ordering Instructions FLUSH Cache Line Cacheability Control Instructions Memory Ordering INstructions Pause Branch Hints SSE, SSE2, AND SSE3 EXCEPTIONS SIMD Floating-Point Exceptions SIMD Floating-Point Exception Conditions Invalid Operation Exception (#I) Denormal Operand Exception (#D) Divide-By-Zero Exception (#Z) Numeric Overflow Exception (#O) Numeric Underflow Exception (#U) Inexact-Result (Precision) Exception (#P) Generating SIMD Floating-Point Exceptions x

11 CONTENTS PAGE Handling Masked Exceptions Handling Unmasked Exceptions Handling Combinations of Masked and Unmasked Exceptions Handling SIMD Floating-Point Exceptions in Software Interaction of SIMD and x87 FPU Floating-Point Exceptions WRITING APPLICATIONS WITH THE SSE AND SSE2 EXTENSIONS General Guidelines for Using the SSE and SSE2 Extensions Checking for SSE and SSE2 Support Checking for the DAZ Flag in the MXCSR Register Initialization of the SSE and SSE2 Extensions Saving and Restoring the SSE and SSE2 State Guidelines for Writing to the MXCSR Register Interaction of SSE and SSE2 Instructions with x87 FPU and MMX Instructions Compatibility of SIMD and x87 FPU Floating-Point Data Types Intermixing Packed and Scalar Floating-Point and 128-Bit SIMD Integer Instructions and Data Interfacing with SSE and SSE2 Procedures and Functions Passing Parameters in XMM Registers Saving XMM Register State on a Procedure or Function Call Caller-Save Requirement for Procedure and Function Calls Updating Existing MMX Technology Routines Using 128-Bit SIMD Integer Instructions Branching on Arithmetic Operations Cacheability Hint Instructions Effect of Instruction Prefixes on the SSE and SSE2 Instructions CHAPTER 12 PROGRAMMING WITH THE STREAMING SIMD EXTENSIONS 3 (SSE3) OVERVIEW OF SSE3 INSTRUCTIONS SSE3 PROGRAMMING ENVIRONMENT AND DATA TYPE Compatibility of SSE3 Extensions with MMX Technology, the x87 FPU Environment, SSE Extensions and SSE2 Extensions Horizontal and Asymetric Processing SSE3 INSTRUCTIONS An x87fpu Instruction for Integer Conversion A SIMD Integer Instruction for Specialized 128-bit Unaligned Data Load Three SIMD Floating-Point Instructions That Enhance LOAD/MOVE/ DUPLICATE Performance Two SIMD Floating-Point Instructions Provide Packed Addition/Subtraction Four SIMD Floating-Point Instructions Provide Horizontal Addition/Subtraction Two Thread Synchronization Instructions SSE3 EXCEPTIONS Device Not Available (DNA) Exceptions Numeric Error flag and IGNNE# Emulation WRITING APPLICATIONS WITH SSE3 EXTENSIONS General Guidelines for Using SSE3 Extensions Checking for SSE3 Support xi

12 CONTENTS PAGE Enable FTZ and DAZ for SIMD Floating-Point Computation Programming SSE3 with SSE and SSE2 extensions CHAPTER 13 INPUT/OUTPUT I/O PORT ADDRESSING I/O PORT HARDWARE I/O ADDRESS SPACE Memory-Mapped I/O I/O INSTRUCTIONS PROTECTED-MODE I/O I/O Privilege Level I/O Permission Bit Map ORDERING I/O CHAPTER 14 PROCESSOR IDENTIFICATION AND FEATURE DETERMINATION USING THE CPUID INSTRUCTION Notes on Where to Start Identification of Earlier IA-32 Processors APPENDIX A EFLAGS CROSS-REFERENCE APPENDIX B EFLAGS CONDITION CODES APPENDIX C FLOATING-POINT EXCEPTIONS SUMMARY C.1. X87 FPU INSTRUCTIONS C-2 C.2. SSE INSTRUCTIONS C-4 C.3. SSE2 INSTRUCTIONS C-6 C.4. SSE3 INSTRUCTIONS C-10 APPENDIX D GUIDELINES FOR WRITING X87 FPU EXCEPTION HANDLERS D.1. ORIGIN OF THE MS-DOS COMPATIBILITY MODE FOR HANDLING X87 FPU EXCEPTIONS D-2 D.2. IMPLEMENTATION OF THE MS-DOS COMPATIBILITY MODE IN THE INTEL486, PENTIUM, AND P6 PROCESSOR FAMILY, AND PENTIUM 4 PROCESSORS.. D-3 D.2.1. MS-DOS Compatibility Mode in the Intel486 and Pentium Processors D-3 D Basic Rules: When FERR# Is Generated D-4 D Recommended External Hardware to Support the MS-DOS Compatibility Mode D-5 D No-Wait x87 FPU Instructions Can Get x87 FPU Interrupt in Window D-7 D.2.2. MS-DOS Compatibility Mode in the P6 Family and Pentium 4 Processors D-9 D.3. RECOMMENDED PROTOCOL FOR MS-DOS* COMPATIBILITY HANDLERS.. D-10 D.3.1. Floating-Point Exceptions and Their Defaults D-11 D.3.2. Two Options for Handling Numeric Exceptions D-11 D Automatic Exception Handling: Using Masked Exceptions D-11 xii

13 CONTENTS PAGE D Software Exception Handling D-13 D.3.3. Synchronization Required for Use of x87 FPU Exception Handlers D-14 D Exception Synchronization: What, Why and When D-14 D Exception Synchronization Examples D-15 D Proper Exception Synchronization in General D-16 D.3.4. x87 FPU Exception Handling Examples D-17 D.3.5. Need for Storing State of IGNNE# Circuit If Using x87 FPU and SMM D-21 D.3.6. Considerations When x87 FPU Shared Between Tasks D-22 D Speculatively Deferring x87 FPU Saves, General Overview D-22 D Tracking x87 FPU Ownership D-23 D Interaction of x87 FPU State Saves and Floating-Point Exception Association D-24 D Interrupt Routing From the Kernel D-26 D Special Considerations for Operating Systems that Support Streaming SIMD Extensions D-27 D.4. DIFFERENCES FOR HANDLERS USING NATIVE MODE D-27 D.4.1. Origin with the Intel 286 and Intel 287, and Intel386 and Intel 387 Processors D-28 D.4.2. D.4.3. Changes with Intel486, Pentium and Pentium Pro Processors with CR0.NE= D-28 Considerations When x87 FPU Shared Between Tasks Using Native Mode D-29 APPENDIX E GUIDELINES FOR WRITING SIMD FLOATING-POINT EXCEPTION HANDLERS E.1. TWO OPTIONS FOR HANDLING FLOATING-POINT EXCEPTIONS E-1 E.2. SOFTWARE EXCEPTION HANDLING E-1 E.3. EXCEPTION SYNCHRONIZATION E-3 E.4. SIMD FLOATING-POINT EXCEPTIONS AND THE IEEE STANDARD 754 FOR BINARY FLOATING-POINT ARITHMETIC E-4 E.4.1. Floating-Point Emulation E-4 E.4.2. SSE/SSE2/SSE3 Response To Floating-Point Exceptions E-6 E Numeric Exceptions E-7 E Results of Operations with NaN Operands or a NaN Result for SSE/SSE2/SSE3 Numeric Instructions E-7 E Condition Codes, Exception Flags, and Response for Masked and Unmasked Numeric Exceptions E-12 E.4.3. SIMD Floating-Point Emulation Implementation Example E-19 xiii

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15 FIGURES PAGE Figure 1-1. Bit and Byte Order Figure 2-1. The P6 Processor Microarchitecture with Advanced Transfer Cache Enhancement Figure 2-2. The Intel NetBurst Microarchitecture Figure 2-3. SIMD Extensions, Register Layouts, and Data Types Figure 2-4. Comparison of an IA-32 Processor Supporting Hyper-Threading Technology and a Traditional Dual Processor System Figure 3-1. IA-32 Basic Execution Environment Figure 3-2. Three Memory Management Models Figure 3-3. General System and Application Programming Registers Figure 3-4. Alternate General-Purpose Register Names Figure 3-5. Use of Segment Registers for Flat Memory Model Figure 3-6. Use of Segment Registers in Segmented Memory Model Figure 3-7. EFLAGS Register Figure 3-8. Memory Operand Address Figure 3-9. Offset (or Effective Address) Computation Figure 4-1. Fundamental Data Types Figure 4-2. Bytes, Words, Doublewords, Quadwords, and Double Quadwords in Memory Figure 4-3. Numeric Data Types Figure 4-4. Pointer Data Types Figure 4-5. Bit Field Data Type Figure Bit Packed SIMD Data Types Figure Bit Packed SIMD Data Types Figure 4-8. BCD Data Types Figure 4-9. Binary Real Number System Figure Binary Floating-Point Format Figure Real Numbers and NaNs Figure 6-1. Stack Structure Figure 6-2. Stack on Near and Far Calls Figure 6-3. Protection Rings Figure 6-4. Stack Switch on a Call to a Different Privilege Level Figure 6-5. Stack Usage on Transfers to Interrupt and Exception Handling Routines Figure 6-6. Nested Procedures Figure 6-7. Stack Frame after Entering the MAIN Procedure Figure 6-8. Stack Frame after Entering Procedure A Figure 6-9. Stack Frame after Entering Procedure B Figure Stack Frame after Entering Procedure C Figure 7-1. Basic Execution Environment for General-Purpose Instructions Figure 7-2. Operation of the PUSH Instruction Figure 7-3. Operation of the PUSHA Instruction Figure 7-4. Operation of the POP Instruction Figure 7-5. Operation of the POPA Instruction Figure 7-6. Sign Extension Figure 7-7. SHL/SAL Instruction Operation Figure 7-8. SHR Instruction Operation Figure 7-9. SAR Instruction Operation Figure SHLD and SHRD Instruction Operations Figure ROL, ROR, RCL, and RCR Instruction Operations xv

16 FIGURES PAGE Figure Flags Affected by the PUSHF, POPF, PUSHFD, and POPFD Instructions Figure 8-1. x87 FPU Execution Environment Figure 8-2. x87 FPU Data Register Stack Figure 8-3. Example x87 FPU Dot Product Computation Figure 8-4. x87 FPU Status Word Figure 8-5. Moving the Condition Codes to the EFLAGS Register Figure 8-6. x87 FPU Control Word Figure 8-7. x87 FPU Tag Word Figure 8-8. Contents of x87 FPU Opcode Registers Figure 8-9. Protected Mode x87 FPU State Image in Memory, 32-Bit Format Figure Real Mode x87 FPU State Image in Memory, 32-Bit Format Figure Protected Mode x87 FPU State Image in Memory, 16-Bit Format Figure Real Mode x87 FPU State Image in Memory, 16-Bit Format Figure x87 FPU Data Type Formats Figure 9-1. MMX Technology Execution Environment Figure 9-2. MMX Register Set Figure 9-3. Data Types Introduced with the MMX Technology Figure 9-4. SIMD Execution Model Figure SSE Execution Environment Figure XMM Registers Figure MXCSR Control/Status Register Figure Bit Packed Single-Precision Floating-Point Data Type Figure Packed Single-Precision Floating-Point Operation Figure Scalar Single-Precision Floating-Point Operation Figure SHUFPS Instruction Packed Shuffle Operation Figure UNPCKHPS Instruction High Unpack and Interleave Operation Figure UNPCKLPS Instruction Low Unpack and Interleave Operation Figure Steaming SIMD Extensions 2 Execution Environment Figure Data Types Introduced with the SSE2 Extensions Figure Packed Double-Precision Floating-Point Operations Figure Scalar Double-Precision Floating-Point Operations Figure SHUFPD Instruction Packed Shuffle Operation Figure UNPCKHPD Instruction High Unpack and Interleave Operation Figure UNPCKLPD Instruction Low Unpack and Interleave Operation Figure SSE and SSE2 Conversion Instructions Figure Example Masked Response for Packed Operations Figure Asymmetric processing in ADDSUBPD Figure Horizontal data movement in ADDSUBPD Figure Memory-Mapped I/O Figure I/O Permission Bit Map Figure D-1. Recommended Circuit for MS-DOS* Compatibility x87 FPU Exception Handling D-6 Figure D-2. Behavior of Signals During x87 FPU Exception Handling D-7 Figure D-3. Timing of Receipt of External Interrupt D-8 Figure D-4. Arithmetic Example Using Infinity D-12 Figure D-5. General Program Flow for DNA Exception Handler D-25 Figure D-6. Program Flow for a Numeric Exception Dispatch Routine D-25 Figure E-1. Control Flow for Handling Unmasked Floating-Point Exceptions E-6 xvi