2 Prof, Dept of ECE, VNR Vignana Jyothi Institute of Engineering & Technology, A.P-India,

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1 ISSN Vol.02,Issue.17, November-2013, Pages: An Efficient Implementation of Floating Pont Multiplier Using Vedic Mathematics D. SRIDEVI 1, DR. L. PADMASREE 2 1 PG Scholar, Dept of ECE, VNR Vignana Jyothi Institute of Engineering &Technology, A.P-India, sridevi1708@yahoo.com. 2 Prof, Dept of ECE, VNR Vignana Jyothi Institute of Engineering & Technology, A.P-India, padmasree_l@vnrvjiet.in. Abstract: These Lab-Oriented Project and Activities have been carried out into two parts. First Half is the Floating Point Representation Using IEEE-754 Format (32 Bit Single Precision) and second Half is simulation, synthesis of Design using HDLs and Software Tools. The multiplier implementation handles the overflow and underflow cases. Rounding is not implemented to give more precision when using the multiplier in a multiply and Accumulate (MAC) unit. With latency of three clock cycles the design achieves 301 MFLOPs. Vedic Mathematics is the ancient methodology of Indian mathematics which has a unique technique of calculations based on 16 Sutras (Formulae). A high speed complex multiplier design (ASIC) using Vedic Mathematics is presented in this paper. The idea for designing the multiplier and adder/subtractor unit is adopted from ancient Indian mathematics "Vedas". On account of those formulas, the partial products and sums are generated in one step which reduces the carry propagation from LSB to MSB. The implementation of the Vedic mathematics and their application to the complex multiplier ensure substantial reduction of propagation delay in comparison with DA based architecture and parallel adder based implementation which are most commonly used architectures. As Multipliers take a long time for execution so there is a need of fast multiplier to save the execution time. This paper describes the multiplication using Ancient Indian Vedic Mathematics multiplication techniques. Vedic Mathematics is the ancient system of mathematics which has a unique technique of calculations based on 16 Sutras. Instead of writing Test- Benches & Test-Cases we used Wave-Form Analyzer which can give a better understanding of Signals & variables and also proved a good choice for simulation of design. Keywords: Floating Point, Multiplication, Vedic Mathematics, Multiplication, Nikhilam Sutra, FPGA, CAD Design Flow. I. INTRODUCTION The computation speed of the computers has increased dramatically during the last decade. This increase in the speed is due to the development of VLSI technology which enabled the integration of millions of transistors on single chip. Even the computational speed has increased the accuracy of the systems is not increased to that extent. Without accuracy, errors can easily occur in any system. The accuracy of a multiplication mostly relies on the precision of the multiplication; double precision multipliers. The multiplication is the most fundamental operation in any arithmetic logic unit. Also the multipliers will take much more time for execution, so the need for speed multiplier with accuracy is desired. Many fast multipliers like array multiplier, booth multiplier etc., are proposed to increase the speed of the multiplication operation. The fast multipliers plays key role in VLSI high speed processor. To design a best processor we need to consider both the accuracy and speed of operation. So a variable precision floating point multiplier when implemented with fast multipliers will have the accuracy and speed which is desired in any processors. II. FLOATING POINT FORMAT The IEEE Standard for Binary Floating-Point Arithmetic (IEEE 754) is the most widely-used standard for floating-point computation, and is followed by many CPU and FPU implementations. The standard defines formats for representing floating-point numbers (including negative zero and de-normal numbers) and special values (infinities and NaNs) together with a set of floating-point operations that operate on these values. It also specifies four rounding modes and five exceptions (including when the exceptions occur, and what happens when they do occur). Four formats for representing floating-point values are: single-precision (32-bit), double-precision (64-bit), single-extended precision ( 43-bit, not commonly used) and double-extended precision( 79-bit, usually implemented with 80 bits). The basic format for single precision is further divided into sign, exponent, and mantissa part as shown in Fig SEMAR GROUPS TECHNICAL SOCIETY. All rights reserved.

2 D. SRIDEVI, DR. L. PADMASREE Fig.1. Format for Single-Precision Z = (-1 S ) * 2 (E - Bias) * (1.M) (1) Where, Bias = 127 M = m m m m m (2) Biased Exponent: A constant is added to the actual exponent so that the biased exponent is always a positive number. The 8-bit exponent for single-precision floatingpoint numbers can take any value in the range -126 to A. Floating Point Multiplier Multiplication is one of the operations which require more number of steps in computation. However, floating point multiplication is somewhat simpler than addition to implement because the significands are represented in sign- magnitude format, which is similar to the integer format. The only additional step required is the calculation of the correct exponent. However, several special cases must be considered. First, if the product is 0, the exponent must be set to the largest negative value which, in the biased case, is 0. Second, if the resulting exponent is too large in B. Multiplication Algorithm As stated in the introduction, normalized floating point numbers have the form of Z= (-1S) * 2 (E - Bias) * (1.M). To multiply two floating point numbers the following is done: 1. Multiplying the significand; i.e. (1.M1*1.M2) 2. Placing the decimal point in the result 3. Adding the exponents; i.e. (E1 + E2 Bias) 4. Obtaining the sign; i.e. s1 x or s2 5. Normalizing the result; i.e. obtaining 1 at the MSB of the results significand 6. Rounding the result to fit in the available bits 7. Checking for underflow/overflow occurrence Consider a floating point representation similar to the IEEE 754 single precision floating point format, but with a reduced number of mantissa bits (only 4) while still retaining the hidden 1 bit for normalized numbers: _ Place the decimal point: Add exponents: The exponent representing the two numbers is already shifted/biased by the bias value (127) and is not the true exponent; i.e. EA=EA-true+bias, EB=EB-true+bias and EA+EB=EA-true+EB-true+2 bias. So we should subtract the bias from the resultant exponent otherwise the bias will be added twice Obtain the sign bit and put the result together: Normalize the result so that there is a 1 just before the radix point (decimal point). Moving the radix point one place to the left increments the exponent by 1; moving one place to the right decrements the exponent by (before normalizing) (normalized) The result is (without the hidden bit): The mantissa bits are more than 4 bits (mantissa available bits); rounding is needed. If we applied the truncation rounding mode then the stored value is: Fig. 2. Floating-point Multiplication block diagram A= = 40, B= =-7.5 To multiply A and B 1. Multiply significand: In this paper we present a floating point multiplier in which rounding support isn t implemented. Rounding support can be added as a separate unit that can be accessed by the multiplier or by a floating point adder, thus accommodating for more precision if the multiplier is connected directly to an adder in a MAC unit. Fig. 2

3 An Efficient Implementation of Floating Pont Multiplier Using Vedic Mathematics shows the multiplier structure; Exponents addition, Significand multiplication, and Result s sign calculation are independent and are done in parallel. The significand multiplication is done on two 24 bit numbers and results in a 48 bit product, which we will call the intermediate product (IP). The IP is represented as (47 down to 0) and the decimal point is located between bits 46 and 45 in the IP. The following sections detail each block of the floating point multiplier. The result of the multiplication is given by the formula: outputs (Difference (R), Borrow out (Bo)). The subtractor logic can be optimized if one of its inputs is a constant value which is our case, where the Bias is constant ( = ). Table I shows the truth table for a 1-bit subtractor with the input T equal to 1 which we will call one subtractor (OS). The following fig 4 denotes the subtractor and the Boolean equations(5) and (6) represent this subtractor: Sign=signA xor signb, e=e A +e B, (3) Mantissa=mantissa A x mantissa B (4) III. HARDWARE OF FLOATING POINT MULTIPLIER A. Sign bit calculation Multiplying two numbers results in a negative sign number iff one of the multiplied numbers is of a negative value. By the aid of a truth table we find that this can be obtained by XORing the sign of two inputs. B. Unsigned Adder (for exponent addition) This unsigned adder is responsible for adding the exponent of the first input to the exponent of the second input and subtracting the Bias (127) from the addition result (i.e. A_exponent + B_exponent - Bias). The result of this stage is called the intermediate exponent. The add operation is done on 8 bits, and there is no need for a quick result because most of the calculation time is spent in the significand multiplication process (multiplying 24 bits by 24 bits); thus we need a moderate exponent adder and a fast significand multiplier. An 8-bit ripple carry adder is used to add the two input exponents. As shown in Fig. 3 a ripple carry adder is a chain of cascaded full adders and one half adder; each full adder has three inputs (A, B, C i ) and two outputs (S, C o ). The carry out (C o ) of each adder is fed to the next full adder (i.e each carry bit "ripples" to the next full adder). Fig.4. Substractor TABLE I 1-BIT SUBTRACTOR WITH THE INPUT T = 1 (5) (6) Fig. 5: 1-bit subtractor with the input T = 1 Table II shows the truth table for a 1-bit subtractor with the input T equal to 0 which we will call zero subtractor (ZS). Fig 5 and 6 shows subtractor with different inputs. The Boolean equations (7) and (8) represent this subtractor: Fig.3. Ripple Carry Adder The addition process produces an 8 bit sum (S 7 to S 0 ) and a carry bit (C o,7). These bits are concatenated to form a 9 bit addition result (S 8 to S 0 ) from which the Bias is subtracted. The Bias is subtracted using an array of ripple borrow subtractors. A normal subtractor has three inputs (minuend (S), subtrahend (T), Borrow in (Bi)) and two Fig. 7 shows the Bias subtractor which is a chain of 7 one subtractors (OS) followed by 2 zero subtractors (ZS); the borrow output of each subtractor is fed to the next subtractor. If an underflow occurs then Eresult < 0 and the number is out of the IEEE 754 single precision normalized (7) (8)

4 D. SRIDEVI, DR. L. PADMASREE numbers range; in this case the output is signaled to 0 and an underflow flag is asserted. TABLE II 1-BIT SUBTRACTOR WITH THE INPUT T = 0 The number of adders (Half adders and Full adders) in each stage is equal to the significand size minus one. For example, a 4x4 carry save multiplier is shown in Fig. 8 and it has the following stages: 1. The first stage consists of three half adders. 2. Two middle stages; each consists of three full adders. 3. The vector merging stage consists of one half adder and two full adders. The decimal point is between bits 45 and 46 in the significand multiplier result. The multiplication time taken by the carry save multiplier is determined by its critical path. The critical path starts at the AND gate of the first partial products (i.e. a 1 b 0 and a 0 b 1 ), passes through the carry logic of the first half adder and the carry logic of the first full adder of the middle stages, then passes through all the vector merging adders. The critical path is marked in bold in Fig. 8. Figure 6: 1-bit subtractor with the input T = 0 Figure 7: Ripple Borrow Subtractor C. Unsigned Multiplier (for significand multiplication) This unit is responsible for multiplying the unsigned significand and placing the decimal point in the multiplication product. The result of significand multiplication will be called the intermediate product (IP). The unsigned significand multiplication is done on 24 bit. Multiplier performance should be taken into consideration so as not to affect the whole multiplier s performance. A 24x24 bit carry save multiplier architecture is used as it has a moderate speed with a simple architecture. In the carry save multiplier, the carry bits are passed diagonally downwards (i.e. the carry bit is propagated to the next stage). Partial products are made by ANDing the inputs together and passing them to the appropriate adder. Carry save multiplier has three main stages: 1. The first stage is an array of half adders. 2. The middle stages are arrays of full adders. The number of middle stages is equal to the significand size minus two. 3. The last stage is an array of ripple carry adders. This stage is called the vector merging stage. Figure 8: 4x4 bit Carry Save multiplier In Figure 8: Partial product: aibj = ai and bj HA: half adder FA: full adder D. Normalizer The result of the significand multiplication(intermediate product) must be normalized to have a leading 1 just to the left of the decimal point (i.e. in the bit 46 in the intermediate product). Since the inputs are normalized numbers then the intermediate product has the leading one at bit 46 or 47. If the leading one is at bit 46 (i.e. to the left of the decimal point) then the intermediate product is already a normalized number and no shift is needed.

5 An Efficient Implementation of Floating Pont Multiplier Using Vedic Mathematics If the leading one is at bit 47 then the intermediate product is shifted to the right and the exponent is incremented by 1. The shift operation is done using combinational shift logic made by multiplexers. Fig. 9 shows a simplified logic of a Normalizer that has an 8 bit intermediate product input and a 6 bit intermediate exponent input. multiplying the numbers of the Column 2 (12 x 3 = 36). The left hand side (LHS) of the product can be found by cross subtracting the second number of Column 2 from the first number of Column 1 or vice versa, i.e., 88 3 =85 or TABLE III: SELECTING THE NEAREST BASE 100, HENCE THE RESULT IS 88 X 97 = 8536 Fig.9. Simplified Normalizer logic IV. VEDIC MATHEMATICS A."Nikhilam Navatascaramam Dasatah" Sutra Nikhilam Sutra literally means all from 9 and last from 10. This technique is applicable to all the cases of multiplication but it is more efficient in case of multiplication of large numbers. In this method, the compliment of the large number is found from its nearest base to perform the multiplication operation on it, hence larger the original number, lesser the complexity of the multiplication. Let us understand this technique with the help of some example. If we want to multiply two numbers i.e. 88 x 97, it can be done as follows using Nikhilam Sutra technique 88 x 97 Select near Base as 100. As shown in Table 2, we write the multiplier and the multiplicand in two rows followed by the differences of each of them from the chosen base, i.e., their compliments. We can now write two columns of numbers, one consisting of the numbers to be multiplied (Column 1) and the other consisting of their compliments (Column 2). The product also consists of two parts which are written in table II for the purpose of illustration. The right hand side (RHS) of the product can be obtained by simply Fig. 10.Hardware implementation of Nikhilam sutra =85. The final result is obtained by concatenating RHS and LHS i.e Architecture of Vedic Multiplier Using Nikhilam Sutra: Broadly this architecture is divided into three parts. 1. Radix Selection Unit 2. Exponent Determinant 3. Multiplier.

6 D. SRIDEVI, DR. L. PADMASREE Hardware implementation of this multiplier is shown in Fig 10. The architecture can be decomposed into three main subsections: (1) Radix Selection Unit (RSU) (2) Exponent Determinant (ED) and (3) Multiplier. The RSU is required to select the proper radices corresponding to the input numbers. B. Mathematical Expression for Nikhilam Sutra Nikhilam sutra means "all from (9) and last from (10)". Mathematical description of this sutra can be formulated as: Assuming A and B are two n-bit numbers to be multiplied and their product is equals to P. The below equations (9) and (10) X = 2 k1 ± Z l (16) y = 2 k2 ± Z 2 (17) For the fast multiplication using Nikhilam sutra the bases of the multiplicand and the multiplier would be same, (here we have considered different base) thus the equation (17) can be rewritten as (18) (9) (10) Multiplication Rule: P=AB (11) Equation (11) can be reformulated as by adding and subtracting the term 10 2n +10 2n (A+B) in the right hand side P =AB n +10 n (A + B) n - 10 n (A + B) =10 n (A+B)-10 2n }+10 2n -10 n (A+B)+AB (12) Equation no 12 can be derived for both the numbers if the number is greater than the base or less than the base. If the number is greater than the base: =10 n {(A+B)-IO n }+{(10 n -A)(IO n -B)} (13) If the number is less than the base: =10 n {(A+B)-10 n }+{(A-10 n )(B-10 n )} =10 n {A-(10 n -B)}+{(10 n -A)(10 n -B)} =10 n (A - B) + (A B)} (14) Where A and B are the10 n,s complement of A and B. Subtraction Rule:equation (15) (15) The serious drawback of Nikhilam sutra can be summarized as: Both the multiplier and multiplicand are less or greater than the base. Multiplier and multiplicand are nearer to the base. (19) (20) The architecture can be decomposed into three main subsections: (1) Radix Selection Unit (RSU) (2) Exponent Determinant (ED) and (3) Array Multiplier. The RSU is required to select the proper radices corresponding to the input numbers. If the selected radix is nearer to the given number then the multiplication of the residual parts (Zl xz2) can be Easier to compute. The Subtractor blocks are required to extract the residual parts (Z I and Z 2 ). The second subsection (ED) is used to extract the power (k l and k 2 ) of the radix and it is followed by a subtractor to calculate the value of (k 1 - k 2 ).The third subsection array multiplier is used to calculate the product (Z 1 xz 2 ). The output of the subtractor (k l -k 2 ) and Z 2 are fed to the shifter block to calculate the value of Z 2 x 2 k1-k2.the first addersubtractor block has been used to calculate the value of X ± Z2 x 2 k1 -k2. The output of the first adder-subtractor and the output of the second Exponent Determinant (k 2 ) are fed to the second shifter block to compute the value of Zk 2 x (X ± Z 2 X 2 k1-k2 ). The output of the multiplier (Z 1 xz 2 ) and the output of the second shifter (2 k 2 x (X ± Z 2 x 2 k1-k2 ))are fed to the second adder subtractor block to compute the value of (2 k 2 x (X ± Z 2 x 2 k1-k2 )) ± Z l Z 2. D. Mathematical expression for RSU The Block level architecture of RSU as shown in Fig 10 RSU consists of three main subsections: 1. Exponent Determinant (ED). 2. Mean Determinant (MD). 3. Comparator. C. Proposed Multipller Architecture Design The mathematical expression for the proposed algorithm is shown below. Broadly this algorithm is divided into three parts. (1) Radix Selection Unit, (2) Exponent Determinant and (3) Multiplier. Consider two n bit numbers X and Y. kl and k2 are the exponent of X and Y respectively. X and Y can be represented as: 'n' number bit from input X is fed to the ED block. The maximum power of X is extracted at the output which is again fed to shifter and the adder block. The second input to the shifter is the (n+ 1) bit representation of decimal '1 '.If the maximum power of X from the ED unit is (n-1) then the output of the shifter is i"-1). The adder unit is needed to increment the value of the maximum power of X

7 An Efficient Implementation of Floating Pont Multiplier Using Vedic Mathematics by '1'. The second shifter is needed to generate the value of 2".Here n is the incremented value taken from the adder block. The Mean Determinant unit is required to compute the mean of (2 n-l + 2 n ). The Comparator compares the actual input with the mean value of (2 n-l + 2 n ). If the input is greater than the mean then 2 n is selected as the required radix. If the input is less than the mean then 2 n-1 is selected as the radix. The select input to the multiplexer block is taken from the output of the comparator. to be shifted or not (to initialize the operation 'Shift' pin is initialized to low). A decrementer has been integrated in this architecture to follow the maximum power of the radix. A sequential searching procedure has been implemented here to search the first '1' starting from the MSB side by using shifting technique. For an N bit number, the value (N-1) 10 Fig.12: Hard ware implementation exponent determinant Fig.11. Hardware implementation of RSU Consider an n bit binary number X,and it can be represented as (21) fed to the input of decrementer. The decrementer is decremented based on a control signal which is generated by the searched result. If the searched bit is '0' then the control signal becomes low then decrementer start decrementing the input value (Here the decrementer is operating in active low logic). The searched bit is used as a controller of the decrementer. When the searched bit is 'I' then the control signal becomes high and the decrementer stops further decrementing and shifter also stops shifting operation. The output of the decrementer shows the integer part (exponent) of the number. Where, in the range the range is equal to A.Then the values of X must lie Consider the mean of V. RESULTS AND DISCUSSIONS This chapter will provide the simulation and synthesis results of the project. The simulation is done using the Modelsim6.0 simulator and the synthesis is done using the Xilinx ISE synthesis tool. The simulation and synthesis results of various design units are presented and each of them is explained with respected to its functionality. (22) E. Exponent Determinant The hardware implementation of the exponent determinant is shown in Fig 12. The integer part or exponent of the number from the binary fixed point number can be obtained by the maximum power of the radix. For the nonzero input, shifting operation is executed using parallel in parallel out (PIPO) shift registers. The number of select lines of the PIPO shifter is chosen as per the binary representation of the number (N-1) 10. 'Shift' pin is assigned in PIPO shifter to check whether the number is A. Register transfer level (RTL) schematic In integrated circuit design, register transfer level (RTL) description is a way of describing the operation of a synchronous digital circuit. In RTL design, a circuit's behavior is defined in terms of the flow of signals (or transfer of data) between hardware registers, and the logical operations performed on those signals. After the HDL synthesis phase of the synthesis process, use the RTL Viewer to view a schematic representation of the preoptimized design. The RTL schematic of floating point multiplier is shown in Fig.13, technology schematic of floating point multiplier is shown in Fig.14 and behavioral

8 D. SRIDEVI, DR. L. PADMASREE simulation waveform of floating point multiplier is shown in Fig RTL schematic XOR gate is shown in Fig.16 and behavioral simulation waveform of the XOR gate is shown in Fig RTL schematic Fig.13: RTL schematic of floating point multiplier 2. Technology schematic for FPM Fig.15. RTL schematic of XOR gate 2. Technology schematic Fig.16. Technology schematic of XOR gate 3. Simulation result Fig.17. Technology schematic of 8 bit XOR gate C. Simulation report for the floating point multiplier Fig.14: Technology schematic of floating point multiplier B. XOR gate: This is the normal XOR gate operation. a and b are the inputs and c is the output. If only one input is high, then output is high otherwise output is low. The RTL schematic of XOR gate is shown in Fig.15, technology schematic of Fig.18: simulation report for floating point multiplier

9 An Efficient Implementation of Floating Pont Multiplier Using Vedic Mathematics D. Design summary for 16 bit floating point multiplier TABLE IV: SRIDEVI PARTITION SUMMARY TABLE V: DEVICE UTILIZATION SUMMARY TABLE VI: PERFORMANACE SUMMARY

10 D. SRIDEVI, DR. L. PADMASREE E. RTL Schematic The Hardware description languages are most used for is the Register Transfer Level (RTL). Between gate level on the low abstraction side and system level on the high abstraction side, The RT level of abstraction is a good balance between corresponds to actual hardware and ease of description for hardware designers. At this level of abstraction designs can be simulated with HDL simulators, they are synthesizable and automatic generation of hardware is provided by most hardware design EDA tools. Routing and Placement phase decides on the placement of cells of the target hardware. Wiring inputs and outputs of these cells through wiring channels and switching areas of the target hardware are determined by the routing and placement phase. The output of this phase is specific to the hardware being used and can be used for programming an FPLD or Manufacturing an ASIC. F. Floor-planner Floor-planner after a design has been placed and routed allows designers to view and possibly improve the results of the automatic implementation. In an iterative floor plan design flow, designers floor plan and place and route interactively shown in Fig.19. The logic placement in the Floor plan window can be modified as often as necessary to achieve design goals. Iterations of a floor planned design can be saved for use later as a constraints file during PAR. Fig.19. Floor-planner - Package View V.CONCLUSION AND FUTURE WORK An implementation of a floating point multiplier that supports the IEEE binary interchange format; the multiplier doesn t implement rounding and just presents the significand multiplication result as is (16 bits); this gives better precision if the whole 16 bits are utilized in another unit; i.e. a floating point adder to form a MAC unit. The design can be extended to find n-bit complex multiplications and different low power techniques can be applied to this model as to reduce the power to significant level. VI. REFERENCES [1] IEEE , IEEE Standard for Floating-Point Arithmetic, [2] B. Fagin and C. Renard, Field Programmable Gate Arrays and Floating Point Arithmetic, IEEE Transactions on VLSI, vol. 2, no. 3, pp , [3] N. Shirazi, A. Walters, and P. Athanas, Quantitative Analysis of Floating Point Arithmetic on FPGA Based Custom Computing Machines, Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines (FCCM 95), pp , [4] L. Louca, T. A. Cook, and W. H. Johnson, Implementation of IEEE Single Precision Floating Point Addition and Multiplication on FPGAs, Proceedings of 83 the IEEE Symposium on FPGAs for Custom Computing Machines (FCCM 96), pp , [5] R. Krishnan, G. A. Jullien, and W. C. Miller, "Complex digital signal processing using quadratic residue number systems," IEEE Trans. Acoust., Speech, Signal processing, vol. 34, Feb [6] T. Aoki, K. Hoshi, and T. Higuchi, "Redundant complex arithmetic and its application to complex multiplier design," in Proceedings 29th IEEE International symposium on Multiple-Valued-Logic, Freiburg, May 20-22, 1999, pp [7] Z. Huang, and M. D. Ercegovac, "High-Performance Low-Power Leftto- Right Array Multiplier Design," IEEE

11 An Efficient Implementation of Floating Pont Multiplier Using Vedic Mathematics Transactions on Computers, vol 54, no. 3, pp , March [8] S. Y. Kung, H. J. Whitehouse, and T. Kailath, VLSI and Modern Signal Processing, Englewood Cliffs, NJ: Prentice-Hall, [9] P. Mehta, and D. Gawali, "Conventional versus Vedic mathematical method for Hardware implementation of a multiplier," in Proceedings IEEE International Cotiference on Advances in Computing, Control, and Telecommunication Technologies, Trivandrum, Kerala, Dec , 2009, pp [10] H. D. Tiwari, G. Gankhuyag, C. M. Kim, and Y. B. Cho, "Multiplier design based on ancient Indian Vedic Mathematics," in Proceedings IEEE International SoC Design Cotiference, Busan, Nov , 2008, pp