Lecture 3: Basic Adders and Counters

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1 Lecture 3: Basic Adders and Counters ECE 645 Computer Arithmetic /5/8 ECE 645 Computer Arithmetic Lecture Roadmap Revisiting Addition and Overflow Rounding Techniques Basic Adders and Counters

2 Required Reading B. Parhami, Computer Arithmetic: Algorithms and Hardware Design Chapter 7, Floating-Point Representations (7.5) Chapter 5, Basic Addition and Counting (5.-5.5) Note errata at: 3 Revisiting Addition and Overflow ECE 645 Computer Arithmetic

3 Adding Unsigned Binary Numbers: Ignoring Overflow Ignoring overflow, adding a K.L binary unsigned number to a K.L binary unsigned number results in a K.L number Example:. + K=4, L= Ignore c K. =. Adding resulted in 3.75 Must add ^K=^4=6 to result to get correct value due to overflow 5 Adding Unsigned Binary Numbers: Ignoring Overflow in VHDL library IEEE; use IEEE.STD_LOGIC_64.all; use IEEE.STD_LOGIC_ARITH.all; use IEEE.STD_LOGIC_UNSIGNED.all; entity adder_unsigned is port( a : in STD_LOGIC_VECTOR( downto ); b : in STD_LOGIC_VECTOR( downto ); sum : out STD_LOGIC_VECTOR( downto )); end adder_unsigned; architecture arch of adder_unsigned is begin sum <= a + b; end arch; 6

4 Adding Unsigned Binary Numbers: Avoiding or Detecting Overflow To avoid overflow, adding a K.L binary unsigned number to a K.L binary unsigned number results in a (K+).L number Example:. + Carry-out c K is new MSB of result. =. K=4, L= If result is confined to a K.L number, need overflow detection, which is the carry-out bit (see previous lecture) Example:. +. = Carry-out c K indicates overflow. 7 Adding Unsigned Binary Numbers: Avoiding Overflow in VHDL Zero pad input values with '', then add and ignore final carryout (c K+ ) Example:. + K=4, L= Ignore c K+. =. use IEEE.STD_LOGIC_UNSIGNED.all; entity adder_unsigned_carryout is port( a : in STD_LOGIC_VECTOR( downto ); b : in STD_LOGIC_VECTOR( downto ); sum : out STD_LOGIC_VECTOR( downto )); end adder_unsigned_carryout; architecture arch of adder_unsigned_carryout is signal tempsum : std_logic_vector( downto ); begin tempsum <= ('' & a) + ('' & b); -- pad with before addition sum <= tempsum; -- alternatively, sum() is the carryout, i.e. overflow flag end arch; 8

5 Adding Two's Complement Numbers: Ignoring Overflow Ignoring overflow, adding a K.L two's complement number to a K.L two's complement number results in a K.L number Example: = Ignore c Ignore c K. = K.. Adding resulted in -.5 Must add ^K=^4=6 to result to get correct value (3.75) Adding resulted in + Must add -^K=-^4=-6 to get correct value (-5) Recall: overflow only possible when adding two numbers of the same sign (positive+positive or negative+negative) Two's complement addition ignoring overflow is also called modulo addition (with modulus of K ) or wraparound addition A two's complement overflow is also called a wraparound A number can represent itself (x) and any positive or negative multiple x + K *j, j=,+/-, +-/ 9 Adding Two's Complement Numbers: Ignoring Overflow in VHDL library IEEE; use IEEE.STD_LOGIC_64.all; use IEEE.STD_LOGIC_ARITH.all; use IEEE.STD_LOGIC_SIGNED.all; entity adder_signed is port( a : in STD_LOGIC_VECTOR( downto ); b : in STD_LOGIC_VECTOR( downto ); sum : out STD_LOGIC_VECTOR( downto )); end adder_signed; architecture arch of adder_signed is begin sum <= a + b; end arch;

6 Two's Complement Wraparound Property Temporary wraparounds are fine as long as final value is in the correct dynamic range: Example: add ( ) + 7 = -7 + = Should be (-4) not (+) wraparound/overflow + = Final result is correct: (-7) If final result guaranteed to be in the correct dynamic range [-8,+7] then intermediate wraparounds are fine Two's Complement Wraparound

7 Adding Two's Complement Numbers: Avoiding or Detecting Overflow To avoid overflow, adding a K.L binary two's complement number to a K.L two's complement number results in a (K+).L number. To compute, sign extend MSB, ignore c K+ Example:. + K=4, L= Ignore c. = K+. If result is confined to a K.L number, need overflow detection, which is the c K xor c K- (see previous lecture) Example:. + c K XOR c K- indicates overflow. =. 3 Adding Two's Complement Numbers: Avoiding or Detecting Overflow in VHDL Sign extend input values, then add and ignore final carryout (c K+ ) Example:. + Ignore c K+. =. use IEEE.STD_LOGIC_SIGNED.all; entity adder_signed_carryout is port( a : in STD_LOGIC_VECTOR( downto ); b : in STD_LOGIC_VECTOR( downto ); sum : out STD_LOGIC_VECTOR( downto )); end adder_signed_carryout; architecture arch of adder_signed_carryout is signal tempsum : std_logic_vector( downto ); begin tempsum <= (a() & a) + (b() & b); -- sign extend before addition sum <= tempsum; end arch; 4

8 Subtracting Two's Complement Numbers: Ignoring Overflow Ignoring overflow, subtracting a K.L binary two's complement number from a K.L two's complement number results in a K.L number Example: - + = Ignore c K 7 (-8) resulted in - A wraparound/overflow occured Must add ^K=^4=6 to get correct value of +5 Again we see the modulo effect As with addition, temporary wraparounds are okay as long as final result is in correct dynamic range 5 Subtracting Two's Complement Numbers: Avoiding or Detecting Overflow To avoid overflow, subtracting a K.L binary two's complement number from a K.L two's complement number results in a (K+).L number Example: =. Ignore c K+ If result is confined to a K.L number, need overflow detection, which is the c K xor c K- (see previous lecture) Example: = c K XOR c K- indicates overflow. 6

9 Subtracting Two's Complement Numbers: Avoiding Overflow in VHDL library IEEE; use IEEE.STD_LOGIC_64.all; use IEEE.STD_LOGIC_ARITH.all; use IEEE.STD_LOGIC_SIGNED.all; entity adder_signed_carryout is port( a : in STD_LOGIC_VECTOR( downto ); b : in STD_LOGIC_VECTOR( downto ); sum : out STD_LOGIC_VECTOR( downto )); end adder_signed_carryout; architecture arch of adder_signed_carryout is signal tempsum : std_logic_vector( downto ); begin tempsum <= (a() & a) - (b() & b); -- sign extend BEFORE addition, very important sum <= tempsum; end arch; 7 Negating a Two's Complement Number Negating a K.L two's complement number usually only requires a K.L digit result. The only exception is when you negate the largest negative number, and you need a K.(L+) digit result. - = - = need extra bit to negate largest negative number Can view negation of x as ( x) Can use the same mechanisms and overflow detection as subtraction + 8

10 Rounding Techniques ECE 645 Computer Arithmetic Rounding Rounding occurs when we want to approximate a more precise number (i.e. more fractional bits L) with a less precise number (i.e. fewer fractional bits L') Example : old:. (K=6, L=8) new:. (K'=6, L'=) Example : old:. (K=6, L=8) new:. (K'=6, L'=) The following pages show rounding from L> fractional bits to L'= bits, but the mathematics hold true for any L' < L Usually, keep the number of integral bits the same K'=K

11 Rounding Equation Whole part Fractional part x k x k... x x. x x... x Round l y k y k... y y y = round(x) Rounding Techniques There are different rounding techniques: ) truncation results in round towards zero in signed magnitude results in round towards - in two's complement ) round to nearest number 3) round to nearest even number (or odd number) 4) round towards + Other rounding techniques 5) jamming or von Neumann 6) ROM rounding Each of these techniques will differ in their error depending on representation of numbers i.e. signed magnitude versus two's complement Error = round(x) x

12 ) Truncation The simplest possible rounding scheme: chopping or truncation x k x k... x x. x x... x trunc l x k x k... x x ulp Truncation in signed-magnitude results in a number chop(x) that is always of smaller magnitude than x. This is called round towards zero or inward rounding. (3.5) (3) Error = -.5. (-3.5) (-3) Error = +.5 Truncation in two's complement results in a number chop(x) that is always smaller than x. This is called round towards - or downward-directed rounding. (3.5) (3) Error = -.5. (-3.5) (-4) Error = Truncation Function Graph: chop(x) chop(x) 4 3 x Fig. 7.5 Truncation or chopping of a signed-magnitude number (same as round toward ). chop(x) 4 3 x Fig. 7.6 Truncation or chopping of a s-complement number (same as round to - ). 4

13 Bias in two's complement truncation X (binary) X (decimal) chop(x) (binary) chop(x) (decimal) Error (decimal) Assuming all combinations of positive and negative values of x equally possible, average error is In general, average error = -( -L' - -L )/, where L' = new number of fractional bits 5 Implementation truncation in hardware Easy, just ignore (i.e. truncate) the fractional digits from L to L'+ x k- x k-.. x x. x - x -.. x -L = y k- y k-.. y y. ignore (i.e. truncate the rest) 6

14 ) Round to nearest number Rounding to nearest number what we normally think of when say round rtn in two's complement. (.5) (3) Error = +.5. (-.5) (-) Error = Round to Nearest Function Graph: rtn(x) rtn(x) x 3 4 8

15 Bias in two's complement round to nearest X (binary) X (decimal) rtn(x) (binary) rtn(x) (decimal) Error (decimal) Assuming all combinations of positive and negative values of x equally possible, average error is +.5 Smaller average error than truncation, but still not symmetric error We have a problem with the midway value, i.e. exactly at.5 or -.5 leads to positive error bias always Also have the problem that you can get overflow if only allocate K' = K integral bits Example: rtn(.) overflow This overflow only occurs on positive numbers near the maximum positive value, not on negative numbers 9 Implementing round to nearest (rtn) in hardware Two methods Method : Add '' in position one digit right of new LSB (i.e. digit L'+) and keep only L' fractional bits x k- x k-.. x x. x - x -.. x -L + = y k- y k-.. y y. Method : Add the value of the digit one position to right of new LSB (i.e. digit L'+) into the new LSB digit (i.e. digit L) and keep only L' fractional bits x k- x k-.. x x. x - x -.. x -L + x - y k- y k-.. y y. ignore (i.e. truncate the rest) ignore (i.e truncate the rest) 3

16 Round to Nearest Even Function Graph: rtne(x) To solve the problem with the midway value we implement round to nearest-even number (or can round to nearest odd number) rtne(x) R*(x) Fig. 7.8 Rounding to the nearest even number. x Fig. 7.9 R* rounding or rounding to the nearest odd number. x 3 Bias in two's complement round to nearest even (rtne) X (binary) X (decimal ) rtne(x) (binary) rtne(x) (decimal) Error (decimal) (overfl) average error is now (ignoring the overflow) cost: more hardware 3

17 4) Rounding towards infinity We may need computation errors to be in a known direction Example: in computing upper bounds, larger results are acceptable, but results that are smaller than correct values could invalidate upper bound Use upward-directed rounding (round toward + ) up(x) always larger than or equal to x Similarly for lower bounds, use downward-directed rounding (round toward - ) down(x) always smaller than or equal to x We have already seen that round toward - in two's complement can be implemented by truncation 33 Rounding Toward Infinity Function Graph: up(x) and down(x) up(x) down(x) down(x) can be implemented by chop(x) in two's complement 34

18 Two's Complement Round to Zero Two's complement round to zero (inward rounding) also exists inward(x ) 4 3 x Other Methods Note that in two's complement round to nearest (rtn) involves an addition which may have a carry propagation from LSB to MSB Rounding may take as long as an adder takes Can break the adder chain using the following two techniques: Jamming or von Neumann ROM-based 36

19 5) Jamming or von Neumann jam(x) x Chop and force the LSB of the result to Simplicity of chopping, with the near-symmetry or ordinary rounding Max error is comparable to chopping (double that of rounding) ) ROM Rounding ROM(x) x Fig. 7. ROM rounding with an 8 table. Example: Rounding with a 3 4 table Rounding result is the same as that of the round to nearest scheme in 3 of the 3 possible cases, but a larger error is introduced when x 3 = x = x = x = x = x k... x 4 x 3 x x x. x x... x l ROM x k... x 4 y 3 y y y ROM address ROM data 38

20 ANSI/IEEE Floating-Point Standard ANSI/IEEE standard includes four rounding modes: Round to nearest even [default rounding mode] Round toward zero (inward) Round toward + (upward) Round toward (downward) 39 Basic Addition and Counters ECE 645 Computer Arithmetic

21 Half-adder c s HA x y x + y = ( c s ) x y c s 4 Half-adder Alternative implementations () a) c = xy s = x y b) c = x + y s = xy + xy 4

22 Half-adder Alternative implementations () c) c = xy s = xc + yc = xc yc 43 Full-adder c out s FA x y c in x + y + c in = ( c out s ) x y c out s c in 44

23 Full-adder Alternative implementations () a) s = (x y) c in c out = xy + c in (x y) c c s 45 Full-adder Alternative implementations () b) c out = xy + xc in + yc in s = x y c in = xyc in + xyc in + xyc in + xyc in 46

24 Full-adder Alternative implementations (3) c) x y c out s c in c in c in c in c in c in 47 Full-adder Alternative implementations (4) Implementation used to generate fast carry logic in Xilinx FPGAs x y c out y c in c in y p = x y g = y x y A A XOR D p g C out C in S s= p c in = x y c in 48

25 CMOS Transmission Gate 49 Ripple-Carry Adder 5

26 Critical Path 5 Latency of a k-bit ripple-carry adder T ripple-add = T FA (x,y c out ) + + (k-) T FA (c in c out ) + + T FA (c in s) Latency k T FA Latency k 5

27 Layout of Ripple-Carry Adder in CMOS 53 Two's Complement Adder 54

28 Two's Complement Overflow Indication of overflow Formulas Positive + Positive = Negative Negative + Negative = Positive Overflow s complement = x k- y k- s k- + x k- y k- s k- = = c k c k- 55 Two's Complement Overflow x k- y k- c k- c k s k- overflow c k c k- 56

29 Bit-Serial Adder 57 Bit-Serial Adder Interface x i y i c i+ Bit-serial adder c start clk s i 58

30 Digit-Serial Adder x i d y i d c i+ Digit-serial adder c start clk d s i 59 Addition of a Constant () + x k- x k-... x x y k- y k-... y y s k- s k-... s s variable constant + x k- x k-... x h+ x h x h-... x y k- y k-... y h+... variable constant s k- s k-... s h+ x h x h-... x 6

31 Addition of a Constant () x k- x k-... x h+ x h+ x h x h-... x c k HA/ MHA HA/ MHA.. HA/ MHA HA/ MHA... s k- s k s h+ s h+ x h x h- x If y i = y i = Half-adder (HA) Modified half-adder (MHA) 6 Modified Half-Adder c s MHA x y x + y + = ( c s ) x y c s 6

32 Incrementer x k- x k-... x x x c k HA HA.. HA HA Decrementer s k- s k-... s s x x k- x k-... x x x c k MHA MHA.. MHA MHA s k- s k-... s s x 63 Counter 64

33 Three-Stage Up Counter 65 Possible Solutions to Carry Propagate Problem. Detect the end of propagation rather than wait for the worst-case time. Speed-up propagation via look-ahead carry skip carry select, etc 3. Limit carry propagation to within a small number of bits 4. Eliminate carry propagation through the redundant number representation 66

34 Carry Chain Lengths 67 Analysis of Carry Propagation Probability of carry generation = (x i y i = ) 4 Probability of carry propagation = (x i y i = or ) Probability of carry anihilation = (x i y i = or ) Probability of carry propagating from position i to position j = j j i+ i or or j i probability of propagation = probability of anihilation j i 68

35 Expected length of the carry chain that starts at position i () Expected length(i, k) = k j i j i ( ) j = i + k k i + ( ) i Length of the carry chain Probability of the given length Distance till the end of adder Probability of propagation till the end of adder 69 Expected length of the carry chain that starts at position i () Expected length(i, k) = ( k i ) For i << k Expected length of the carry propagation is 7

Number Representation

ECE 645: Lecture 5 Number Representation Part 2 Floating Point Representations Rounding Representation of the Galois Field elements Required Reading Behrooz Parhami, Computer Arithmetic: Algorithms and