Lecture (09) Programmable Logic Devices programming using CUPL By: Dr. Ahmed ElShafee

Transcription

1 Lecture (09) Programmable Logic Devices programming using CUPL By: Dr. Ahmed ElShafee ١ Dr. Ahmed ElShafee, ACU : Spring 2018, CSE303 Logic design II What is Programmable Logic? Digital integrated circuits where the Boolean function can be determined by the user. PLDs can replace several specific purpose ICs in a digital design. A single PLD is functionally equivalent to a specific device containing from 5 to 10,000 gates. Typically PLDs implement Boolean functions using Sum Of Minterms (SOM) or Sum of Products (SOP) form. SOM and SOP use a AND OR gate structure. ٢

2 PLD Programming PLDs are manufactured in a "blank" or "erased" form. Programming is performed in concept blowing out fuses between inputs, AND gates, and OR gates in the generic AND OR structure. An erased PLD has all fuses intact. Actual "fuses" may be implemented as: ٣ PLD Advantages: reduce IC package count board space power shorten design time allow for future changes (maintainability) improve reliability (fewer packages) generally faster smaller inventory ٤

3 Introduction to Atmel ATF16V8C Industry standard Architecture Emulates Many 20 pin PALs Low cost Easy to use Software Tools High speed Electrically erasable Programmable Logic Devices 5 ns Maximum Pin to pin Delay Low power 100 μapin controlled Power down Mode Option CMOS and TTL Compatible Inputs and Outputs I/O Pin Keeper Circuits ٥ Advanced Flash Technology Reprogrammable 100% Tested High reliability CMOS Process 20 Year Data Retention 100 Erase/Write Cycles 2,000V ESD Protection 200 ma Latchup Immunity Commercial and Industrial Temperature Ranges Dual in line and Surface Mount Packages in ٦ Standard Pinouts

4 Designing with the CUPL Language *Cornell University Programming Language WinCUPL is a software package that runs on an PC. It performs most of the work in translating a PLD design into a programming file. The programming file can be used to program an IC to implement the desired logic functions. ٧ CUPL Programming models Combinational Use equations or Truth table Sequential Use Equations or State Machine ٨

5 File extensions File extensions that will be useful to know PLD DOC ABS LST JED SI SO ٩ Created by the user Contains all of the logic instructions necessary for your device, i.e. the cupl program itself. Generated by CUPL Contains all of the logic equations that CUPL generated from your program Tells you errors encountered in compiling the program (including location) Provides information about how it fit the compiled logic into the selected device. Generated by CUPL File used by CUPL to perform the simulation Generated by CUPL Error Listing file that contains all the original lines of code numbered. All errors are listed at the end with offending line number. Generated by CUPL File used by the programmer to actually burn the chip Filename comes from the Name field in the pld file header Simulation Input file created by user Contains your list of test vectors Simulation Output file generated by CUPL Contains the results of the simulation run including any errors Used for the Dr. graphical Ahmed ElShafee, display of ACU your : simulation Spring 2018, results CSE303 Logic design II CUPL Language Numbers can be represented in binary, octal, decimal, or hexadecimal. Pin numbers and indexed variable will always be represented in decimal. The default base for all other number is hexadecimal. To indicate a particular base, precede the number will the particular prefix (which is not case sensitive). ١٠

6 ١١ Variables are case sensitive cannot have spaces cannot use reserved words or symbols ١٢

7 Reserved Symbols & Symbol sets ١٣ Indexed Variables Example: [A0, A1, A2, A3] might be a 4 bit address Indexing should always start from 0, not 1 or such. Another notation for these is [A0..3] when using the entire group The index cannot be greater than 31 ١٤

8 CUPL program format There are three parts to a CUPL file (a.pld file) Header Declarations Main body ١٥ Header The following are the basic header fields: All of the header fields are required to be present in the file, but only the Name field is required to have a real value in it. It will be used Dr. Ahmed as ElShafee, the ACU name : Spring for 2018, CSE303 the JEDEC Logic design II output file ١٦ Name XXXXX; Partno XXXXX; Date XX/XX/XX; Revision XX; Designer XXXXX; Company XXXXX; Assembly XXXXX; Location XXXXX; Device XXXXX;

9 Declarations The standard place to set up all your variables for the program. Pin Assignment This section allows you specifically assign variable names to individual pins on the part. You need to make sure that your assignment of pins does not conflict with device specification of pins (i.e. clock, input only, input or output, etc.). Pin 1 =!a; Assign pin 1 to be "not a". The optional '!' defines the polarity. Pin [2..5] = [b, c, d, e]; assign pin 2=b, pin 3=c, pin 4=d, pin5=e Pin [6,10] = [f,g]; Assign pin 6 to f and pin 7 to g. ١٧ The polarity selection allows you to choose whether the signal is active high or active low. Default, without a bang, is active high. This allows you to simply write equations without having to worry about if the signal is active high or low. You can simply refer to it as being asserted or not. e.g. Pin 2 =!A; Pin 3 =!B; Pin 16 = Y; Y = A & B; Y will be true (high) when both A and B are true (both are low). ١٨

10 Bit Field Declaration Bit Fields allow you to refer to a group of bits by a single variable e.g. FIELD Data = [D0..D7]; Assigns Data name to group of bits. FIELD Control = [strobe,ack,rdy]; Also works on individual pins. ١٩ Preprocessor Commands Just as in C programming you can use preprocessor commands. The most common command used is the $DEFINE. e.g. $DEFINE ON 'b'1 $DEFINE OFF b 0 ٢٠

11 Main body Arithmetic Operations They must also appear in braces {}. ٢١ Logic equations ٢٢

12 Truth Table TABLE var_1 => var_2 { input_n => output_n; input_y => output_y; } FIELD input = [In3..0]; FIELD output = [out4..0]; TABLE input => output { h 0=> d 00; h 1=> d 01; h 2=> d 02; h 3=> d 03; h 4=> d 04; h 5=> d 05; h 6=> d 06; h 7=> d 07; h 8=> d 08; h 9=> d 09; h A=> d 10; h B=> d 11; h C=> d 12; h D=> d 13; h E=> d 14; h F=> d 15; } ٢٣ FIELD INPUT = [x,y,z]; FIELD OUTPUT = [A,B]; * Truth Table * TABLE INPUT => OUTPUT { 0=>'b'01; 1=>'b'00; 2=>'b'10; 3=>'b'11; 4=>'b'01; 5=>'b'11; 6=>'b'00; 7=>'b'01; } ٢٤

13 Condition Statement CONDITION { if expr0 OUT var1; if exprn OUT var2; default OUT var3; } ٢٥ PIN [1,2] = [A,B] ; Data Inputs PIN 3 =!enable ; Enable Input PIN [12..15] = [Y0..3] ; Decoded Outputs PIN 14 = no_match ; Match Output CONDITION { IF enable &!B &!A out Y0; IF enable &!B & A out Y1; IF enable & B &!A out Y2; IF enable & B & A out Y3; default no_match; } ٢٦

14 Working with wincupl Selecting your device ٢٧ ٢٨

15 Compiling options ٢٩ ٣٠

16 ٣١ Miscellaneous Options ٣٢

17 Secure device: Adds necessary code to allow the programmer to blow the security fuse of the device. Generally you won't want to do this since you aren't actually producing a product. I'm also not sure if this functionality is available with Allpro. Deactivate Unused OR Terms: Normally on an OR gate array output, unused OR gate inputs are left connected to the product term array so that new terms may be added. By selecting this option, all unused inputs will be disconnected, thereby reducing propagation delay through the device. ٣٣ Simulate & Display Waveform: These two options allow you to perform compilation and simulation all in one step. Make sure that the Display Waveform option is not checked unless you are also simulating. I would suggest that you don't use this as it can become a pain as you are trying to debug syntax of your program. One Hot bit State Machine: To use this, you need to define each state with a one hot bit code. Checking this will then allow CUPL to use slightly different optimization techniques. The results will vary depending on the part being used. Generally leave ٣٤ this unchecked.

18 JEDEC Name = Filename: This forces cupl to make the name of your output file (JED) the same as your program name (PLD) rather than using the name specified in the NAME field of the header ٣٥ ٣٦

19 ٣٧ Gates simulation example ٣٨

20 ٣٩ ٤٠

21 ٤١ ٤٢

22 ٤٣ Name Gates; Partno 0; Revision 0; Date 9/12/18; Designer AFee; Company ACU; Location None; Assembly None; Device g16v8a; * Inputs: Pin 2 = a; Pin 3 = b; ٤٤

23 * Outputs: Pin 12 = xor; Pin 13 = or; Pin 14 = nand; Pin 15 = and; Pin 16 = invb; Pin 17 = inva; Pin 18 = repb; Pin 19 = repa; * code repa = a; buffer repb = b; inva =!a; inverters invb =!b; and = a & b; and gate nand =!(a & b); nand gate or = a # b; or gate nor = ٤٥!(a # b); nor gate xor = a $ b; exclusive or gate ٤٦

24 Name decoder; Partno 0; Revision 0; Date 9/12/18; Designer AFee; Company ACU; Location None; Assembly None; Device g16v8a; * Inputs: Pin 2 = a; Pin 3 = b; Pin 4 = c; * Outputs: * Pin 19 = A0; Pin 18 = A1; Pin 17 = A2; Pin 16 = A3; Pin 15 ٤٧ = A4; Decoder Pin 14 = A5; Pin 13 = A6; Pin 12 = A7; * DECLERATION FIELD INPUT = [c,b,a]; FIELD OUTPUT = [A7,A6,A5,A4,A3,A2,A1,A0]; * CODE TABLE INPUT => OUTPUT { 'b'000=>'b' ; 'b'001=>'b' ; 'b'010=>'b' ; 'b'011=>'b' ; 'b'100=>'b' ; 'b'101=>'b' ; 'b'110=>'b' ; 'b'111=>'b' ; { Security System Security system installed in a house; consists of Door sensor (D) : 0 = closed; 1= opened Light sensor (L): 0 = night; 1 = day Windows (w) : 0: closed; 1 = opened Alarm (A) : 0 = no alarm; 1 = Alarm System is designed to protect home at day and night, that if door is opened during day light; alarm will not be activated, if door is open during night; alarm will be activated. If window is opened during day light; alarm will not be activated, if door is open during night; alarm will be activated. ٤٨

25 L D W A A = L D W+L DW +L DW ٤٩ Name SecuritySystem; Partno 0; Revision 0; Date 9/12/18; Designer AFee; Company ACU; Location None; Assembly None; Device g16v8a; * code A = (!L&!D&W) # (!L&D&!W) # (!L&D&W); * Inputs: Pin 2 = L ; Pin 3 = D ; Pin 4 = W; * Outputs: Pin 19 = A; x ٥٠

26 Counter 2 Q1(n) Q0(n) Q1(n+1) Q0(n+1) Q0(n+1)= Q1(n) & Q0(n) or Q1(n) & Q0(n) Q1(n+1)=Q1(n) & Q0(n) or Q1(n) & Q0(n) ٥١ Name Counter2; Partno 0; Revision 0; Date 9/12/18; Designer AFee; Company ACU; Location None; Assembly None; Device g16v8a; * code q0.d =! reset & (! q0 &!q1 #!q0 & q1 ); q1.d =! reset & (! q0 & q1 # q0 &!q1 ); * Inputs: Pin 1 = clock ; Pin 2 = reset ; Pin 11 =!oe; * Outputs: Pin 19 = q0; Pin 18 = q1; ٥٢

27 Name Counter2'; Partno 0; Revision 0; Date 9/12/18; Designer AFee; Company ACU; Location None; Assembly None; Device g16v8a; * Inputs: Pin 1 = clock ; Pin 2 = Reset; Pin 11 =!oe; * Outputs: Pin [18..19] = [Q1..0]; ٥٣ * Deceleration field count = [Q1..0]; $define S0 'b'00 $define S1 'b'01 $define S2 'b'10 $define S3 'b'11 * code Sequenced count { free running counter present S0 if!reset next S1; if Reset next S0; present S1 if!reset next S2; if Reset next S0; present S2 if!reset next S3; if Reset next S0; present S3 if!reset next S0; if Reset next S0; { Counter 3 Q2(n 1) Q1(n 1) Q0(n 1) Q2(n) Q1(n) Q0(n) qo.d =! reset & (!q2 &!q1 &!q0 #!q2 & q1 &!q0 # q2 &!q1 &!q0 # q2 & q1 &!q0); q1.d =! reset & (!q2 &!q1 & q0 #!q2 & q1 &!q0 # q2 &!q1 & q0 # q2 & q1 &!q0); q2.d =! reset & (!q2 & q1 & q0 # q2 &!q1 &!q0 # q2 &!q1 & q0 # q2 & q1 &!q0); ٥٤

28 Name Counter3; Partno 0; Revision 0; Date 9/12/18; Designer AFee; Company ACU; Location None; Assembly None; Device g16v8a; * Inputs: Pin 1 = clock ; Pin 2 = reset ; Pin 11 =!oe; * Outputs: Pin 19 = q0; Pin 18 = q1; Pin 17 = q2; ٥٥ * code qo.d =! reset & (!q2 &!q1 &!q0 #!q2 & q1 &!q0 # q2 &!q1 &!q0 # q2 & q1 &!q0); q1.d =! reset & (!q2 &!q1 & q0 #!q2 & q1 &!q0 # q2 &!q1 & q0 # q2 & q1 &!q0); q2.d =! reset & (!q2 & q1 & q0 # q2 &!q1 &!q0 # q2 &!q1 & q0 # q2 & q1 &!q0); Name Counter3; Partno 0; Revision 0; Date 9/12/18; Designer AFee; Company ACU; Location None; Assembly None; Device g16v8a; * Inputs: Pin 1 = clock ; Pin 2 = Reset ; Pin 11 =!oe; * Outputs: Pin [17..19] = [Q2..0]; * Deceleration ٥٦ field count = [Q2..0]; $define S0 'b'000 $define S1 'b'001 $define S2 'b'010 $define S3 'b'011 $define S4 'b'100 $define S5 'b'101 $define S6 'b'110 $define S7 'b'111 * code Sequenced count { free running counter present S0 if!reset next S1; if Reset next S0; present S1 if!reset next S2; if Reset next S0; present S2 if!reset next S3; if Reset next S0; present S3 if!reset next S4; if Reset next S0; present S4 if!reset next S5; if Reset next S0;

29 present S5 if!reset next S6; if Reset next S0; present S6 if!reset next S7; if Reset next S0; present S7 if!reset next S0; S0; { if Reset next ٥٧ Adder Name ٥٨ Adder4; Partno 0; Revision 0; Date 9/12/18; Designer Company Location Assembly Device * Inputs: AFee; ACU; None; None; g16v8a; Pin [2..5] = [X1..4]; Pin [6..9] = [Y1..4]; * Outputs: pin 15 = Carry; pin 12 = C3; pin 13 = C2; pin 14 = C1; pin 16 = Z4; pin 17 = Z3; pin 18 = Z2; pin 19 = Z1; pin 19 = Carry; pin 18 = C3; pin 17 = C2; pin 16 = C1;

30 pin 15 = Z4; pin 14 = Z3; pin 13 = Z2; pin 12 = Z1; Pin [12..15] = [Z1..4]; * Pin [16..18] = [C1..3]; * Pin 19 = Carry; * code function adder_slice(x, Y, Cin, Cout) { Cout = Cin & X Compute carry # Cin & Y # X & Y; adder_slice = Cin $ (X $ Y); Compute sum { Z1 = adder_slice(x1, Y1, 'h'0, C1); Initial carry = 'h'0 Z2 = adder_slice(x2, Y2, C1, C2); Z3 = adder_slice(x3, Y3, C2, C3); Z4 = adder_slice(x4, Y4, C3, Carry); Get final carry value ٥٩ Name Seven Segment Display Decoder Partno 0; Revision 0; Date 9/12/18; Designer Company Location Assembly Device ٦٠ 7SegmentsDecoder; AFee; ACU; None; None; g16v8a; * Inputs: pin [2..5] = [D0..3]; * Outputs: pin [19..13] =![a,b,c,d,e,f,g];

31 *Declarations field data = [D3..0]; field segment =[a,b,c,d,e,f,g]; $define ON 'b'1 $define OFF 'b'0 * code segment = 0 [ ON, ON, ON, ON, ON, ON, OFF ] & data :0 1 # [OFF, ON, ON, OFF, OFF, OFF, OFF] & data :1 2 # [ ON, ON, OFF, ON, ON, OFF, ON] & data :2 3 # [ ON, ON, ON, ON, OFF, OFF, ON] & data :3 4 # [OFF, ON, ON, OFF, OFF, ON, ON] & data :4 5 # [ ON, OFF, ON, ON, OFF, ON, ON] & data :5 6 # [ ON, OFF, ON, ON, ON, ON, ON] & data :6 7 # [ ON, ON, ON, OFF, OFF, OFF, ON] & data :7 8 # [ ON, ON, ON, ON, ON, ON, OFF ] & data :8 9 # [ ON, ON, ON, ON, OFF, ON, ON] & data :9 A # [ ON, ON, ON, OFF, ON, ON, ON] & data :A B # [OFF, OFF, ON, ON, ON, ON, ON] & data :B C # [ ON, OFF, OFF, ON, ON, ON, OFF ] & data :C D # [OFF, ON, ON, ON, ON, OFF, ON] & data :D E # [ ON, OFF, OFF, ON, ON, ON, ON] & data :E F ٦١ # [ ON, OFF, OFF, Dr. OFF Ahmed, ON ElShafee,, ON ACU, ON] : Spring & 2018, data CSE303 :F; Logic design II Thanks,.. ٦٢ Dr. Ahmed ElShafee, ACU : Spring 2018, CSE303 Logic design II