Midterm Exam Review. CS 2420 :: Fall 2016 Molly O'Neil

Size: px
Start display at page:

Download "Midterm Exam Review. CS 2420 :: Fall 2016 Molly O'Neil"

Transcription

1 Midterm Exam Review CS 2420 :: Fall 2016 Molly O'Neil

2 Midterm Exam Thursday, October 20 In class, pencil & paper exam Closed book, closed notes, no cell phones or calculators, clean desk 20% of your final grade 80 minutes to complete the exam Please bring a pencil and eraser! All writing will be done on exam paper that I'll hand out 2

3 Exam Format 100 points total 5 pages, each with 4 problems = 20 problems total (~4 minutes per) Each problem is worth 5 points -- regardless of difficulty Consider working on easy problems first! You must show work/reasoning to receive any credit! Each page has a different topic: 1: Numbers 2: Boolean Algebra & Gates 3: Canonical Forms / NAND Circuits 4: K-Maps & Minimization 5: CL Circuit Design / Structured Design Types of questions: Exercises very similar to homework problems......plus short-answer concept questions 3

4 Content Slides from lecture: Introduction, Motivation, & Background Numbers, Coding, & Arithmetic Binary Logic & Gates Boolean Algebra & Functions K-Maps & Minimization Combinational Circuits & Structured Logic Design Lecture slides: All homeworks (HW 1, HW 2, HW 3) NO HDLs/SystemVerilog! Nothing from lab! 4

5 Things You Should Know How to Do... (I) A. Numbers (1) Convert a hex # to octal via binary (2) Convert an octal # to hex via binary (3) Convert a fractional decimal # to binary (4) Convert a fractional binary, octal, or hex # to decimal (5) Describe 2's complement vs. 1's complement vs. signedmagnitude and their relative advantages/disadvantages (6) Represent a negative decimal # in 2's complement (7) Perform subtration on decimal #s using 2's complement encoding and binary arithmetic (must show work, including carries!) (8) Represent a decimal # in BCD 5

6 Things You Should Know How to Do... (II) B. Gates (1) Explain the operation (and/or draw a truth table) and know the symbols for AND, OR, NOT, NAND, NOR, XOR, and XNOR gates (2) Explain why NAND and NOR gates are universal (3) Draw a logic diagram from a Boolean expression (4) Construct a Boolean expression from a logic diagram C. Boolean Algebra (1) Construct a truth table from a Boolean expression (2) Demonstrate the validity of an identity via a truth table (3) Reduce a Boolean expression to a given # of literals using theorems & postulates (not K-Maps!) (4) Provide the complement of a function using DeMorgan's theorem 6

7 Things You Should Know How to Do... (III) D. Canonical Forms (1) Via a truth table, express a function in canonical SOP form (as an expression) or as a sum of minterms (2) Via a truth table, express a function in canonical POS form (as an expression) or as a product of maxterms (3) Convert between maxterm/minterm #s and Boolean expressions (4) Express a Boolean function in canonical SOP or POS form working directly from the expression, not via truth table (5) Describe the relationship between the minterms and maxterms of a function E. NAND Circuits (1) Use bubble-pushing/demorgan's equivalencies to express a function using only NAND gates 7

8 Things You Should Know How to Do... (IV) F. K-Maps (1) Simplify a 3-variable function (given as an expression, truth table, or sum-of-minterms) to a minimal 2-level SOP using a K-Map (2) Simplify a 4-variable function (given as an expression, truth table, or sum-of-minterms) to a minimal 2-level SOP using a K-Map (3) Using a K-Map, simplify a Boolean expression with don't-care conditions (4) Identify prime implicants and essential prime implicants in a K- Map G. Minimization (1) Further simplify a reduced 2-level SOP expression (derived from a K-Map) by identifying common factors (2) Further simplify a reduced 2-level SOP expression (derived form a K-Map) by identifying XOR/XNOR patterns 8

9 Things You Should Know How to Do... (V) H. Combinational Logic Circuit Design (1) Given a description of a CL circuit's operation, draw a truth table for the function(s) (2) Use K-Maps to derive a simplified implementation of a multi-output combinational circuit (3) Identify a static timing hazard in a K-map and give a fix (4) Draw a waveform demonstrating the output values of a circuit over time, given a series of input changes I. Structured Logic Design (1) Use a mux to implement a Boolean function by using some of its input variables as mux selects and placing factored functions of the remaining variables on the mux inputs (2) Implement a canonical SOP expression using a decoder (3) Describe the operation of a multiplexor and demultiplexor (4) Understand and describe the internals of a half-adder 9

10 How to Prepare Review the slides Understand all the concepts Quiz yourself Review the homework solutions (on TRACS) Re-do the homeworks (without consulting any notes) And re-check your answers against the solutions me with questions that come up while you study Sleep! Eat breakfast! 10

Chapter 2. Boolean Expressions:

Chapter 2. Boolean Expressions: Chapter 2 Boolean Expressions: A Boolean expression or a function is an expression which consists of binary variables joined by the Boolean connectives AND and OR along with NOT operation. Any Boolean

More information

KING FAHD UNIVERSITY OF PETROLEUM & MINERALS COMPUTER ENGINEERING DEPARTMENT

KING FAHD UNIVERSITY OF PETROLEUM & MINERALS COMPUTER ENGINEERING DEPARTMENT KING FAHD UNIVERSITY OF PETROLEUM & MINERALS COMPUTER ENGINEERING DEPARTMENT COE 202: Digital Logic Design Term 162 (Spring 2017) Instructor: Dr. Abdulaziz Barnawi Class time: U.T.R.: 11:00-11:50AM Class

More information

1. Mark the correct statement(s)

1. Mark the correct statement(s) 1. Mark the correct statement(s) 1.1 A theorem in Boolean algebra: a) Can easily be proved by e.g. logic induction b) Is a logical statement that is assumed to be true, c) Can be contradicted by another

More information

ENEL 353: Digital Circuits Midterm Examination

ENEL 353: Digital Circuits Midterm Examination NAME: SECTION: L01: Norm Bartley, ST 143 L02: Steve Norman, ST 145 When you start the test, please repeat your name and section, and add your U of C ID number at the bottom of the last page. Instructions:

More information

QUESTION BANK FOR TEST

QUESTION BANK FOR TEST CSCI 2121 Computer Organization and Assembly Language PRACTICE QUESTION BANK FOR TEST 1 Note: This represents a sample set. Please study all the topics from the lecture notes. Question 1. Multiple Choice

More information

ECE 2030B 1:00pm Computer Engineering Spring problems, 5 pages Exam Two 10 March 2010

ECE 2030B 1:00pm Computer Engineering Spring problems, 5 pages Exam Two 10 March 2010 Instructions: This is a closed book, closed note exam. Calculators are not permitted. If you have a question, raise your hand and I will come to you. Please work the exam in pencil and do not separate

More information

Gate-Level Minimization. BME208 Logic Circuits Yalçın İŞLER

Gate-Level Minimization. BME208 Logic Circuits Yalçın İŞLER Gate-Level Minimization BME28 Logic Circuits Yalçın İŞLER islerya@yahoo.com http://me.islerya.com Complexity of Digital Circuits Directly related to the complexity of the algebraic expression we use to

More information

Digital logic fundamentals. Question Bank. Unit I

Digital logic fundamentals. Question Bank. Unit I Digital logic fundamentals Question Bank Subject Name : Digital Logic Fundamentals Subject code: CA102T Staff Name: R.Roseline Unit I 1. What is Number system? 2. Define binary logic. 3. Show how negative

More information

CS8803: Advanced Digital Design for Embedded Hardware

CS8803: Advanced Digital Design for Embedded Hardware CS883: Advanced Digital Design for Embedded Hardware Lecture 2: Boolean Algebra, Gate Network, and Combinational Blocks Instructor: Sung Kyu Lim (limsk@ece.gatech.edu) Website: http://users.ece.gatech.edu/limsk/course/cs883

More information

Incompletely Specified Functions with Don t Cares 2-Level Transformation Review Boolean Cube Karnaugh-Map Representation and Methods Examples

Incompletely Specified Functions with Don t Cares 2-Level Transformation Review Boolean Cube Karnaugh-Map Representation and Methods Examples Lecture B: Logic Minimization Incompletely Specified Functions with Don t Cares 2-Level Transformation Review Boolean Cube Karnaugh-Map Representation and Methods Examples Incompletely specified functions

More information

Bawar Abid Abdalla. Assistant Lecturer Software Engineering Department Koya University

Bawar Abid Abdalla. Assistant Lecturer Software Engineering Department Koya University Logic Design First Stage Lecture No.6 Boolean Algebra Bawar Abid Abdalla Assistant Lecturer Software Engineering Department Koya University Outlines Boolean Operations Laws of Boolean Algebra Rules of

More information

Department of Electrical Engineering McGill University ECSE 221 Introduction to Computer Engineering Assignment 2 Combinational Logic

Department of Electrical Engineering McGill University ECSE 221 Introduction to Computer Engineering Assignment 2 Combinational Logic Department of Electrical Engineering McGill University ECSE 221 Introduction to Computer Engineering Assignment 2 Combinational Logic Question 1: Due October 19 th, 2009 A convenient shorthand for specifying

More information

Chapter 3. Gate-Level Minimization. Outlines

Chapter 3. Gate-Level Minimization. Outlines Chapter 3 Gate-Level Minimization Introduction The Map Method Four-Variable Map Five-Variable Map Outlines Product of Sums Simplification Don t-care Conditions NAND and NOR Implementation Other Two-Level

More information

EECS 270 Midterm Exam

EECS 270 Midterm Exam EECS 270 Midterm Exam Fall 2009 Name: unique name: Sign the honor code: I have neither given nor received aid on this exam nor observed anyone else doing so. Scores: NOTES: Problem # Points 1 /11 2 /4

More information

Student Number: UTORid: Question 0. [1 mark] Read and follow all instructions on this page, and fill in all fields.

Student Number: UTORid: Question 0. [1 mark] Read and follow all instructions on this page, and fill in all fields. CSC 258H1 Y 2016 Midterm Test Duration 1 hour and 50 minutes Aids allowed: none Student Number: UTORid: Last Name: First Name: Question 0. [1 mark] Read and follow all instructions on this page, and fill

More information

Question Total Possible Test Score Total 100

Question Total Possible Test Score Total 100 Computer Engineering 2210 Final Name 11 problems, 100 points. Closed books, closed notes, no calculators. You would be wise to read all problems before beginning, note point values and difficulty of problems,

More information

Chapter 2: Combinational Systems

Chapter 2: Combinational Systems Uchechukwu Ofoegbu Chapter 2: Combinational Systems Temple University Adapted from Alan Marcovitz s Introduction to Logic and Computer Design Riddle Four switches can be turned on or off. One is the switch

More information

Chapter Three. Digital Components

Chapter Three. Digital Components Chapter Three 3.1. Combinational Circuit A combinational circuit is a connected arrangement of logic gates with a set of inputs and outputs. The binary values of the outputs are a function of the binary

More information

ENEL Digital Circuits Midterm Examination

ENEL Digital Circuits Midterm Examination Name: Lecture Section: L0 N. artley :-:50 L02 S. Norman, 2:-2:50 ENEL 353 - igital ircuits Midterm Examination Wednesday, October 30, 203 Instructions: Time allowed is 90 minutes. In order to minimize

More information

ECE 2020B Fundamentals of Digital Design Spring problems, 6 pages Exam Two 26 February 2014

ECE 2020B Fundamentals of Digital Design Spring problems, 6 pages Exam Two 26 February 2014 Instructions: This is a closed book, closed note exam. Calculators are not permitted. If you have a question, raise your hand and I will come to you. Please work the exam in pencil and do not separate

More information

ECE 2030D Computer Engineering Spring problems, 5 pages Exam Two 8 March 2012

ECE 2030D Computer Engineering Spring problems, 5 pages Exam Two 8 March 2012 Instructions: This is a closed book, closed note exam. Calculators are not permitted. If you have a question, raise your hand and I will come to you. Please work the exam in pencil and do not separate

More information

Gate Level Minimization Map Method

Gate Level Minimization Map Method Gate Level Minimization Map Method Complexity of hardware implementation is directly related to the complexity of the algebraic expression Truth table representation of a function is unique Algebraically

More information

Logic Design: Part 2

Logic Design: Part 2 Orange Coast College Business Division Computer Science Department CS 6- Computer Architecture Logic Design: Part 2 Where are we? Number systems Decimal Binary (and related Octal and Hexadecimal) Binary

More information

LECTURE 4. Logic Design

LECTURE 4. Logic Design LECTURE 4 Logic Design LOGIC DESIGN The language of the machine is binary that is, sequences of 1 s and 0 s. But why? At the hardware level, computers are streams of signals. These signals only have two

More information

Computer Organization and Levels of Abstraction

Computer Organization and Levels of Abstraction Computer Organization and Levels of Abstraction Announcements PS8 Due today PS9 Due July 22 Sound Lab tonight bring machines and headphones! Binary Search Today Review of binary floating point notation

More information

2.6 BOOLEAN FUNCTIONS

2.6 BOOLEAN FUNCTIONS 2.6 BOOLEAN FUNCTIONS Binary variables have two values, either 0 or 1. A Boolean function is an expression formed with binary variables, the two binary operators AND and OR, one unary operator NOT, parentheses

More information

Department of Electrical and Computer Engineering University of Wisconsin - Madison. ECE/CS 352 Digital System Fundamentals.

Department of Electrical and Computer Engineering University of Wisconsin - Madison. ECE/CS 352 Digital System Fundamentals. Department of Electrical and Computer Engineering University of Wisconsin - Madison ECE/C 352 Digital ystem Fundamentals Quiz #2 Thursday, March 7, 22, 7:15--8:3PM 1. (15 points) (a) (5 points) NAND, NOR

More information

Review. EECS Components and Design Techniques for Digital Systems. Lec 05 Boolean Logic 9/4-04. Seq. Circuit Behavior. Outline.

Review. EECS Components and Design Techniques for Digital Systems. Lec 05 Boolean Logic 9/4-04. Seq. Circuit Behavior. Outline. Review EECS 150 - Components and Design Techniques for Digital Systems Lec 05 Boolean Logic 94-04 David Culler Electrical Engineering and Computer Sciences University of California, Berkeley Design flow

More information

2008 The McGraw-Hill Companies, Inc. All rights reserved.

2008 The McGraw-Hill Companies, Inc. All rights reserved. 28 The McGraw-Hill Companies, Inc. All rights reserved. 28 The McGraw-Hill Companies, Inc. All rights reserved. All or Nothing Gate Boolean Expression: A B = Y Truth Table (ee next slide) or AB = Y 28

More information

Announcements. Chapter 2 - Part 1 1

Announcements. Chapter 2 - Part 1 1 Announcements If you haven t shown the grader your proof of prerequisite, please do so by 11:59 pm on 09/05/2018 (Wednesday). I will drop students that do not show us the prerequisite proof after this

More information

LAB #1 BASIC DIGITAL CIRCUIT

LAB #1 BASIC DIGITAL CIRCUIT LAB #1 BASIC DIGITAL CIRCUIT OBJECTIVES 1. To study the operation of basic logic gates. 2. To build a logic circuit from Boolean expressions. 3. To introduce some basic concepts and laboratory techniques

More information

Code No: 07A3EC03 Set No. 1

Code No: 07A3EC03 Set No. 1 Code No: 07A3EC03 Set No. 1 II B.Tech I Semester Regular Examinations, November 2008 SWITCHING THEORY AND LOGIC DESIGN ( Common to Electrical & Electronic Engineering, Electronics & Instrumentation Engineering,

More information

Code No: R Set No. 1

Code No: R Set No. 1 Code No: R059210504 Set No. 1 II B.Tech I Semester Supplementary Examinations, February 2007 DIGITAL LOGIC DESIGN ( Common to Computer Science & Engineering, Information Technology and Computer Science

More information

DIGITAL ELECTRONICS. P41l 3 HOURS

DIGITAL ELECTRONICS. P41l 3 HOURS UNIVERSITY OF SWAZILAND FACUL TY OF SCIENCE AND ENGINEERING DEPARTMENT OF PHYSICS MAIN EXAMINATION 2015/16 TITLE OF PAPER: COURSE NUMBER: TIME ALLOWED: INSTRUCTIONS: DIGITAL ELECTRONICS P41l 3 HOURS ANSWER

More information

2/8/2017. SOP Form Gives Good Performance. ECE 120: Introduction to Computing. K-Maps Can Identify Single-Gate Functions

2/8/2017. SOP Form Gives Good Performance. ECE 120: Introduction to Computing. K-Maps Can Identify Single-Gate Functions University of Illinois at Urbana-Champaign Dept. of Electrical and Computer Engineering ECE 120: Introduction to Computing Two-Level Logic SOP Form Gives Good Performance s you know, one can use a K-map

More information

Midterm Exam #2 Review. CS 2308 :: Spring 2016 Molly O'Neil

Midterm Exam #2 Review. CS 2308 :: Spring 2016 Molly O'Neil Midterm Exam #2 Review CS 2308 :: Spring 2016 Molly O'Neil Midterm Exam #2 Wednesday, April 13 In class, pencil & paper exam Closed book, closed notes, no cell phones or calculators, clean desk 20% of

More information

Gate-Level Minimization. section instructor: Ufuk Çelikcan

Gate-Level Minimization. section instructor: Ufuk Çelikcan Gate-Level Minimization section instructor: Ufuk Çelikcan Compleity of Digital Circuits Directly related to the compleity of the algebraic epression we use to build the circuit. Truth table may lead to

More information

Code No: R Set No. 1

Code No: R Set No. 1 Code No: R059210504 Set No. 1 II B.Tech I Semester Regular Examinations, November 2006 DIGITAL LOGIC DESIGN ( Common to Computer Science & Engineering, Information Technology and Computer Science & Systems

More information

COLLEGE OF ENGINEERING DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING QUESTION BANK SUBJECT CODE & NAME: EC 1312 DIGITAL LOGIC CIRCUITS UNIT I

COLLEGE OF ENGINEERING DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING QUESTION BANK SUBJECT CODE & NAME: EC 1312 DIGITAL LOGIC CIRCUITS UNIT I KINGS COLLEGE OF ENGINEERING DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING QUESTION BANK SUBJECT CODE & NAME: EC 1312 DIGITAL LOGIC CIRCUITS YEAR / SEM: III / V UNIT I NUMBER SYSTEM & BOOLEAN ALGEBRA

More information

LSN 4 Boolean Algebra & Logic Simplification. ECT 224 Digital Computer Fundamentals. Department of Engineering Technology

LSN 4 Boolean Algebra & Logic Simplification. ECT 224 Digital Computer Fundamentals. Department of Engineering Technology LSN 4 Boolean Algebra & Logic Simplification Department of Engineering Technology LSN 4 Key Terms Variable: a symbol used to represent a logic quantity Compliment: the inverse of a variable Literal: a

More information

Experiment 3: Logic Simplification

Experiment 3: Logic Simplification Module: Logic Design Name:... University no:.. Group no:. Lab Partner Name: Mr. Mohamed El-Saied Experiment : Logic Simplification Objective: How to implement and verify the operation of the logical functions

More information

B.Tech II Year I Semester (R13) Regular Examinations December 2014 DIGITAL LOGIC DESIGN

B.Tech II Year I Semester (R13) Regular Examinations December 2014 DIGITAL LOGIC DESIGN B.Tech II Year I Semester () Regular Examinations December 2014 (Common to IT and CSE) (a) If 1010 2 + 10 2 = X 10, then X is ----- Write the first 9 decimal digits in base 3. (c) What is meant by don

More information

Experiment 4 Boolean Functions Implementation

Experiment 4 Boolean Functions Implementation Experiment 4 Boolean Functions Implementation Introduction: Generally you will find that the basic logic functions AND, OR, NAND, NOR, and NOT are not sufficient to implement complex digital logic functions.

More information

SIR C.R.REDDY COLLEGE OF ENGINEERING, ELURU DEPARTMENT OF INFORMATION TECHNOLOGY LESSON PLAN

SIR C.R.REDDY COLLEGE OF ENGINEERING, ELURU DEPARTMENT OF INFORMATION TECHNOLOGY LESSON PLAN SIR C.R.REDDY COLLEGE OF ENGINEERING, ELURU DEPARTMENT OF INFORMATION TECHNOLOGY LESSON PLAN SUBJECT: CSE 2.1.6 DIGITAL LOGIC DESIGN CLASS: 2/4 B.Tech., I SEMESTER, A.Y.2017-18 INSTRUCTOR: Sri A.M.K.KANNA

More information

TWO-LEVEL COMBINATIONAL LOGIC

TWO-LEVEL COMBINATIONAL LOGIC TWO-LEVEL COMBINATIONAL LOGIC OVERVIEW Canonical forms To-level simplification Boolean cubes Karnaugh maps Quine-McClusky (Tabulation) Method Don't care terms Canonical and Standard Forms Minterms and

More information

Computer Organization and Levels of Abstraction

Computer Organization and Levels of Abstraction Computer Organization and Levels of Abstraction Announcements Today: PS 7 Lab 8: Sound Lab tonight bring machines and headphones! PA 7 Tomorrow: Lab 9 Friday: PS8 Today (Short) Floating point review Boolean

More information

R10. II B. Tech I Semester, Supplementary Examinations, May

R10. II B. Tech I Semester, Supplementary Examinations, May SET - 1 1. a) Convert the following decimal numbers into an equivalent binary numbers. i) 53.625 ii) 4097.188 iii) 167 iv) 0.4475 b) Add the following numbers using 2 s complement method. i) -48 and +31

More information

Bawar Abid Abdalla. Assistant Lecturer Software Engineering Department Koya University

Bawar Abid Abdalla. Assistant Lecturer Software Engineering Department Koya University Logic Design First Stage Lecture No.5 Boolean Algebra Bawar Abid Abdalla Assistant Lecturer Software Engineering Department Koya University Boolean Operations Laws of Boolean Algebra Rules of Boolean Algebra

More information

Chapter 6. Logic Design Optimization Chapter 6

Chapter 6. Logic Design Optimization Chapter 6 Chapter 6 Logic Design Optimization Chapter 6 Optimization The second part of our design process. Optimization criteria: Performance Size Power Two-level Optimization Manipulating a function until it is

More information

II/IV B.Tech (Regular/Supplementary) DEGREE EXAMINATION. Answer ONE question from each unit.

II/IV B.Tech (Regular/Supplementary) DEGREE EXAMINATION. Answer ONE question from each unit. Hall Ticket Number: 14CS IT303 November, 2017 Third Semester Time: Three Hours Answer Question No.1 compulsorily. II/IV B.Tech (Regular/Supplementary) DEGREE EXAMINATION Common for CSE & IT Digital Logic

More information

Chapter 2. Boolean Algebra and Logic Gates

Chapter 2. Boolean Algebra and Logic Gates Chapter 2. Boolean Algebra and Logic Gates Tong In Oh 1 Basic Definitions 2 3 2.3 Axiomatic Definition of Boolean Algebra Boolean algebra: Algebraic structure defined by a set of elements, B, together

More information

Assignment (3-6) Boolean Algebra and Logic Simplification - General Questions

Assignment (3-6) Boolean Algebra and Logic Simplification - General Questions Assignment (3-6) Boolean Algebra and Logic Simplification - General Questions 1. Convert the following SOP expression to an equivalent POS expression. 2. Determine the values of A, B, C, and D that make

More information

ECE 331: N0. Professor Andrew Mason Michigan State University. Opening Remarks

ECE 331: N0. Professor Andrew Mason Michigan State University. Opening Remarks ECE 331: N0 ECE230 Review Professor Andrew Mason Michigan State University Spring 2013 1.1 Announcements Opening Remarks HW1 due next Mon Labs begin in week 4 No class next-next Mon MLK Day ECE230 Review

More information

EECS 140/141 Introduction to Digital Logic Design Fall Semester 2016 Exam #1 Date: 3 October 2016

EECS 140/141 Introduction to Digital Logic Design Fall Semester 2016 Exam #1 Date: 3 October 2016 EECS 4/4 Introduction to Digital Logic Design Fall Semester 26 Exam # Date: 3 October 26 NAME: KUID: General Instructions. This exam is closed-book. You are allowed a non-communicating calculator and one

More information

Written exam for IE1204/5 Digital Design Thursday 29/

Written exam for IE1204/5 Digital Design Thursday 29/ Written exam for IE1204/5 Digital Design Thursday 29/10 2015 9.00-13.00 General Information Examiner: Ingo Sander. Teacher: William Sandqvist phone 08-7904487 Exam text does not have to be returned when

More information

Lecture 4: Implementation AND, OR, NOT Gates and Complement

Lecture 4: Implementation AND, OR, NOT Gates and Complement EE210: Switching Systems Lecture 4: Implementation AND, OR, NOT Gates and Complement Prof. YingLi Tian Feb. 13, 2018 Department of Electrical Engineering The City College of New York The City University

More information

CprE 281: Digital Logic

CprE 281: Digital Logic CprE 28: Digital Logic Instructor: Alexander Stoytchev http://www.ece.iastate.edu/~alexs/classes/ Minimization CprE 28: Digital Logic Iowa State University, Ames, IA Copyright Alexander Stoytchev Administrative

More information

Get Free notes at Module-I One s Complement: Complement all the bits.i.e. makes all 1s as 0s and all 0s as 1s Two s Complement: One s complement+1 SIGNED BINARY NUMBERS Positive integers (including zero)

More information

SUBJECT CODE: IT T35 DIGITAL SYSTEM DESIGN YEAR / SEM : 2 / 3

SUBJECT CODE: IT T35 DIGITAL SYSTEM DESIGN YEAR / SEM : 2 / 3 UNIT - I PART A (2 Marks) 1. Using Demorgan s theorem convert the following Boolean expression to an equivalent expression that has only OR and complement operations. Show the function can be implemented

More information

ELCT201: DIGITAL LOGIC DESIGN

ELCT201: DIGITAL LOGIC DESIGN ELCT201: DIGITAL LOGIC DESIGN Dr. Eng. Haitham Omran, haitham.omran@guc.edu.eg Dr. Eng. Wassim Alexan, wassim.joseph@guc.edu.eg Lecture 3 Following the slides of Dr. Ahmed H. Madian ذو الحجة 1438 ه Winter

More information

Boolean Algebra and Logic Gates

Boolean Algebra and Logic Gates Boolean Algebra and Logic Gates Binary logic is used in all of today's digital computers and devices Cost of the circuits is an important factor Finding simpler and cheaper but equivalent circuits can

More information

Objectives: 1. Design procedure. 2. Fundamental circuits. 1. Design procedure

Objectives: 1. Design procedure. 2. Fundamental circuits. 1. Design procedure Objectives: 1. Design procedure. 2. undamental circuits. 1. Design procedure Design procedure has five steps: o Specification. o ormulation. o Optimization. o Technology mapping. o Verification. Specification:

More information

GATE CSE. GATE CSE Book. November 2016 GATE CSE

GATE CSE. GATE CSE Book. November 2016 GATE CSE GATE CSE GATE CSE Book November 2016 GATE CSE Preface This book is made thanks to the effort of GATE CSE members and Praneeth who made most of the latex notes for GATE CSE. Remaining work of completing

More information

Specifying logic functions

Specifying logic functions CSE4: Components and Design Techniques for Digital Systems Specifying logic functions Instructor: Mohsen Imani Slides from: Prof.Tajana Simunic and Dr.Pietro Mercati We have seen various concepts: Last

More information

Standard Forms of Expression. Minterms and Maxterms

Standard Forms of Expression. Minterms and Maxterms Standard Forms of Expression Minterms and Maxterms Standard forms of expressions We can write expressions in many ways, but some ways are more useful than others A sum of products (SOP) expression contains:

More information

MGU-BCA-205- Second Sem- Core VI- Fundamentals of Digital Systems- MCQ s. 2. Why the decimal number system is also called as positional number system?

MGU-BCA-205- Second Sem- Core VI- Fundamentals of Digital Systems- MCQ s. 2. Why the decimal number system is also called as positional number system? MGU-BCA-205- Second Sem- Core VI- Fundamentals of Digital Systems- MCQ s Unit-1 Number Systems 1. What does a decimal number represents? A. Quality B. Quantity C. Position D. None of the above 2. Why the

More information

Final Examination (Open Katz, asynchronous & test notes only, Calculators OK, 3 hours)

Final Examination (Open Katz, asynchronous & test notes only, Calculators OK, 3 hours) Your Name: UNIVERSITY OF CALIFORNIA AT BERKELEY BERKELEY DAVIS IRVINE LOS ANGELES RIVERSIDE SAN DIEGO SAN FRANCISCO Department of Electrical Engineering and Computer Sciences SANTA BARBARA SANTA CRUZ CS

More information

SWITCHING THEORY AND LOGIC CIRCUITS

SWITCHING THEORY AND LOGIC CIRCUITS SWITCHING THEORY AND LOGIC CIRCUITS COURSE OBJECTIVES. To understand the concepts and techniques associated with the number systems and codes 2. To understand the simplification methods (Boolean algebra

More information

1. Fill in the entries in the truth table below to specify the logic function described by the expression, AB AC A B C Z

1. Fill in the entries in the truth table below to specify the logic function described by the expression, AB AC A B C Z CS W3827 05S Solutions for Midterm Exam 3/3/05. Fill in the entries in the truth table below to specify the logic function described by the expression, AB AC A B C Z 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2.

More information

EECS150 Homework 2 Solutions Fall ) CLD2 problem 2.2. Page 1 of 15

EECS150 Homework 2 Solutions Fall ) CLD2 problem 2.2. Page 1 of 15 1.) CLD2 problem 2.2 We are allowed to use AND gates, OR gates, and inverters. Note that all of the Boolean expression are already conveniently expressed in terms of AND's, OR's, and inversions. Thus,

More information

Injntu.com Injntu.com Injntu.com R16

Injntu.com Injntu.com Injntu.com R16 1. a) What are the three methods of obtaining the 2 s complement of a given binary (3M) number? b) What do you mean by K-map? Name it advantages and disadvantages. (3M) c) Distinguish between a half-adder

More information

Slide Set 5. for ENEL 353 Fall Steve Norman, PhD, PEng. Electrical & Computer Engineering Schulich School of Engineering University of Calgary

Slide Set 5. for ENEL 353 Fall Steve Norman, PhD, PEng. Electrical & Computer Engineering Schulich School of Engineering University of Calgary Slide Set 5 for ENEL 353 Fall 207 Steve Norman, PhD, PEng Electrical & Computer Engineering Schulich School of Engineering University of Calgary Fall Term, 207 SN s ENEL 353 Fall 207 Slide Set 5 slide

More information

Code No: R Set No. 1

Code No: R Set No. 1 Code No: R059210504 Set No. 1 II B.Tech I Semester Regular Examinations, November 2007 DIGITAL LOGIC DESIGN ( Common to Computer Science & Engineering, Information Technology and Computer Science & Systems

More information

ELCT201: DIGITAL LOGIC DESIGN

ELCT201: DIGITAL LOGIC DESIGN ELCT201: DIGITAL LOGIC DESIGN Dr. Eng. Haitham Omran, haitham.omran@guc.edu.eg Dr. Eng. Wassim Alexan, wassim.joseph@guc.edu.eg Lecture 3 Following the slides of Dr. Ahmed H. Madian محرم 1439 ه Winter

More information

IT 201 Digital System Design Module II Notes

IT 201 Digital System Design Module II Notes IT 201 Digital System Design Module II Notes BOOLEAN OPERATIONS AND EXPRESSIONS Variable, complement, and literal are terms used in Boolean algebra. A variable is a symbol used to represent a logical quantity.

More information

Purdue IMPACT 2015 Edition by D. G. Meyer. Introduction to Digital System Design. Module 2 Combinational Logic Circuits

Purdue IMPACT 2015 Edition by D. G. Meyer. Introduction to Digital System Design. Module 2 Combinational Logic Circuits Purdue IMPACT 25 Edition by D. G. Meyer Introduction to Digital System Design Module 2 Combinational Logic Circuits Glossary of Common Terms DISCRETE LOGIC a circuit constructed using small-scale integrated

More information

To write Boolean functions in their standard Min and Max terms format. To simplify Boolean expressions using Karnaugh Map.

To write Boolean functions in their standard Min and Max terms format. To simplify Boolean expressions using Karnaugh Map. 3.1 Objectives To write Boolean functions in their standard Min and Max terms format. To simplify Boolean expressions using. 3.2 Sum of Products & Product of Sums Any Boolean expression can be simplified

More information

CDS Computing for Scientists. Midterm Exam Review. Midterm Exam on October 22, 2013

CDS Computing for Scientists. Midterm Exam Review. Midterm Exam on October 22, 2013 CDS 130-001 Computing for Scientists Midterm Exam Review Midterm Exam on October 22, 2013 1. Review Sheet 2. Sample Midterm Exam CDS 130-001 Computing for Scientists Midterm Exam - Review Sheet The following

More information

DHANALAKSHMI SRINIVASAN COLLEGE OF ENGINEERING AND TECHNOLOGY

DHANALAKSHMI SRINIVASAN COLLEGE OF ENGINEERING AND TECHNOLOGY DHANALAKSHMI SRINIVASAN COLLEGE OF ENGINEERING AND TECHNOLOGY Dept/Sem: II CSE/03 DEPARTMENT OF ECE CS8351 DIGITAL PRINCIPLES AND SYSTEM DESIGN UNIT I BOOLEAN ALGEBRA AND LOGIC GATES PART A 1. How many

More information

Department of Electrical and Computer Engineering University of Wisconsin - Madison. ECE/CS 352 Digital System Fundamentals.

Department of Electrical and Computer Engineering University of Wisconsin - Madison. ECE/CS 352 Digital System Fundamentals. Last (family) name: First (given) name: Student I.D. #: Circle section: Lipasti Kim Department of Electrical and Computer Engineering University of isconsin - Madison ECE/CS 352 Digital System Fundamentals

More information

SIDDHARTH GROUP OF INSTITUTIONS :: PUTTUR Siddharth Nagar, Narayanavanam Road QUESTION BANK (DESCRIPTIVE)

SIDDHARTH GROUP OF INSTITUTIONS :: PUTTUR Siddharth Nagar, Narayanavanam Road QUESTION BANK (DESCRIPTIVE) SIDDHARTH GROUP OF INSTITUTIONS :: PUTTUR Siddharth Nagar, Narayanavanam Road 517583 QUESTION BANK (DESCRIPTIVE) Subject with Code : STLD(16EC402) Year & Sem: II-B.Tech & I-Sem Course & Branch: B.Tech

More information

Karnaugh Map (K-Map) Karnaugh Map. Karnaugh Map Examples. Ch. 2.4 Ch. 2.5 Simplification using K-map

Karnaugh Map (K-Map) Karnaugh Map. Karnaugh Map Examples. Ch. 2.4 Ch. 2.5 Simplification using K-map Karnaugh Map (K-Map) Ch. 2.4 Ch. 2.5 Simplification using K-map A graphical map method to simplify Boolean function up to 6 variables A diagram made up of squares Each square represents one minterm (or

More information

Chap-2 Boolean Algebra

Chap-2 Boolean Algebra Chap-2 Boolean Algebra Contents: My name Outline: My position, contact Basic information theorem and postulate of Boolean Algebra. or project description Boolean Algebra. Canonical and Standard form. Digital

More information

ECE 2020B Fundamentals of Digital Design Spring problems, 6 pages Exam Two Solutions 26 February 2014

ECE 2020B Fundamentals of Digital Design Spring problems, 6 pages Exam Two Solutions 26 February 2014 Problem 1 (4 parts, 21 points) Encoders and Pass Gates Part A (8 points) Suppose the circuit below has the following input priority: I 1 > I 3 > I 0 > I 2. Complete the truth table by filling in the input

More information

INSTITUTE OF AERONAUTICAL ENGINEERING (Autonomous) Dundigal, Hyderabad

INSTITUTE OF AERONAUTICAL ENGINEERING (Autonomous) Dundigal, Hyderabad INSTITUTE OF AERONAUTICAL ENGINEERING (Autonomous) Dundigal, Hyderabad - 500043 Course Name : DIGITAL LOGIC DESISN Course Code : AEC020 Class : B Tech III Semester Branch : CSE Academic Year : 2018 2019

More information

ECE 241F Digital Systems

ECE 241F Digital Systems ECE 241F Digital Systems Fall 2016 J. Anderson, P. Chow Basic Information Instructors and Lecture Information Section L101 L102 L103 Instructor Jason Anderson Paul Chow Jason Anderson Office EA 314 EA

More information

Lecture 5. Chapter 2: Sections 4-7

Lecture 5. Chapter 2: Sections 4-7 Lecture 5 Chapter 2: Sections 4-7 Outline Boolean Functions What are Canonical Forms? Minterms and Maxterms Index Representation of Minterms and Maxterms Sum-of-Minterm (SOM) Representations Product-of-Maxterm

More information

Class Subject Code Subject Prepared By Lesson Plan for Time: Lesson. No 1.CONTENT LIST: Introduction to UnitI 2. SKILLS ADDRESSED: Listening I year, 02 sem CS6201 Digital Principles & System Design S.Seedhanadevi

More information

UNIT-4 BOOLEAN LOGIC. NOT Operator Operates on single variable. It gives the complement value of variable.

UNIT-4 BOOLEAN LOGIC. NOT Operator Operates on single variable. It gives the complement value of variable. UNIT-4 BOOLEAN LOGIC Boolean algebra is an algebra that deals with Boolean values((true and FALSE). Everyday we have to make logic decisions: Should I carry the book or not?, Should I watch TV or not?

More information

CONTENTS CHAPTER 1: NUMBER SYSTEM. Foreword...(vii) Preface... (ix) Acknowledgement... (xi) About the Author...(xxiii)

CONTENTS CHAPTER 1: NUMBER SYSTEM. Foreword...(vii) Preface... (ix) Acknowledgement... (xi) About the Author...(xxiii) CONTENTS Foreword...(vii) Preface... (ix) Acknowledgement... (xi) About the Author...(xxiii) CHAPTER 1: NUMBER SYSTEM 1.1 Digital Electronics... 1 1.1.1 Introduction... 1 1.1.2 Advantages of Digital Systems...

More information

NH 67, Karur Trichy Highways, Puliyur C.F, Karur District DEPARTMENT OF INFORMATION TECHNOLOGY CS 2202 DIGITAL PRINCIPLES AND SYSTEM DESIGN

NH 67, Karur Trichy Highways, Puliyur C.F, Karur District DEPARTMENT OF INFORMATION TECHNOLOGY CS 2202 DIGITAL PRINCIPLES AND SYSTEM DESIGN NH 67, Karur Trichy Highways, Puliyur C.F, 639 114 Karur District DEPARTMENT OF INFORMATION TECHNOLOGY CS 2202 DIGITAL PRINCIPLES AND SYSTEM DESIGN UNIT 1 BOOLEAN ALGEBRA AND LOGIC GATES Review of binary

More information

UPY14602-DIGITAL ELECTRONICS AND MICROPROCESSORS Lesson Plan

UPY14602-DIGITAL ELECTRONICS AND MICROPROCESSORS Lesson Plan UPY14602-DIGITAL ELECTRONICS AND MICROPROCESSORS Lesson Plan UNIT I - NUMBER SYSTEMS AND LOGIC GATES Introduction to decimal- Binary- Octal- Hexadecimal number systems-inter conversions-bcd code- Excess

More information

UNCA CSCI 255 Exam 1 Spring February, This is a closed book and closed notes exam. It is to be turned in by 1:45 PM.

UNCA CSCI 255 Exam 1 Spring February, This is a closed book and closed notes exam. It is to be turned in by 1:45 PM. UNCA CSCI 255 Exam 1 Spring 2017 27 February, 2017 This is a closed book and closed notes exam. It is to be turned in by 1:45 PM. Communication with anyone other than the instructor is not allowed during

More information

Simplification of Boolean Functions

Simplification of Boolean Functions COM111 Introduction to Computer Engineering (Fall 2006-2007) NOTES 5 -- page 1 of 5 Introduction Simplification of Boolean Functions You already know one method for simplifying Boolean expressions: Boolean

More information

Chapter 2 Combinational Logic Circuits

Chapter 2 Combinational Logic Circuits Logic and Computer Design Fundamentals Chapter 2 Combinational Logic Circuits Part 2 Circuit Optimization Overview Part Gate Circuits and Boolean Equations Binary Logic and Gates Boolean Algebra Standard

More information

Spring 2010 CPE231 Digital Logic Section 1 Quiz 1-A. Convert the following numbers from the given base to the other three bases listed in the table:

Spring 2010 CPE231 Digital Logic Section 1 Quiz 1-A. Convert the following numbers from the given base to the other three bases listed in the table: Section 1 Quiz 1-A Convert the following numbers from the given base to the other three bases listed in the table: Decimal Binary Hexadecimal 1377.140625 10101100001.001001 561.24 454.3125 111000110.0101

More information

Summary. Boolean Addition

Summary. Boolean Addition Summary Boolean Addition In Boolean algebra, a variable is a symbol used to represent an action, a condition, or data. A single variable can only have a value of or 0. The complement represents the inverse

More information

INSTITUTE OF AERONAUTICAL ENGINEERING (Autonomous) Dundigal, Hyderabad

INSTITUTE OF AERONAUTICAL ENGINEERING (Autonomous) Dundigal, Hyderabad INSTITUTE OF AERONAUTICAL ENGINEERING (Autonomous) Dundigal, Hyderabad - 500 043 COMPUTER SCIENCE AND ENGINEERING TUTORIAL QUESTION BANK Name : DIGITAL LOGIC DESISN Code : AEC020 Class : B Tech III Semester

More information

VALLIAMMAI ENGINEERING COLLEGE. SRM Nagar, Kattankulathur DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING EC6302 DIGITAL ELECTRONICS

VALLIAMMAI ENGINEERING COLLEGE. SRM Nagar, Kattankulathur DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING EC6302 DIGITAL ELECTRONICS VALLIAMMAI ENGINEERING COLLEGE SRM Nagar, Kattankulathur-603 203 DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING EC6302 DIGITAL ELECTRONICS YEAR / SEMESTER: II / III ACADEMIC YEAR: 2015-2016 (ODD

More information

Gate Level Minimization

Gate Level Minimization Gate Level Minimization By Dr. M. Hebaishy Digital Logic Design Ch- Simplifying Boolean Equations Example : Y = AB + AB Example 2: = B (A + A) T8 = B () T5 = B T Y = A(AB + ABC) = A (AB ( + C ) ) T8 =

More information