Beyond Offloading Programming Models for the Intel Xeon Phi Coprocessor. Michael Hebenstreit, Senior Cluster Architect, Intel SFTS001

Transcription

1 Beyond Offloading Programming Models for the Intel Xeon Phi Coprocessor Michael Hebenstreit, Senior Cluster Architect, Intel SFTS001

2 Agenda Overview Automatic offloading Offloading by pragmas and keywords Native application Cluster and MPI support The PDF for this Session presentation is available from our Technical Session Catalog at the end of the day at: intel.com/go/idfsessions URL is on top of Session Agenda Pages in Pocket Guide 2

3 Agenda Overview Automatic offloading Offloading by pragmas and keywords Native application Cluster and MPI support 3

4 4 The Intel Xeon Phi Coprocessor (Formerly Code name Knights Corner)

5 Intel s Many-Core and Multicore Engines Intel Xeon processor: Intel s Foundation of HPC Performance Suited for full scope of workloads Industry leading performance/watt for serial & highly parallel workloads Multi-core Intel Xeon processor at GHz Intel Xeon Phi Coprocessor Based on standard Intel Architecture (IA) Optimized for highly parallelized compute intensive workloads Runs an Open Source Linux * OS Common programming model & software tools Many Core Intel Xeon Phi coprocessor at GHz Note: Die Size not to scale 5

6 Architecting Scaling Full C / C++ / Fortran compilers and Intel Math Kernel Library and Intel Integrated Performance Primitives libraries Programming models that span multi-core IA and Intel Xeon Phi coprocessors IA ecosystem support Eliminate Need for Dual Programming Architecture 6

7 Intel Xeon Phi Coprocessor Core Architecture 4 Threads per core, 64 bit, in order, specialized instructions 512 bit wide registers Vector Processing Unit (VPU): integer, SP, DP; 3 operand, transcendental functions realized in hardware Fully coherent L2 HW prefetching Improved ring interconnect 7

8 Intel Xeon Phi Coprocessor Software Architecture Overview Linux * Host Host-side application User code Offload libraries, user-level driver, user-accessible APIs and libraries Intel Xeon Phi Coprocessor Target-side application User code Offload libraries, user-accessible APIs and libraries User-level code System-level code Intel Many Integrated Core Architecture (Intel MIC Architecture) support libraries, tools, and drivers Intel MIC Architecture communication and application-launching support User-level code System-level code Linux OS PCIe PCI Express * Card OS PCIe 8

9 Spectrum of Programming & Execution Models Multicore Centric Many-core Centric (Intel Xeon processors) (Intel Xeon Phi Coprocessors) Multicore-hosted Offload Symmetric Many-core-hosted General purpose serial and parallel computing Codes with balanced needs Codes with highly- parallel phases Highly-parallel codes Multicore Main( ) Foo( ) MPI_*() Main( ) Foo( ) MPI_*() Main( ) Foo( ) MPI_*() Many-core Foo( ) Main( ) Foo( ) MPI_*() Main() Foo( ) MPI_*() Range of Models to Meet Application Needs 9

10 Intel Xeon Phi Coprocessor Programming Models Intel Many Integrated Core Architecture (Intel MIC Architecture) Regular programming techniques apply on this platform This is an Intel architecture, with caches, its own memory, etc. It is programmed just like a traditional SMP machine Offload code will run on both platforms Some modifications to existing code might be needed The familiar Intel development environment is available: Intel C, C++, and Fortran Compilers OpenMP*, Intel Threading Building Blocks, Intel Cilk Plus Intel Debugger Intel Math Kernel Library (Intel MKL) and Intel Performance Libraries (Intel IPL) Intel VTune Amplifier XE Standard runtime libraries, even pthreads* 10

11 Agenda Overview Automatic offloading Offloading by pragmas and keywords Native application Cluster and MPI support 11 11

12 Demo: Intel Math Kernel Library (Intel MKL) and Automatic Offload (AO) 12

13 Intel MKL Automatic Offload Model IA Host Intel Xeon Phi Coprocessor User Application calls: sgemm(&transa, &transb, &M, &N, &K, &alpha, A,&LDA, B, &LDB, &beta, C, &LDC); MKL Worker + MKL Library MKL Library Transport Transport User enjoys host and Intel Xeon Phi coprocessor parallelism and performance without changing code User still can use environment variables/functions to control the work division to fine tune the performance 13 (Intel MKL) Intel Math Kernel Library

14 Intel MKL Automatic Offload (AO) Overview Key feature: No changes to Intel MKL use are required Function calls and link line stay the same Speedup is transparent: if there is no Intel Xeon Phi Coprocessor, Intel MKL runs as usual AO-aware functions divide work and data between the host and Intel Xeon Phi Coprocessor(s) automatically Not everything can be accelerated: Only functions with sufficiently high flops / bytes ratio like SGEMM, DGEMM and matrix solvers 14 (Intel MKL) Intel Math Kernel Library

15 Enabling Intel MKL Automatic Offload (AO) for Intel MIC Architecture Via environment variable MKL_MIC_ENABLE=1 With MKL functions: int mkl_mic_enable() enables automatic offload returns 0 if the operation was successful returns -1 if the operation failed int mkl_mic_get_device_count() returns the number of Intel Xeon Phi coprocessors in the system 15 (Intel MKL) Intel Math Kernel Library Intel Many Integrated Core Architecture (Intel MIC Architecture)

16 Agenda Overview Automatic offloading Offloading by pragmas and keywords Native application Cluster and MPI support 16

17 User Controlled Offload Model IA Host Intel Xeon Phi Coprocessor User Application calls: #pragma offload target(mic) foo(a,b,c,d); Worker + Libraries (Intel MKL, TBB.) Transport Transport User enjoys host and Intel Xeon Phi coprocessor parallelism and performance but needs (usually) small changes to existing code Additional libraries need native port to the Intel Xeon Phi coprocessor 17 Intel Math Kernel Library (Intel MKL) Intel Threading Building Blocks (Intel TBB)

18 Offload Using Pragmas OpenMP* & Intel Cilk Plus Examples C/C++ Intel Cilk Plus #pragma offload target(mic) : foo(a,b,c,d); _declspec(target(mic)) void foo (a,b,c,d) { } _Cilk_for (int i=0; i < count; i++) { } a[i] = b[i] * c + d; C/C++ OpenMP* #pragma offload target (mic) #pragma omp parallel for reduction(+:pi) for (i=0; i<count; i++) { } float t = (float)((i+0.5)/count); pi += 4.0/(1.0+t*t); pi /= count; // executes on host Fortran OpenMP*!dir$ omp offload target(mic)!$omp parallel do do i=1,10 A(i) = B(i) * C(i) enddo!$omp end parallel 18

19 Offload with Language Extensions // Shared variable declaration for pi _Cilk_Shared float pi; // Shared function declaration for // compute _Cilk_Shared void compute_pi(int count) { int i; } #pragma omp parallel for reduction(+:pi) for (i=0; i<count; i++) { float t = (float)((i+0.5f)/count); pi += 4.0f/(1.0f+t*t); } void findpi() { int count = 10000; } // Initialize shared global // variables pi = 0.0f; // Compute pi on target _Cilk_Offload compute_pi(count); pi /= count; 19

20 Compiler Extensions for C/C++ Simple Offload Extensions with the Intel Compilers New offload pragma #pragma offload ( clauses ) Execute next statement on target (which could be an OpenMP* parallel construct or a function) Input clause in (var-list modifiers opt ) Copy CPU to target Output clause out (var-list modifiers opt ) Copy target to CPU Inputs & outputs inout (var-list modifiers opt ) Copy both ways Non-copied data nocopy (var-list modifiers opt ) Data is local to target Place function on target Place on data target declspec ( target ( x ) ) declspec (target(mic)) float array [8000]; Compile function for host and target Two arrays are created, one on the host and one on the target 20

21 Running Offloaded Applications Build application with -offload-build switch: icpc -offload-build o foo foo.cpp Execute binary: foo Binary and required libraries are automatically uploaded to the Intel Xeon Phi coprocessor Direct support for OpenMP *, Intel Threading Building Blocks, Intel Cilk Plus, Intel Math Kernel Library, Intel Integrated Performance Primitives, GNU libc, GNU stdc++ 21

22 Demo: Offload with Intel Cilk Plus 22

23 Agenda Overview Automatic offloading Offloading by pragmas and keywords Native application Cluster and MPI support 23

24 How Micro is the μos of the Intel Xeon Phi Coprocessor? Fully featured Linux * kernel derived form Busybox * toolkit Drivers for virtual Ethernet Ethernet Bridging possible nfs support MICdirect driver for InfiniBand * HCAs sep driver (event based sampling with Intel VTune Amplifier XE performance profiler) ssh access 24

25 Demo: SSH Access 25

26 26 Architecture of the Linux * μos

27 27

28 Running Native Applications Build application with -mmic switch: icpc -mmic o foo foo.cpp Upload binary and required libraries to the Intel Xeon Phi coprocessor using scp: scp foo `hostname`-mic0: Execute binary: ssh `hostname`-mic0 foo Direct support for OpenMP *, Intel Threading Building Blocks, Intel Cilk Plus, Intel Math Kernel Library, Intel Integrated Performance Primitives, GNU libc, GNU stdc++ 28

29 Shared Libraries Both native and offloaded codes need libraries Standard Linux * tools to build shared libs ldd command to check dependencies: $ssh `hostname`-mic0 ldd foo linux-vdso.so.1 => (0x00007fff291ff000) libm.so.6 => /lib64/libm.so.6 (0x00007feef740d000) libcilkrts.so.5 => not found libstdc++.so.6 => /lib64/libstdc++.so.6 (0x00 ) libgcc_s.so.1 => /lib64/libgcc_s.so.1 (0x00 ) libc.so.6 => /lib64/libc.so.6 (0x00007feef6b9e000) libdl.so.2 => /lib64/libdl.so.2 (0x00007feef699a000) /lib64/ld-linux-l1om.so.2 (0x00007feef763b000) 29

30 Demo: Native Execution 30

31 Agenda Overview Automatic offloading Offloading by pragmas and keywords Native application Cluster and MPI support 31

32 Cluster Support for the Intel Xeon Phi Coprocessor Standard Linux * environment Ethernet bridging support Native NFS Basic tool chain to adapt software stack on the μos Yocto Project * initiative to provide completely configurable μos Proof of concept for native Lustre * and Panasas * panfs file systems InfiniBand * support on selected HCA 32

33 MPI Support for the Intel Xeon Phi Coprocessor MPI is the message passing standard for High Performance computing Intel is a leading vendor of MPI implementations and tools Optimized MPI application performance Application-specific tuning Automatic tuning Interconnect Independence and Runtime Selection Seamless interoperability with Intel Trace Analyzer and Collector 33

34 Offload MPI Model MPI communication taking place only between the host processors The coprocessors are used exclusively through offload capabilities Use with Intel C, C++, and Fortran Compiler for Intel Many Integrated Core Architecture, Intel Math Kernel Library, etc. Using MPI calls inside offloaded code are not supported 34

35 Coprocessor-only Model MPI Model MPI communication taking place only between the coprocessors The host processors are not used Supported with Intel C, C++, and Fortran Compiler for Intel Many Integrated Core Architecture, Intel Math Kernel Library, etc. 35

36 Symmetric MPI Model Both the host CPUs and the coprocessors execute MPI processes and take part in MPI communication Message passing is supported between all partners using shared memory, TCP or InfiniBand * The best fabric is chosen automatically Use with Intel C, C++, and Fortran Compiler Intel Many Integrated Core Architecture, Intel Math Kernel Library, etc. 36

37 Compiling a Symmetric MPI Program for the Intel Xeon Phi Coprocessor Source the environment for the Intel compiler and the Intel MPI Library Use mpiicc to compile your MPI program for the host. Use mpiicc to compile your MPI program for the Xeon Phi coprocessor adding the -mmic switch: $. /PATH_TO_INSTALL/bin/compilervars.sh intel64 $. /PATH_TO_INSTALL/intel64/bin/mpivars.sh $ mpiicc -o mpifoo.x86_64 mpifoo.c $ mpiicc -mmic -o mpifoo.mic mpifoo.c 37

38 Demo: MPI Application 38

39 Resources Parallel Programming Community 39 Intel Many Integrated Core (MIC) Architecture Forum

40 Shipping Sept 5, 2012 $1,599-$2,299 Top New Features Shipping Q $2,949 Performance Performance Profiling Reliability Reproducibility Standards Parallelism Assistance Improved compiler and library performance + Ivy Bridge microarchitecture + Haswell microarchitecture A dozen new analysis features Low overhead Java* profiling CPU Power Analysis Pointer checker Heap growth analysis Improved MPI fault tolerance Conditional numerical reproducibility Expanded C++ 11 Expanded Fortran 2008 MPI 2.2 Analysis extended to include Linux *, Fortran and C# (in addition to Windows* and C/C++) + Intel Xeon Phi coprocessor Intel Cluster Studio XE Efficiently produce fast, scalable and reliable applications running on Windows * and Linux * 40

41 Summary Various programming models are available Intel Math Kernel Library can directly use Intel Xeon Phi Coprocessor Offloading can be controlled via keywords or pragmas Linux * μos allows programs to run natively on the Intel Xeon Phi coprocessor Cluster support with Intel MPI Library allows to treat the Intel Xeon Phi coprocessor as MPI node 41

42 Demos Software Pavilion Title Indispensable software development tools for desktops, servers and MIC Intel Math Kernel Library Showcase Debug Tools for Fast Runtime Issue Resolution Exhibit Hours: Tuesday, September 11 5:00PM - 7:00PM Wednesday, September 12 Wednesday, September 12 11:00AM - 1:00PM 4:00PM - 7:00PM Thursday, September 13 11:00AM - 2:00PM 42

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46 46 Backup

47 MIC Application Run Types Native applications. Running on MIC card only. Must be compiled for MIC, no code changes required. Offload applications. Running on host, but transferring data between host and card, required offload regions and variables definitions in code: declspec(target(mic)) <FUNCTIONS_OR_VARS_DEFINITION> #pragma offload target(mic) in(<var_pointer>:length(<in_bytes>)) \ out(<var_pointer>:length(<in_bytes>)) \ nocopy(<list_of_vars>) Details: C/C++/Fortran Extensions for Offload by Rajiv Deodhar (rajiv.deodhar@intel.com) MPI applications. Running on host, but transferring data between host and card by MPI

48 Options for Parallelism Intel Cilk Plus Examples Spawn and sync int fib(int n) { int x, y; if (n < 2) return n; x = cilk_spawn fib(n-1); // non-blocking x & y values y = fib(n-2); // calculated in parallel cilk_sync; // wait here until both done return x+y; } cilk_for Parallel for (int i = begin; i < end; i += 2) f(i); cilk_for (T::iterator i(vec.begin()); i!= vec.end(); ++i) g(i); 48 48

49 Heterogeneous compiler Offloading using _Offload Feature Example Description Offloading a function call x = _Offload func(y); func executes on target if possible Offloading asynchronously x = _Cilk_spawn _Offload func(y); Non-blocking offload Offload a parallel for-loop Offload array expressions _Offload _Cilk_for (i = 0; i < N; i++) { a[i] = b[i] + c[i]; } _Offload a[:] = b[:] <op> c[:]; _Offload a[:] = elemental_func(b[:]); Loop executes in parallel on target. The loop is implicitly outlined as a function call. Array operations execute in parallel on Intel MIC Architecture 49 49