Intel Xeon Phi coprocessor (codename Knights Corner) George Chrysos Senior Principal Engineer Hot Chips, August 28, 2012

Transcription

1 Intel Xeon Phi coprocessor (codename Knights Corner) George Chrysos Senior Principal Engineer Hot Chips, August 28, 2012

2 Legal Disclaimers INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. A "Mission Critical Application" is any application in which failure of the Intel Product could result, directly or indirectly, in personal injury or death. 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The information here is subject to change without notice. Do not finalize a design with this information. The products described in this document may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an order number and are referenced in this document, or other Intel literature, may be obtained by calling , or go to: Intel, the Intel logo, Xeon, Intel and Intel Xeon Phi are trademarks of Intel Corporation in the U.S. and/or other countries Other names and brands may be claimed as the property of others. Software and workloads used in performance tests may have been optimized for performance only on Intel microprocessors. Performance tests, such as SYSmark and MobileMark, are measured using specific computer systems, components, software, operations and functions. Any change to any of those factors may cause the results to vary. You should consult other information and performance tests to assist you in fully evaluating your contemplated purchases, including the performance of that product when combined with other products. For more complete information about performance and benchmark results, visit Performance Test Disclosure This document contains information on products in the design phase of development. All products, computer systems, dates and figures specified are preliminary based on current expectations, and are subject to change without notice. Intel's compilers may or may not optimize to the same degree for non-intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice. Notice revision # WARNING: Altering clock frequency and/or voltage may: (i) reduce system stability and useful life of the system and processor; (ii) cause the processor and other system components to fail; (iii) cause reductions in system performance; (iv) cause additional heat or other damage; and (v) affect system data integrity. Intel has not tested, and does not warranty, the operation of the processor beyond its specifications. Intel assumes no responsibility that the processor, including if used with altered clock frequencies and/or voltages, will be fit for any particular purpose. For more information, visit Overclocking Intel Processors Warning: Altering PC memory frequency and/or voltage may (i) reduce system stability and use life of the system, memory and processor; (ii) cause the processor and other system components to fail; (iii) cause reductions in system performance; (iv) cause additional heat or other damage; and (v) affect system data integrity. Intel assumes no responsibility that the memory, included if used with altered clock frequencies and/or voltages, will be fit for any particular purpose. Check with memory manufacturer for warranty and additional details Available on select Intel Intel Xeon and Intel Xeon Phi processors. Requires an Intel HT Technology-enabled system. Consult your PC manufacturer. Performance will vary depending on the specific hardware and software used. For more information including details on which processors support HT Technology, visit Requires a system with a 64-bit enabled processor, chipset, BIOS and software. Performance will vary depending on the specific hardware and software you use. Consult your PC manufacturer for more information. For more information, visit Requires a system with Intel Turbo Boost Technology. Intel Turbo Boost Technology and Intel Turbo Boost Technology 2.0 are only available on select Intel processors. Consult your PC manufacturer. Performance varies depending on hardware, software, and system configuration. For more information, visit ENERGY STAR is a system-level energy specification, defined by the Environmental Protection Agency, that relies on all system components, such as processor, chipset, power supply, etc.) For more information, visit

3 Intel Many Integrated (Intel MIC) Architecture Targeted at highly parallel HPC workloads Physics, Chemistry, Biology, Financial Services Power efficient cores, support for parallelism s: less speculation, threads, wider SIMD Scalability: high BW on die interconnect and memory General Purpose Programming Environment Runs Linux (full service, open source OS) Runs applications written in Fortran, C, C++, Supports X86 memory model, IEEE 754 x86 collateral (libraries, compilers, Intel VTune debuggers, etc) 3 Visual and Parallel Computing Group

4 Knights Corner Coprocessor KNC Card Intel Xeon Processor System Memory TCP/IP PC e x16 PCIe x16 KNC Card Channel KN KN > 50 s Linux OS Channel Channel Channel Channel Channel >= 8GB memory 4 Visual and Parallel Computing Group

5 Knights Corner Power Efficient Performance per Watt of a prototype Knights Corner Cluster compared to the 2 Top Graphics Accelerated Clusters MFLOPS/Watt Higher is Better Source: 0 Intel Corp Knights Corner Top500 # kw Nagasaki Univ. ATI Radeon Top500 # kw Barcelona Supercomputing Center Nvidia Tesla 2090 Top500 # kw 5 Visual and Parallel Computing Group

6 Knights Corner Micro-architecture PCIe Client Logic 6 Visual and Parallel Computing Group

7 Knights Corner PPF PF D0 D1 D2 E WB T0 IP T1 IP T2 IP T3 IP L1 TLB and 32KB Code Cache Code Cache Miss TLB Miss 4 Threads In-Order Pipe 0 Decode 16B/Cycle (2 IPC) Pipe 1 ucode TLB Miss Handler TLB HWP Ctl 512KB Cache VPU RF X87 RF Scalar RF VPU 512b SIMD X87 ALU 0 ALU 1 L1 TLB and 32KB Data Cache TLB Miss DCache Miss To On-Die Interconnect X86 specific logic < 2% of core + area 7 Visual and Parallel Computing Group

8 Vector Processing Unit PPF PF D0 D1 D2 E WB D2 E VC1 VC2 V1-V4 WB D2 E VC1 VC2 V1 V2 V3 V4 DEC VPU RF 3R, 1W LD EMU Vector ALUs ST 16 Wide x 32 bit 8 Wide x 64 bit Fused Multiply Add Mask RF Scatter Gather 8 Visual and Parallel Computing Group

9 Interconnect BL - 64 Bytes Data AD Command and Address AK Coherence and Credits AK AD BL 64 Bytes 9 Visual and Parallel Computing Group

10 Distributed Tag Directories TAG Valid Mask State TAG Valid Mask State Tag Directories track cache-lines in all s 10 Visual and Parallel Computing Group

11 Interleaved Memory Access TD TD TD TD TD TD TD TD 11 Visual and Parallel Computing Group

12 Interconnect: 2X AD/AK BL - 64 Bytes AD AK AK 2x AD BL 64 Bytes 12 Visual and Parallel Computing Group

13 Multi-threaded Triad Saturation for 1 AD/AK Ring Performance Simulation Data indicates saturation for a single AD/AK ring s Running Results measured in development labs at Intel on Knights Corner prototype hardware and systems. For more information go to 13 Visual and Parallel Computing Group

14 Multi-threaded Triad Benefit of Doubling AD/AK Performance Silicon Data for 2 AD + AK rings > 40% Simulation Data indicates saturation for a single AD/AK ring s Running Results measured in development labs at Intel on Knights Corner prototype hardware and systems. For more information go to 14 Visual and Parallel Computing Group

15 Streaming Stores Streams Triad for (i=0; i<huge; i++) A[i] = k*b[i] + C[i]; Without Streaming Stores Read A, B, C, Write A 256 Bytes transferred to/from memory per iteration With Streaming Stores Read B, C, Write A 192 Bytes transferred to/from memory per iteration 15 Visual and Parallel Computing Group

16 Multi-threaded Triad with Streaming Stores Silicon Data Streaming Stores > 30% Performance s Running Results measured in development labs at Intel on Knights Corner prototype hardware and systems. For more information go to 16 Visual and Parallel Computing Group

17 Cache Hierarchy Micro-architecture Choices TLB 64 entry, holds PTEs and PDEs vs. no TLB Dcache Capability Simultaneous 512b load and 512b store vs. 1 load or store per cycle Cache 512 KB vs. 256 KB Hardware Prefetcher 16 stream detectors, prefetch into the vs. no HWP (rely only on software prefetching) 17 Visual and Parallel Computing Group

18 Per- ST Performance Improvement (per cycle) Spec FP 2006 Performance impact of KNC core uarch improvements >1.8x Average Performance/Cycle Improvement 1, 1 Thread Results measured in development labs at Intel on Knights Corner and Knights Ferry prototype hardware and systems. For more information go to 18 Visual and Parallel Computing Group

19 Caches For or Against? Relative BW Caches: high data BW low energy per byte of data supplied programmer friendly (coherence just works) Relative BW/Watt Memory BW Cache BW L1 Cache BW Coherent Caches are a key MIC Architecture Advantage Results have been simulated and are provided for informational purposes only. Results were derived using simulations run on an architecture simulator or model. Any difference in system hardware or software design or configuration may affect actual performance. 19 Visual and Parallel Computing Group

20 Example: Stencils spatial time-step simulation of a physical system $ Sized Cache blocking promotes much higher performance and performance/watt vs. memory streaming 20 Visual and Parallel Computing Group

21 Power Management: All On and Running PCIe IO PCIe Client Logic GDDR IO GDDR IO 21 Visual and Parallel Computing Group

22 C1: Clock Gate PCIe IO PCIe Client Logic GDDR IO GDDR IO When all 4T on a care have halted, core clock gates itself 22 Visual and Parallel Computing Group

23 C6: Power Gate PCIe IO PCIe Client Logic GDDR IO GDDR IO C1 time-out, power gate core, save leakage, requires core-re-init 23 Visual and Parallel Computing Group

24 Package Auto C3 PCIe IO PCIe Client Logic GDDR IO GDDR IO Timeout when all cores have been in C6, clock gate the and interconnect 24 Visual and Parallel Computing Group

25 Package C6 PCIe IO PCIe Client Logic GDDR IO GDDR IO Host Driver can initiate Package C6 Uncore Voltage Off, requires partial restart 25 Visual and Parallel Computing Group

26 Summary Intel Xeon Phi coprocessor provides: Performance and Performance/Watt for highly parallel HPC with cores, threads, wide-simd, caches, memory BW Intel Architecture general purpose programming environment advanced power management technology KNC delivers programmability and performance/watt for highly parallel HPC 26 Visual and Parallel Computing Group

27 Thank You Knights Corner brought to you by: IAG (Intel Architecture Group) DCSG (Data Center and Systems Group) VPG (Visual and Parallel Group) MIC HW Architecture HW Design SW SSG (Software and Services Group) MIC IL PCL (Intel Labs Parallel Computing Lab) 27 Visual and Parallel Computing Group

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29 Vector Processor: 512b SIMD Width DP DP DP DP 1 Shared Multiplier Circuit for /DP 13 DP DP DP DP 0 0 RF3 RF2 RF1 RF0 16 wide SIMD, 8 wide DP SIMD 2:1 Ratio good for circuit optimization 29 Visual and Parallel Computing Group

30 Gather/Scatter Address Machinery Gather Instruction Loop gather-prime loop: gather-step; jump-mask-not-zero loop Vector Register Scalar Register Base Address Index0 Index1 Index2 Index3 Index4 Index5 Index6 Index Mask Register Clear 1 1 Addr0 Addr1 Addr2 Addr3 Addr4 Addr5 Addr6 Addr Find First Access Address To TLB/ DCACHE 1 Clear = = Gather/Scatter machine takes advantage of cache-line locality 30 Visual and Parallel Computing Group

31 Package Deep C3 PCIe IO PCIe Client Logic GDDR IO GDDR IO Host Driver Initiated /Ring/TDs dropped to retention V, memory in self refresh 31 Visual and Parallel Computing Group