Intel Many Integrated Core (MIC) Architecture

Transcription

1 Intel Many Integrated Core (MIC) Architecture Karl Solchenbach Director European Exascale Labs BMW2011, November 3,

2 Notice and Disclaimers Notice: This document contains information on products in the design phase of development. The information here is subject to change without notice. Do not finalize a design with this information. Contact your local Intel sales office or your distributor to obtain the latest specification before placing your product order. INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY RELATING TO SALE AND/OR USE OF INTEL PRODUCTS, INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT, OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications, product descriptions, and plans at any time, without notice. All products, dates, and figures are preliminary for planning purposes and are subject to change without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined. Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. Performance tests and ratings are measured using specific computer systems and/or components and reflect the approximate performance of Intel products as measured by those tests. Any difference in system hardware or software design or configuration may affect actual performance. The Intel products discussed herein may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Knights Corner, Knights Ferry, Aubrey Isle and other code names featured are used internally within Intel to identify products that are in development and not yet publicly announced for release. Customers, licensees and other third parties are not authorized by Intel to use code names in advertising, promotion or marketing of any product or services and any such use of Intel's internal code names is at the sole risk of the user. Copies of documents which have an order number and are referenced in this document, or other Intel literature, may be obtained by calling , or by visiting Intel's website at Intel, Itanium, Xeon, Pentium, and the Intel logo are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries. Copyright 2011, Intel Corporation. All rights reserved. *Other names and brands may be claimed as the property of others. 2

3 Intel and Parallelism Images not intended to reflect actual die sizes 64-bit Intel Xeon processor Intel Xeon processor 5100 series Intel Xeon processor 5500 series Intel Xeon processor 5600 series Sandy Bridge Aubrey Isle (in Knights Ferry) Frequency 3.6GHz 3.0GHz 3.2GHz 3.3GHz 2.7GHz 1.2GHz Core(s) Thread(s) SIMD width 128 (2 clock) 128 (1 clock) 128 (1 clock) 128 (1 clock) 256 (1 clock) 512 (1 clock) MIC extends established CPU architecture and programming concepts to highly parallel applications 3

4 Many Core and Multi-Core Many Integrated Cores at GHz Multi-core Intel Xeon processor at GHz Die Size not to scale In Intel MIC, each core is smaller and lower power, has lower single thread performance, but higher aggregate performance Many core relies on a high degree of parallelism to compensate for the lower speed of each individual core Relatively few specialized applications today are highly parallel, but those applications will benefit from Intel MIC 4

5 Knights Ferry Software development platform for Intel MIC Architecture includes: PCIe 2.0 Adapter Card Up to 2 Gigabytes of GDDR5 Aubrey Isle Intel MIC processor with up to 32 cores and 128 threads, and 8 MB of coherent L2 cache Designed for systems that support 300W PCIe design guidelines Intel Software Development tools Growing availability through 2011 Software development platform for Intel MIC Architecture 5

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8 Enabling & Advancing Parallelism High Performance Parallel Programming Intel tools, libraries and parallel models extend to multicore, many-core and heterogeneous computing Compiler Libraries Parallel Models Code Multicore Many core Cluster Use One Software Architecture Today. Scale Forward Tomorrow. 8

9 Invest in Common Tools and Programming Models Multicore Intel Xeon processors are designed for intelligent performance and smart energy efficiency Your Application Many-core Intel MIC Architecture - coprocessors are ideal for highly parallel computing applications + Continuing to advance Intel Xeon processor family and instruction set (e.g., Intel AVX, etc.) Use One Software Architecture Today Tomorrow Software development platforms ramping now Use One Software Architecture Today. Scale Forward Tomorrow. 9

10 High Performance Software Products Supporting Multicore and Many-core Development Intel Parallel Studio XE* Advanced Performance Intel Cluster Studio XE* Distributed Performance Intel C/C++ and Fortran Compilers w/openmp Intel MKL, Intel Cilk Plus, Intel TBB Library, Intel ArBB Library Intel IPP Library Intel Inspector XE, Intel VTune Amplifier XE, Intel Advisor Intel MPI Library Intel Trace Analyzer and Collector Intel Parallel Studio XE Performance. Scale Forward. Proven 10

11 A Family of Parallel Programming Models Developer Choice Intel delivers developer choice of high-performance parallel computing tools and technologies Intel Parallel Building Blocks ( Intel PBB) adds parallelism for the vast majority of applications.. Innovating on Parallel Programming Increased Application Efficiency and Performance on IA and Intel MIC Architecture 11

12 ISC 11 demos - Performance Hybrid LU Factorization: Up to 772 GFLOPS using 2 Intel Xeon 5680 processors and 1 Knights Ferry Hybrid SGEMM with Intel MKL: 1+ TFLOP using 2 Intel Xeon 5680 processors and 1 Knights Ferry with no change to code Native SGEMM: 7.4 TFLOPS in a node with 8 Knights Ferry cards; 925 GFLOPS per card without data transfer Software and workloads used in performance tests may have been optimized for performance only on Intel microprocessors. Performance tests, such as SYSmark and MobileMark, are measured using specific computer systems, components, software, operations and functions. Any change to any of those factors may cause the results to vary. You should consult other information and performance tests to assist you in fully evaluating your contemplated purchases, including the performance of that product when combined with other products. Source: Intel measured results as of March See backup for details. For more information go to 12

13 Intel exascale activities in Europe 13 Intel Confidential

14 A Look at the TOP500 List 1 Exaflop/s in Petaflop/s entry level in Intel Confidential data center group

15 US DOE s Exascale Expectations DOE driving for an ExaFLOP system by 2018 Fundamental challenges on Parallelsim, Energy, Resilience Lower ratios of floating point speed vs Memory size Memory bandwidth Communication bandwidth Char Ratio Peak Perf 2 PF 1 EF x 500 Sys Memory 0.3 PB PB x Node Perf 125 GF 1-2 TF x 8-16 Node Mem BW 25 GB/s GB/s Node Concurrency x ~1000 x 80 Interconnect BW 1.5 GB/s 50 GB/s x 30 # Nodes 20K ~ 1 M x 50 Total Concurrency 225K ~1 B x 4000 Storage 15 PB 300 PB x 20 I/O 0.2 TB/s 60 TB/s x 300 MTTI Days 1 Day x 0.1 Power 6 MW 20 MW x 3 15 Intel Confidential data Intel center Confidential group 15

16 Exascale Challenges Exploiting massive parallelism Mathematical models, numerical methods, and software implementations will all need new conceptual and programming paradigms to make effective use of unprecedented levels of concurrency. Reducing power requirements Reducing the power requirement by a factor of at least 100 is a challenge for future hardware and software technologies. Coping with run-time errors an exascale system will have approximately one billion processing elements. An immediate consequence is that the frequency of errors will increase while timely identification and correction of errors become much more difficult. 16 Source: Exascale Computing Summary Report of the Advanced Scientific Computing Advisory Committee (ASCAC) Subcommittee Intel Confidential

17 Intel Exascale Labs - Europe Strong commitment to advance computing leading edge: Intel collaborating with HPC community & European researchers 3 labs in Europe, Exascale computing is the central topic ExaScale Computing Research Center, Paris Exascale Cluster Lab, Jülich Exascience Lab, Leuven Performance and scalability of Exascale applications Exascale cluster scalability and reliability Space weather prediction Architectural simulation and visualization Numerical kernels 17 Intel Confidential

18 The Exascale Labs are part of the Intel Labs Europe Network 18 Intel Confidential 18 Intel Confidential

19 New: Intel-BSC Exascale Lab To be announced at SC11: Intel-BSC exascale lab Focus on StarSs, Paraver/Dimemas, asynchronous algorithms ExaScale Computing Research Center, Paris Exascale Cluster Lab, Jülich Exascience Lab, Leuven Intel -BSC Exascale Lab, Barcelona Performance and scalability of Exascale applications Exascale cluster scalability and reliability Space weather prediction Architectural simulation and visualization Numerical kernels Scalable Run Time System Exascale tools New algorithms 19 Intel Confidential