Block Diagram NC VDD2 VDD1 GND NC NC NC NC GND NC
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1 248-pixel CCD Linear Sensor (B/W) Description The ILX7B is a reduction type CCD linear sensor designed for facsimile, image scanner and OCR use. This sensor reads B4 size documents at a density of 2DPI (Dot Per Inch). Featuring a shutter funcyion, correspondences with the sensitivity correction, etc, is possible. A built-in timing generator and clockdrivers ensure direct drive at V logic for easy use. ILX7B 22 pin DIP (Cer-DIP) Preliminary Features Number of effective pixels: 248 pixels Pixel size: 4µm 4µm (4µm pitch) Built-in timing generator and clock-drivers Shutter function Ultra low lag Maximum clock frequency: MHz Absolute Maximum Ratings Supply voltage VDD V VDD2 6 V Operating temperature to + C Storage temperature 3 to +8 C Pin Configuration (Top View) VOUT 22 VDD2 2 2 VDD2 3 2 VDD SHSW 4 9 φclk VDD2 8 φshut 9 4 Block Diagram VDD2 VDD Shutter drain Shutter gate D39 D38 D37 D36 D3 D34 S248 S247 S S2 D4 D D Read out gate CCD analog shift register Output amplifier Sample-and-hold circuit Clock-drivers Shutter gate pulse generator Read out gate pulse generator Mode selector Clock pulse generator Sample-and-hold pulse generator VDD2 φclk VDD2 SHSW φshut VOUT Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. PEY37
2 Pin Description Pin No. Symbol Description 2 3 VOUT Signal output Pin No. Symbol Description SHSW Switch { With S/H Without S/H VDD2 φclk Clock pulse VDD2 V power supply 9 9 VDD2 V power supply 2 VDD 9V power supply 2 VDD2 V power supply Clock pulse 22 VDD2 V power supply Recommended Supply voltage Item Min. Typ. Max. Unit VDD V VDD V Note) Rules for raising and lowering power supply voltage To raise power supply voltage, first raise VDD (9V) and then VDD2 (V). To lower voltage, first lower VDD2 (V) and then VDD (9V). Mode Description Mode in use S/H Yes No Pin condition Pin 4 SHSW VDD2 Input Capacity of Pins Item Symbol Min. Typ. Max. Unit Input capacity of φclk pin CφCLK pf Input capacity of pin C pf Input capacity of φshut pin CφSHUT pf Recommended Input Pulse Voltage Item Input clock high level Input clock low level Min. 4. Typ. Max. Unit.. V. V 2
3 Electro-optical Characteristics (Ta = 2 C, VDD = 9V, VDD2 = V, Clock frequency = MHz, Light source = 32K, IR cut filter: CM-S (t =.mm)) Item Symbol Min. Typ. Max. Unit Remarks Sensitivity R (3) 4 () V/(lx s) Note Sensitivity nonuniformity PRNU 2. (8.) % Note 2 Saturation output voltage VSAT (.).8 V Dark voltage average VDRK.3 (2.) mv Note 3 Dark signal nonuniformity DSNU. (3.) mv Note 3 Image lag IL.2 % Note 4 Dynamic range DR 6 Note Saturation exposure SE.4 lx s Note 6 9V supply current IVDD 4. (8.) ma V supply current IVDD2.8 (.) ma Total transfer efficiency TTE % Output impedance ZO 6 Ω Offset level VOS 4. V Note 7 Shutter lag SHUT. (.) % Note 8 Note). For the sensitivity test light is applied with a uniform intensity of illumination. 2. PRNU is defined as indicated below. Ray incidence conditions are the same as for Note. (VMAX VMIN)/2 PRNU = [%] VAVE The maximum output is set to VMAX, the minimum output to VMIN and the average output to VAVE. 3. Integration time is ms. 4. VOUT = mv. DR = VSAT VDRK When optical accumulated time is shorter, the dynamic range gets wider because dark voltage is in proportion to optical accumulated time. 6. SE = VSAT R 7. VOS is defined as indicated below. OS D3 D32 D33 S VOS 3
4 8. To stipulate the lag during shutter opetation, use the formula below. Place the output voltage average value during shutter operation at VSHUT and the output Voltage average value when the shutter is not in operation at VAVE. (Refer to Fig..) VSAT SHUT= [%] R Please note that the shutter pulse at this time accord with Fig.. 4
5 Fig.. Clock Timing Diagram (without S/H mode) D2 D3 D4 D D6 D D2 D3 D4 D D3 D32 D33 S S2 S3 S4 S24 S246 S247 S248 D34 D3 D36 S37 S38 D φclk VOUT Dummy signal (33 pixels) Optical black (8 pixels) Effective picture elements signal (248 pixels) Dummy signal (6 pixels) -line output period (287 pixels) ILX7B
6 Fig. 2. φclk, VOUT Timing t t2 φclk t3 t4 t VOUT t6 Item Symbol Min. Typ. Max. Unit φclk pulse rise/fall time t, t2 ns φclk pulse duty 4 6 % φclk VOUT t 8 ns φclk VOUT2 t ns t3 / (t3 + t4) Fig. 3., φclk Timing t8 t9 t φclk t7 t Item Symbol Min. Typ. Max. Unit, φclk pulse timing t7, t ns pulse rise/fall time t8, t ns pulse period t9 ns 6
7 Fig. 4. φshut Timing φshut t2 t3 t4 Item φshut pulse rise/fall time φshut pulse period Symbol t2, t3 t4 Min. Typ. Max. Unit ns ns 7
8 Fig.. Shutter Operation Mode Clock φclk 287 bits or more 8 φshut ms Illumination Light source ON During shutter lag evaluation, the light source will be accompanied by a flash. ILX7B
9 Fig.6. Shutter Pulse and Output Voltage V V Illumination ON OFF ON OFF ON OFF 9 φshut V V Shutter ON VSHUT VOUT VAVE ILX7B
10 Description of Shutter Pin 9 ) The state at V is when the shutter is not in operation. 2) When dropped to V, the shutter gate will open, letting the accumulated charge of the sensor be thrown away to the shutter drain. V V The charge is sent to the transfer register as signal charge. Accumulated charge of the sensor The charge up to this point will be thrown away to the shutter drain. φshut V V Shutter gate ON
11 Example of Representative Characteristics..9.8 Spectral sensitivity characteristics (Standard characteristics) Ta = 2 C Relative sensitivity Wavelength [nm] Dark signal voltage rate vs. Ambient temperature (Standard characteristics) VDD, VDD2 supply current vs. Clock frequency (Standard characteristics) IVDD IVDD2 Dark signal voltage rate. IVDD, IVDD2 VDD, VDD2 supply current [ma] M M M Ta Ambient temperature [ C] Clock frequency [Hz]
12 Application Circuit V 9V VDD2 (D) VDD2 (D) VDD (A) (A) (A) (D) 2 VOUT SHSW φclk VDD2 (D) φshut µ µ/6v 3k.µ 22µ/V Output signal 2SA7 φclk φshut Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. ILX7B
13 Notes on Handling ) Static charge prevention CCD image sensors are easily damaged by static discharge. Before handling, be sure to take the following protective measures. a) Either handle bare handed or use non-chargeable gloves, clothes or material. Also use conductive shoes. b) When handling directly use an eath band. c) Install a conductive mat on the floor or working table to prevent the generation of static electricity. d) lonized air is recommended for discharge when handling CCD image sensors. e) For the shipment of mounted substrates use cartons treated for the prevention of static charges. 2) Notes on handling CCD Cer-DIP package The following points should be observed when handling and installing Cer-DIP packages. a) Remain within the following limits when applying static load to the ceramic portion of the package: () Compressive strength: 39N/surface (Do not apply load more than.7mm inside the outer perimeter of the glass portion.) (2) Shearing strength: 29N/surface (3) Tensile strength: 29N/surface (4) Torsional strength:.9nm Upper ceramic layer 39N 29N 29N.9Nm Lower ceramic layer () Low-melting glass (2) (3) (4) b) In addition, if a load is applied to the entire surface by a hard component, bending stress may be generated and the package may fracture, etc., depending on the flatness of the ceramic portion. Therefore, for installation, either use an elastic load, such as a spring plate, or an adhesive. c) Be aware that any of the following can cause the glass to crack because the upper and lower ceramic layers are shielded by low-melting glass. () Applying repetitive bending stress to the external leads. (2) Applying heat to the external leads for an extended period of time with a soldering iron. (3) Rapid cooling or heating. (4) Rapid cooling or impact to a limited portion of the low-melting glass with a small-tipped tool such as tweezers. () Prying the upper or lower ceramic layers away at a support point of the low-melting glass. Note that the preceding notes should also be observed when removing a component from a board after it has already been soldered. 3) Soldering a) Make sure the package temperature does not exceed 8 C. b) Solder dipping in a mounting furnace causes demage to the glass abd other defects. Use a 3W soldering iron with a ground wire and solder each pin in less than 2 seconds. For repairs and remount, cool sufficiently. c) To dismount image sensors, do not use a solder suction equipment. When using an electric desoldering tool, ground the controller. For the control system, use a zero cross type. 3
14 4) Dust and dirt protection a) Operate in clean environments. b) Do not either touch glass plates by hand or have any object come in contact with glass surfaces. Should dirt stick to a glass surface blow it off with an air blower. (For dirt stuck through static electricity, ionized air is recommended.) c) Clean with a cotton bud and ethyl alcohol if the glass surface is grease stained. Be careful not to scratch the glass. d) Keep in case to protect from dust and dirt. To prevent dew condensation, preheat or precool when moving to a room with great temperature differences. ) Exposure to high temperature or humidity will affect the characteristics. Accordingly avoid storage or usage in such conditions. 6) CCD image sensors are precise optical equipment that should not be subject to mechanical shocks. 4
15 4. ± ±.. ±.. ±. to 9 Package Outline Unit: mm 22 pin DIP (4mil) 4.6 ±. 7.3 ± (4µm X 248Pixels) 22 2 V H No. Pixel.2. The height from the bottom to the sensor surface is 2.4 ±.3mm. 2. The thickness of the cover glass is.7mm, and the refractive index is M PACKAGE STRUCTURE PACKAGE MATERIAL LEAD TREATMENT LEAD MATERIAL PACKAGE MASS Cer-DIP TIN PLATING 42 ALLOY.2g Sony Corporation DRAWING NUMBER LS-A8-(E) ILX7B
Block Diagram NC VDD2 VDD1 GND NC NC NC NC GND NC
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