Block Diagram NC VDD2 VDD1 GND NC NC NC NC GND NC

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1 2048-pixel CCD Linear Seor (B/W) ILX55B Description The ILX55B is a reduction type CCD linear seor designed for facsimile, image scanner and OCR use. This seor reads B4 size documents at a deity of 200DPI (Dot Per Inch). A built-in timing generator and clock-drivers eure direct drive at 5V logic for easy use. 22 pin DIP (Cer-DIP) Features Number of effective pixels: 2048 pixels Pixel size: 4µm 4µm (4µm pitch) Built-in timing generator and clock-drivers Ultra low lag Maximum clock frequency: 5MHz Block Diagram 9 Absolute Maximum Ratings Supply voltage VDD V 6 V Operating temperature to +55 C Storage temperature 30 to +80 C Pin Configuration (Top View) VOUT VDD SHSW VDD D39 D38 D37 D36 D35 D34 S2048 S2047 S S2 D4 D5 D33 Read out gate CCD analog shift register Clock-drivers Read out gate pulse generator Mode selector Clock pulse generator Sample-and-hold pulse generator SHSW Output amplifier Sample-and-hold circuit VOUT Sony reserves the right to change products and specificatio without prior notice. This information does not convey any licee by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume respoibility for any problems arising out of the use of these circuits. E0Y35

2 ILX55B Pin Description Pin No. Symbol Description 2 3 VOUT Signal output Pin No. Symbol Description SHSW Switch { With S/H Without S/H 5 5 Clock pulse V power supply 9 9 5V power supply 20 VDD 9V power supply 2 5V power supply Clock pulse 22 5V power supply Recommended Supply voltage Typ. Max. Unit VDD V V Note) Rules for raising and lowering power supply voltage To raise power supply voltage, first raise VDD (9V) and then (5V). To lower voltage, first lower (5V) and then VDD (9V). Mode Description Mode in use S/H Yes No Pin condition Pin 4 SHSW Input Capacity of Pi Symbol Typ. Max. Unit Input capacity of pin C pf Input capacity of pin C pf Recommended Input Pulse Voltage Input clock high level Input clock low level Typ. Max. Unit V 0.5 V 2

3 ILX55B Electro-optical Characteristics (Ta = 25 C, VDD = 9V, = 5V, Clock frequency = MHz, Light source = 3200K, IR cut filter: CM-500S (t =.0mm)) Symbol Typ. Max. Unit Remarks Seitivity R V/(lx s) Note Seitivity nonuniformity PRNU % Note 2 Saturation output voltage VSAT.5.8 V Dark voltage average VDRK mv Note 3 Dark signal nonuniformity DSNU mv Note 3 Image lag IL 0.02 % Note 4 Dynamic range DR 6000 Note 5 Saturation exposure SE lx s Note 6 9V supply current IVDD ma 5V supply current I ma Total trafer efficiency TTE % Output impedance ZO 600 Ω Offset level VOS 4.0 V Note 7 Note). For the seitivity test light is applied with a uniform inteity of illumination. 2. PRNU is defined as indicated below. Ray incidence conditio are the same as for Note. (VMAX VMIN)/2 PRNU = 0 [%] VAVE The maximum output is set to VMAX, the minimum output to VMIN and the average output to VAVE. 3. Integration time is ms. 4. VOUT = 500mV 5. DR = VSAT VDRK When optical accumulated time is shorter, the dynamic range gets wider because dark voltage is in proportion to optical accumulated time. 6. SE = VSAT R 7. VOS is defined as indicated below. OS D3 D32 D33 S VOS 3

4 Fig.. Clock Timing Diagram (without S/H mode) D2 D3 D4 D5 D6 D D2 D3 D4 D5 D3 D32 D33 S S2 S3 S4 S2045 S2046 S2047 S2048 D34 D35 D36 S37 S38 D VOUT Dummy signal (33 pixels) Optical black (8 pixels) Effective picture elements signal (2048 pixels) Dummy signal (6 pixels) -line output period (2087 pixels) ILX55B

5 ILX55B Fig. 2., VOUT Timing t t2 t3 t4 t5 VOUT t6 Symbol Typ. Max. Unit pulse rise/fall time t, t2 0 pulse duty % VOUT t VOUT2 t t3 / (t3 + t4) Fig. 3., Timing t8 t9 t t7 t Symbol Typ. Max. Unit, pulse timing t7, t pulse rise/fall time t8, t 0 pulse period t

6 ILX55B Example of Representative Characteristics Spectral seitivity characteristics (Standard characteristics) Ta=25 C Relative seitivity Wavelength [nm] Dark signal voltage rate vs. Ambient temperature (Standard characteristics) VDD, supply current vs. Clock frequency (Standard characteristics) IVDD I Dark signal voltage rate IVDD, I VDD, supply current [ma] Ta Ambient temperature [ C] M M Clock frequency [Hz] 5M 6

7 Application Circuit 5V Ω 9V VOUT SHSW (D) (D) (D) (D) VDD (A) (A) (A) (D) µ µ/6v 3kΩ 0.0µ 22µ/V Output signal 2SA75 Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume respoibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. ILX55B

8 ILX55B Notes on Handling ) Static charge prevention CCD image seors are easily damaged by static discharge. Before handling, be sure to take the following protective measures. a) Either handle bare handed or use non-chargeable gloves, clothes or material. Also use conductive shoes. b) When handling directly use an eath band. c) Itall a conductive mat on the floor or working table to prevent the generation of static electricity. d) lonized air is recommended for discharge when handling CCD image seors. e) For the shipment of mounted substrates use carto treated for the prevention of static charges. 2) Notes on handling CCD Cer-DIP package The following points should be observed when handling and italling Cer-DIP packages. a) Remain within the following limits when applying static load to the ceramic portion of the package: () Compressive strength: 39N/surface (Do not apply load more than 0.7mm iide the outer perimeter of the glass portion.) (2) Shearing strength: 29N/surface (3) Teile strength: 29N/surface (4) Torsional strength: 0.9Nm Upper ceramic layer 39N 29N 29N 0.9Nm Lower ceramic layer () Low-melting glass (2) (3) (4) b) In addition, if a load is applied to the entire surface by a hard component, bending stress may be generated and the package may fracture, etc., depending on the flatness of the ceramic portion. Therefore, for itallation, either use an elastic load, such as a spring plate, or an adhesive. c) Be aware that any of the following can cause the glass to crack because the upper and lower ceramic layers are shielded by low-melting glass. () Applying repetitive bending stress to the external leads. (2) Applying heat to the external leads for an extended period of time with a soldering iron. (3) Rapid cooling or heating. (4) Rapid cooling or impact to a limited portion of the low-melting glass with a small-tipped tool such as tweezers. (5) Prying the upper or lower ceramic layers away at a support point of the low-melting glass. Note that the preceding notes should also be observed when removing a component from a board after it has already been soldered. 3) Soldering a) Make sure the package temperature does not exceed 80 C. b) Solder dipping in a mounting furnace causes demage to the glass abd other defects. Use a 30W soldering iron with a ground wire and solder each pin in less than 2 seconds. For repairs and remount, cool sufficiently. c) To dismount image seors, do not use a solder suction equipment. When using an electric desoldering tool, ground the controller. For the control system, use a zero cross type. 8

9 ILX55B 4) Dust and dirt protection a) Operate in clean environments. b) Do not either touch glass plates by hand or have any object come in contact with glass surfaces. Should dirt stick to a glass surface blow it off with an air blower. (For dirt stuck through static electricity, ionized air is recommended.) c) Clean with a cotton bud and ethyl alcohol if the glass surface is grease stained. Be careful not to scratch the glass. d) Keep in case to protect from dust and dirt. To prevent dew condeation, preheat or precool when moving to a room with great temperature differences. 5) Exposure to high temperature or humidity will affect the characteristics. Accordingly avoid storage or usage in such conditio. 6) CCD image seors are precise optical equipment that should not be subject to mechanical shocks. 9

10 4.0 ± ± ± ± to 9 Package Outline Unit: mm 22 pin DIP (400mil) 4.6 ± ± (4µm X 2048Pixels) 22 2 V H No. Pixel The height from the bottom to the seor surface is 2.45 ± 0.3mm. 2. The thickness of the cover glass is 0.7mm, and the refractive index is M PACKAGE STRUCTURE PACKAGE MATERIAL LEAD TREATMENT Cer-DIP TIN PLATING Sony Corporation LEAD MATERIAL 42 ALLOY PACKAGE MASS 5.20g DRAWING NUMBER LS-A8-0(E) ILX55B