Block Diagram NC VDD2 VDD1 GND NC NC NC NC GND NC

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1 2048-pixel CCD Linear Seor (B/W) ILX55A Description The ILX55A is a reduction type CCD linear seor designed for facsimile, image scanner and OCR use. This seor reads B4 size documents at a deity of 200DPI (Dot Per Inch). A built-in timing generator and clock-drivers eure direct drive at 5 logic for easy use. 22 pin DIP (Cer-DIP) Features Number of effective pixels: 2048 pixels Pixel size: 4µm 4µm (4µm pitch) Built-in timing generator and clock-drivers Ultra low lag Maximum clock frequency: 5MHz Block Diagram 9 Absolute Maximum Ratings Supply voltage DD 6 Operating temperature to +55 C Storage temperature 30 to +80 C Pin Configuration (Top iew) OUT DD SHSW 4 9 φclk DD D OUT D38 D37 D36 D35 D34 S2048 S2047 S S2 D4 D5 D33 Read out gate CCD analog shift register Output amplifier Sample-and-hold circuit Clock-drivers Read out gate pulse generator Mode selector Clock pulse generator Sample-and-hold pulse generator φclk SHSW φrog φrog Sony reserves the right to change products and specificatio without prior notice. This information does not convey any licee by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume respoibility for any problems arising out of the use of these circuits. E00439-PS

2 Pin Description Pin No. Description Pin No. Description OUT Signal output SHSW Switch { with S/H without S/H φclk Clock pulse power supply power supply 20 DD 9 power supply 2 5 power supply φrog Clock pulse 22 5 power supply Recommended Supply oltage DD Note) Rules for raising and lowering power supply voltage To raise power supply voltage, first raise DD (9) and then (5). To lower voltage, first lower (5) and then DD (9). Mode Description Mode in use S/H Yes No Pin condition Pin 4 SHSW Input Capacity of Pi Input capacity of φclk pin CφCLK pf Input capacity of φrog pin CφROG pf Recommended Input Pulse oltage Input clock high level Input clock low level

3 Electrooptical Characteristics (Ta = 25 C, DD = 9, = 5, Clock frequency = MHz, Light source = 3200K, IR cut filter: CM-500S (t =.0mm)) Remarks Secsitivity R /(lx s) Note Seitivity nonuniformity PRNU % Note 2 Saturation output voltage SAT.5.8 Dark voltage average DRK m Note 3 Dark signal nonuniformity DSNU m Note 3 Image lag IL 0.02 % Note 4 Dynamic range DR 6000 Note 5 Saturation exposure SE lx s Note 6 9 supply current IDD ma 5 supply current I ma Total trafer efficiency TTE % Output impedance ZO 600 Ω Offset level OS 4.0 Note 7 Notes). For the seitivity test light is applied with a uniform inteity of illumination. 2. PRNU is defined as indicated below. Ray incidence conditio are the same as for Note. PRNU = (MAX MIN)/2 0 [%] The maximum output is set to MAX, the minimum output to MIN and the average output to AE. 3. Integration time is ms. 4. OUT = 500m 5. DR = When optical accumulated time is shorter, the dynamic range gets wider because dark voltage is in proportion to optical accumulated time. 6. SE = SAT DRK SAT R AE 7. os is defined as indicated below. OS D3 D32 D33 S,OS 3

4 Fig.. Clock Timing Diagram (without S/H mode) Dummy signal (33 pixels) Optical black (8 pixels) Dummy signal (6 pixels) D2 D3 D4 D5 D6 D D2 D3 D4 D5 D3 D32 D33 S S2 S3 S4 S2045 S2046 S2047 S S38 D39 D34 D35 D36 S φrog 0 5 φclk 0 OUT Effective picture elements signal (2048 pixels) -line output period (2087 pixels) 4

5 Fig. 2. φclk, OUT Timing, t t2 φclk OUT t6 t3 t5 t4, φclk pulse rise/fall time t, t2 0 φclk pulse duty % φclk OUT t φclk OUT 2 t t3/(t3 + t4) Fig. 3. φrog, φclk Timing φrog t8 t9 t φclk t7 t φrog, φclk pulse timing t7, t φrog pulse rise/fall time t8, t 0 φrog pulse period t

6 Example of Representative Characteristics Spectral seitivity characteristics (Standard characteristics) Ta = 25 C Relative seitivity Wavelength [nm] Dark signal voltage rate vs. Ambient temperature (Standard characteristics) DD, supply current vs. Clock frequency (Standard characteristics) IDD I Dark signal voltage rate IDD, I DD, supply current [ma] Ta Ambient temperature [ C] 0. 0.M M Clock frequency [Hz] 5M 6

7 OUT SHSW φclk (D) (D) φrog (D) (D) DD (A) (A) (A) (D) Application Circuit 5 Ω 9 0.0µ µ/6 3kΩ Output signal µ 22µ/ 2SA75 φclk φrog Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume respoibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. 7

8 Notes of Handling ) Static charge prevention CCD image seors are easily damaged by static discharge. Before handling be sure to take the following protective measures. a) Either handle bare handed or use non chargeable gloves, clothes or material. Also use conductive shoes. b) When handling directly use an earth band. c) Itall a conductive mat on the floor or working table to prevent the generation of static electricity. d) Ionized air is recommended for discharge when handling CCD image seor. e) For the shipment of mounted substrates, use boxes treated for prevention of static charges. 2) Notes on Handling CCD Cer-DIP Packages The following points should be observed when handling and italling cer DIP packages. a) Remain within the following limits when applying static load to the ceramic portion of the package: () Compressive strength: 39N/surface (Do not apply load more than 0.7mm iide the outer perimeter of the glass portion.) (2) Shearing strength: 29N/surface (3) Teile strength: 29N/surface (4) Torsional strength: 0.9Nm Upper ceramic layer Lower ceramic layer () 39N Low-melting glass,, 29N (2) b) In addition, if a load is applied to the entire surface by a hard component, bending stress may be generated and the package may fracture, etc., depending on the flatness of the ceramic portion. Therefore, for itallation, either use an elastic load, such as a spring plate, or an adhesive. c) Be aware that any of the following can cause the glass to crack: because the upper and lower ceramic layers are shielded by low-melting glass, () Applying repetitive bending stress to the external leads. (2) Applying heat to the external leads for an extended period of time with soldering iron. (3) Rapid cooling or heating. (4) Rapid cooling or impact to a limited portion of the low-melting glass with a small-tipped tool such as tweezers. (5) Prying the upper or lower ceramic layers away at a support point of the low-melting glass. Note that the preceding notes should also be observed when removing a component from a board after it has already been soldered. (3) 29N (4) 0.9Nm 3) Soldering a) Make sure the package temperature does not exceed 80 C. b) Solder dipping in a mounting furnace causes damage to the glass and other defects. Use a grounded 30W soldering iron and solder each pin in less then 2 seconds. For repairs and remount, cool sufficiently. c) To dismount an imaging device, do not use a solder suction equipment. When using an electric desoldering tool, ground the controller. For the control system, use a zero cross type. 8

9 4) Dust and dirt protection a) Operate in clean environments. b) Do not either touch glass plates by hand or have any object come in contact with glass surfaces. Should dirt stick to a glass surface, blow it off with an air blower. (For dirt stuck through static electricity ionized air is recommended.) c) Clean with a cotton bud and ethyl alcohol if the glass surface is grease stained. Be careful not to scratch the glass. d) Keep in a case to protect from dust and dirt. To prevent dew condeation, preheat or precool when moving to a room with great temperature differences. 5) Exposure to high temperatures or humidity will affect the characteristics. Accordingly avoid storage or usage in such conditio. 6) CCD image seors are precise optical equipment that should not be subject to mechanical shocks. 9

10 4.0 ± ± ± ± to 9 ILX55A 0.25 Package Outline : mm 22pin DIP (400mil) 7.35 ± ± (4µm X 2048Pixels) 22 2 H No. Pixel PACKAGE STRUCTURE PACKAGE MATERIAL Cer-DIP LEAD TREATMENT TIN PLATING LEAD MATERIAL 42 ALLOY PACKAGE MASS 5.20g DRAWING NUMBER LS-A8-0(E) 0.3 M. The height from the bottom to the seor surface is 2.45 ± 0.3mm. 2. The thickness of the cover glass is 0.7mm, and the refractive index is.5. Sony Corporation

11 This datasheet has been download from: Datasheets for electronics components.