Fuzzy Flow Regulation for Network-on-Chip based Chip Multiprocessor System

Transcription

1 Fuzzy Flow egulation for Network-on-Chip based Chip Multiprocessor System Yuan Yao and Zhonghai Lu KTH oyal Institute of Technology, Stockholm 14 th AS-DAC Conference 19-23, January, 2014, Singapore

2 Outline Introduction roblem statement Design overview Fuzzy logic basics Design details Experimental results Conclusions 2

3 Introduction Chip multiprocessors (CM) become the mainstream to build high-performance computers. Integrating more processors onto a CM infrastructure presents challenges. - Traffic flows from processors are diverse, - The impact of interferences among traffic flows may introduce high communication delay and reduce the CM performance (in terms of CI). 3

4 Flow egulation The on-chip (σ, ρ) flow regulation 1 has been introduced to achieve proactive flow congestion control. - Based on network calculus 2, a queuing theory for worst-case performance analysis in communication networks. - σ constrains the maximum burst of a flow and ρ the long-term average rate. It can avoid traffic congestion and further decrease communication delay and reduce buffer requirements. 1. Z. Lu, M. Millberg, A. Jantsch, A. Bruce,. Wolf and T. Henriksson. Flow egulation for On-Chip Communication, roceedings of the 2009 Design, Automation and Test in Europe Conference (DATE'09), Nice, France, April J.-Y. L. Boudec and. Thiran, Network Calculus: A Theory of Deterministic Queuing Systems for the Internet. No in LNCS, 2004.

5 Flow egulation Example 0 with $0 1 with $1 n with $n regulator 0 regulator FC regulator n Network-on-Chip An example of (1, 0.2) regulation. After regulation 5

6 revious Works Two approaches in literature to achieve on-chip (σ, ρ) regulation: static 1 and partially dynamic 2. Static (σ, ρ) regulation has (σ, ρ) offline configured. It is easy to implement, especially in providing real-time performance guarantees. artially dynamic (σ, ρ) regulation can further adaptively adjust (σ, ρ) parameters online in response to real traffic workload scenarios. 1. Z. Lu, M. Millberg, A. Jantsch, A. Bruce,. Wolf and T. Henriksson. Flow egulation for On-Chip Communication, roceedings of the 2009 Design, Automation and Test in Europe Conference (DATE'09), Nice, France, April. 2. Z. Lu, Y. Wang, Dynamic Flow egulation for I Integration on Network-on-Chip, roceedings of the Sixth IEEE/ACM International Symposium on Network-on-Chip, May,

7 Network utilization is not optimized roblem Statement However, both the static or partially dynamic regulation lack the adaptivity to different network states. Thus, over-regulation or underregulation may happen. 1. Over-regulation: the network is empty, but the admission control policy is tight. 2. Under-regulation: the network is saturated, but the admission control policy is loose. In CM environment, a desirable flow admission control policy should make regulation decisions according to the traffic dynamism as well as to 7 the state of interconnection network.

8 roblem Statement - Cont. It may not be appropriate to model the network states using exact logics which defines threshold to distinguish different states. IF average_delay x THEN the network is saturated. How about average_delay=x-1? The network is unsaturated at all? The network state is better recognized using fuzzy logic rather than exact logic. Central idea: use fuzzy logic to recognize the network status and then intelligently control the 8 admission of input flows.

9 Design Overview We design two kinds of component: network state recognizer (NS) and fuzzy controller (FC), to achieve fully dynamic flow control. The control loop is marked. 0 with $0 ρ' ρ regulator 0 FC 0 K... n with $n regulator n FC n... NS Data Control avg_delay, avg_utilization Network-on-Chip... 9

10 Design Overview - Cont. In CM, σ is equal to the size of a memory data block, thus remains changed. The FC generates new flow injection rate ρ according to: 1. The cache missing rate of the local CU (ρ ), 2. The network state indicator (K) from NS. The NS monitors the network state through two metrics: average packet delay and average link utilization. K reflects the network state, and is assigned one of the following three conditions: empty, normal, saturated. 10

11 Design Overview - Cont. In order to tolerate the control latency, our design is based on a sampling window mechanism. The new flow injection rate is updated periodically instead of continually. All the CUs share the same state of interconnect network. There is only one NS per CM chip. However, FC is attached to each CU. 11

12 Fuzzy Logic Basics - rinciple Instead of using exact true/false, fuzzy logic uses degree of truth, which denotes how confidently we believe a statement is true. Degree of truth is in [0, 1], with 1 indicates totally true and 0 totally false. Degree of truth represents that a proposition might be more or less true, rather than simply true or simply false. For instance, the proposition = 2 is simply true, while The network is saturated is neither simply true nor simply false. 12

13 Fuzzy Logic Basics - Terminology Membership Function (MF): The MF determines the degree of truth value of a proposition. Fuzzy ule: A fuzzy rule is defined as a statement in the form: IF x is A THEN y is B. For example, IF average_delay x THEN the network is saturated. - Note that a fuzzy rule can also be in the following form: IF x is A AND y is B THEN z is C. ule Base: A set of fuzzy rules. Consequence Membership Function (CMF): Select the most true proposition. 13

14 Fuzzy Logic Basics - An Example D 1 LOW α β MEDIUM HIGH D 2 D 3 D 4 D 5 rule 1 d rule 2 Average acket Delay (cycles) EMTY NOMAL 1 SAT UAT ED M.F. 0.5 C.M.F. S 1 S 2 S 3 S 4 C.V. (center of the gray area) S 5 S 6 Network Congestion Status 1. IF avg. packet delay is LOW, THEN network status is EMTY 2. IF avg. packet delay is MEDIUM, THEN network status is NOMAL 3. IF avg. packet delay is HIGH, THEN network status is SAT UAT ED ule Base 14

15 eference of Fuzzy Logics For more information about fuzzy logics and fuzzy control (for example: shape/ number of MF/CMF, design of rule base) you are encouraged to read the following articles/books: 1. L.A. Zadeh, Fuzzy Logic, Stanford Encyclopedia of hilosophy, Stanford University, K. M. assino, S. Yurkovich, Fuzzy Control, Addison-Wesley,

16 Design Details Both NS and FC are designed with fuzzy logic, which are composed of the following four elements: 1. Fuzzification interface, which converts input variables into degree of truth values. 2. ule base, which contains a set of fuzzy rules. 3. Inference mechanism, which makes decision by interpreting and applying rules in the rule base. Inputs for CMF are generated. 4. Defuzzification interface, which converts the conclusions of the inference mechanism into actual output signals. 16

17 Design Details - Cont. Cache missing rate Fuzzy Controller for N Fuzzy Controller for 1 Fuzzy Controller for 0 N with $N 1 with $1 0 with $0 Fuzzification Inference mechanism Defuzzification ρ egulator for 0 ρ Network ules egulator for 1 egulator for N Network state (Empty, Normal, Saturated) Statistics Unit Network State ecognizer CM Chip Network info. (avg. delay; avg. link utilization) 17

18 0 Design Details - NS Network state Link utilization (packet/ cycle) MEDIUM(m l 2 ) acket latency (cycle) Low Medium High Low Empty Empty Saturated Medium Empty Normal Saturated High Saturated Saturated Saturated LOW (m l 1 ) HIGH(ml 3 ) 1 m l 1 (l k)=0.75 l k ξ 3 ξ 4 3 ξ min{0.75, 0.6 } = 0.6 avg. link utilization (packet/cycle) MEDIUM(m d 2 ) LOW (m d 1 ) HIGH(md 3 ) m d 2 (d k)=0.6 Empty(c nsr 1 ) Saturated(c nsr b 1 Normal(c nsr 2 ) b 2 b 3 Network State Indicator K 3 ) ζ d k ζ 4 3 ζ avg. packet delay (cycle) 18

19 Design Details - FC In fuzzy controller, the network state affects the mapping of the membership functions. To avoid both over-regulation and under-regulation: if the network is saturated, then a tight flow control policy is produced. Otherwise, a loose policy is produced. Verylow Low Slightly Low 1 Slightly high High Veryhigh Normal Empty Saturated 1 7 η 3 7 η 5 7 η η 9 7 η 11 7 η 13 7 η ρ (packet/cycle) Verylow Low Slightly Low 1 Slightly high High Veryhigh 1 7 η(b 1) 3 7 η(b 2) 5 7 η(b 3) η(b 4 ) 9 7 η(b 5) 11 7 η(b 6) 13 7 η(b 7) ρ (packet/cycle) 19

20 Experiment Setup Our design is implemented using C++ in the cycle accurate full system simulator GEMS. We simulate 4 CM chips, with16 CUs, 16 private L1 cache and 16 shared cache totally. - Synthetic flow patterns: uniform random and bit-permutation. - Benchmark program SLASH2. M0 M1 Chip 0 Chip 1 Chip 2 Chip 3 M2 M3 20

21 Synthetic Flows I: Uniform traffic The experiment shows that the fuzzy flow regulation method can efficiently regulates flows. Both overregulation and under regulation are avoided. Injection ate (packets/cycle) Source Flow (Unregulated Flow) Fuzzy based egulation E S N Simulation Time (cycles) x 10 5 ackets Simulation Time (cycles) Source Flow Static egulated Flow Unregulated Flow Fuzzy egulated Flow

22 Synthetic Flows II The fuzzy flow regulation consistently improves the results of static regulation and no-regulation for both traffic patterns No egulation Fuzzy egulation Static egulation Fuzzy egulation Static egulation No egulation ercentage ercentage Max Delay 200 cycles Max Delay 169 cycles 0.05 Max Delay 259 cycles Max Delay 267 cycles Max Delay 498 cycles Max Delay 498 cycles Total Delay for Uniform Traffic (cycles) Total Delay for ermutation Traffic (cycles)

23 esults with SLASH-2 We experimented with the SLASH-2 benchmark to confirm the performance benefits brought by the fuzzy flow regulation system. Since in a real system the performance is measured by CI, we choose to report the results for the network throughput here. Throughput (packet/cycle) No egulation Static egulation Fuzzy egulation FFT Water Barnes Ocean 23

24 Conclusion The central idea of this work is to make network status aware flow regulation through a fuzzy logic approach. On GEMS, our experiments with both synthetic traffic and SLASH-2 benchmark traces show that the fuzzy regulation can flexibly adjust regulation strength on demand. As a result, it makes more effective use of the system interconnect, achieving significant improvement in average packet delay and throughput. 24

25 ACKNOLEDGEMENT The research is sponsored in part by Intel Corporation through a research gift. 25

26 Thank you very much! Q & A 26