ZLAN-026 ZL50400/02/04/05/07/08/09/10/11 Processor Interface

Transcription

1 ZL50400/02/04/05/07/08/09/10/11 Processor Interface Contents 1.0 Introduction Processor Interface Bootstraps Configuration Registers Direct Access Registers Write Indirect Register In 16-Bit Mode In 8-Bit Mode In Serial Only or Serial+MII Modes Read Indirect Register In 16-Bit Mode In 8-Bit Mode In Serial Only or Serial+MII Modes Device Control & Status Registers Enabling Switching of Packets Device ID Control of Ethernet Frames to CPU Device Interrupts Device Time-out Detection EEPROM Usage Processor Ethernet Frame Frame Tag Frame Transmitted by the CPU Transmitting Frame Status Definitions Steps To Transmit Ethernet Frame In 8/16-Bit and SSI-Only Modes In Serial+MII or MII Only Modes Ethernet Frame Received by the CPU Receiving Frame Status Definitions Steps To Receive Ethernet Frame In 8/16-Bit and Serial Only Mode In Serial+MII or MII Only Modes Processor Control Command Frame Command Engine Steps To Transmit Control Command Steps To Receive Command Response Control Frame Reference Structure Formats of Control Commands Requests From CPU to ZL5040x Responses From ZL5040x to CPU Responses Via Control Frame Buffer Responses Via Control Frame Buffer Sample of Software Introduction June 2006 The purpose of this application note is to describe the ZL5040x processor interface and to provide simple examples that demonstrate how the processor interface operates. The ZL5040x processor interface was designed with simplicity in mind and therefore natively supports Little Endian mode only. This gives the software greater flexibility to restructure data blocks. The ZL5040x processor interface supports four modes: 1. 8-bit data bus bit data bus 3. 1-bit serial (managed/unmanaged) 4. 1-bit serial + MII mode. The unmanaged 1-bit serial interface supports an optional I 2 C EEPROM for register configuration during bootup. The processor interface provides three basic operations: 1. Configuration register access 2. Ethernet frame access 3. Control command frame access Figure 1 ZL5040x Processor Interface 8/16 Bit Interface, Figure 2 ZL5040x Processor Interface - Serial and Figure 3 ZL5040x Processor Interface - Serial + MII below show how the internal blocks accessing the different processor interface of the ZL5040x. 1 Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Copyright All Rights Reserved.

2 Processor W R 3-bit Address Bus 8/16-bit Data Bus ZL5040x Address I/O Data MUX Index Reg 1 (Addr = 1) Index Reg 0 (Addr = 0) Config Data Reg (Addr = 2) CPU Frame Reg (Addr = 3) Command/ Status Reg (Addr = 4) Interrupt Reg (Addr = 5) Control Command 1 Reg (Addr = 6) Control Command 2 Reg (Addr = 7) 16-bit Address 8-bit Data Bus 8/16-bit Data Bus 8/16-bit Data Bus Internal Registers Inderect Access CPU frame CPU frametransmit Receive FIFO FIFO Control Control Command 1 Command 1Transmit Receive FIFO FIFO Control Command 2 Transmit FIFO Interrupt Figure 1 - ZL5040x Processor Interface 8/16 Bit Interface 2

3 Processor Serial Out Serial In Strobe Synchronous Serial Interface 3-bit Address Bus 16-bit Data Bus CS W R ZL5040x Address I/O Data MUX Index Reg 1 (Addr = 1) Index Reg 0 (Addr = 0) Config Data Reg (Addr = 2) CPU Frame Reg (Addr = 3) Command/ Status Reg (Addr = 4) Interrupt Reg (Addr = 5) Control Command 1 Reg (Addr = 6) Control Command 2 Reg (Addr = 7) 16-bit Address 8-bit Data Bus 8/16-bit Data Bus 8/16-bit Data Bus Internal Registers Inderect Access CPU frame CPU frametransmit Receive FIFO FIFO Control Control Command 1 Command 1Transmit Receive FIFO FIFO Control Command 2 Transmit FIFO Interrupt Figure 2 - ZL5040x Processor Interface - Serial 3

4 Tclk Txd Txen Rxd Rxdv Rclk Processor Serial Out Serial In Strobe MII Interface Synchronous Serial Interface 3-bit Address Bus 16-bit Data Bus CS W R ZL5040x Address I/O Data MUX Index Reg 1 (Addr = 1) Index Reg 0 (Addr = 0) Config Data Reg (Addr = 2) Command/ Status Reg (Addr = 4) Interrupt Reg (Addr = 5) Control Command 1 Reg (Addr = 6) Control Command 2 Reg (Addr = 7) 8/16-bit Data Bus 16-bit Address 8-bit Data Bus 8/16-bit Data Bus CPU frame CPU frametransmit Receive FIFO FIFO Internal Registers Inderect Access Control Control Command 1 Command 1Transmit Receive FIFO FIFO Control Command 2 Transmit FIFO Interrupt 2.0 Processor Interface Bootstraps Figure 3 - ZL5040x Processor Interface - Serial + MII The processor interface mode is selected using bootstrap options. External pull-up/down resistors are used to select a configuration. Zarlink recommends the use of 1 KΩ for pull-downs and 10 KΩ for pull-ups. Note: Bootstrap pins cannot share the same external pull-up/down bit data bus TSTOUT[3:1] = bit data bus TSTOUT[11:9] = 001 4

5 3. 1-bit serial + MII TSTOUT[11:9] = 010 The Chip ID for the 1-bit serial interface is selected via TSTOUT[6:4] The debounce feature on the 1-bit serial interface is controlled via TSTOUT[0] - If debounce is enabled, DATAOUT is an open-drain driver, thus, requires an external pull-up resistor - If debounce is disabled, DATAOUT is a totem-pole driver 4. 1-bit serial only TSTOUT[11:9] = 011 The Chip ID for the 1-bit serial interface is selected via TSTOUT[6:4] The debounce feature on the 1-bit serial interface is controlled via TSTOUT[0] - If debounce is enabled, DATAOUT is an open-drain driver, thus, requires an external pull-up resistor - If debounce is disabled, DATAOUT is a totem-pole driver 5. Unmanaged 1-bit serial only TSTOUT[11:9] = 111 An optional EEPROM can be used, and is enabled via TSTOUT[7] The Chip ID for the 1-bit serial interface is selected via TSTOUT[6:4] The debounce feature on the 1-bit serial interface is controlled via TSTOUT[0] - If debounce is enabled, DATAOUT is an open-drain driver, thus, requires an external pull-up resistor - If debounce is disabled, DATAOUT is a totem-pole driver 3.0 Configuration Registers The ZL5040x has many programmable parameters contained in 8-bit configuration registers (also referred to as indirect access registers). The ZL5040x uses direct access registers to read and write to the configuration registers, as follows: 5

6 register write addr=0, data[15:0]=reg_addr[15:0] addr=2, data[15:0]={0,reg_data[7:0]} 16-bit CPU ZL5040x register read addr=0, data[15:0]=reg_addr[15:0] addr=2 {0, reg_data[7:0]}=data[15:0] register write addr=0, data[7:0]=reg_addr[7:0] addr=1, data[7:0]=reg_addr[15:8] addr=2, data[7:0]=reg_data[7:0] 8-bit CPU register read addr=0, data[7:0]=reg_addr[7:0] addr=1, data[7:0]=reg_addr[15:8] addr=2 reg_data[7:0]=data[7:0] ZL5040x register write 1-bit CPU register read Dev ID, addr=0, data[15:0]=reg_addr[15:0] Dev ID, addr=2, data[15:0]=16-bit serial data Dev ID, addr=0, data[15:0]=reg_addr[15:0] Dev ID, addr=2 16-bit serial data=data[15:0] ZL5040x 3.1 Direct Access Registers Figure 4 - Configuration (Indirect) Register Access INDEX_REG0 Width Access Address Used to write the address of the indirect register to be accessed. 8/16-bit W 0 Default: 00 Bit # Name Type Description 16-bit or serial CPU Interface [15:0] INDEX W 16-bit address of the indirect register 8-bit CPU Interface [7:0] INDEX_L W LSB [7:0] of the 16-bit address of the indirect register Register Table 1-0, INDEX_REG0 6

7 INDEX_REG1 Width Access Address Used to write the address of the indirect register to be accessed. 8-bit CPU Interface Only 8-bit W 1 Default: 00 Bit # Name Type Description [7:0] INDEX_H W MSB [15:8] of the 16-bit address of the indirect register Register Table 2-1, INDEX_REG1 DATA_REG Width Access Address Reflects the value of the indirect access register set by INDEX_REG 8/16-bit R/W 2 Default: 00 Bit # Name Type Description 8/16-bit or serial CPU Interface [7:0] DATA R/W 8-bit indirect register data 16-bit CPU Interface Only [15:8] RSVD R/W Reserved Register Table 3-2, DATA_REG CPU_FRAME_REG Width Access Address Used to transmit/receive Ethernet frames via an 8-byte FIFO to/from the CPU MAC. This register (FIFO) is disabled in SSI+MII CPU interface mode. 8/16-bit R/W 3 Default: 00 Bit # Name Type Description 16-bit or serial CPU Interface [15:0] CPU_FRAME W Send Ethernet frame to CPU MAC. Bits [7:0] is even byte, [15:8] is odd byte. R Data sequence specified in Processor Interface application note, ZLAN-26. Receive Ethernet frame from CPU MAC. Bits [7:0] is even byte, [15:8] is odd byte. Data sequence specified in Processor Interface application note, ZLAN-26. Register Table 4-3, CPU_FRAME_REG 7

8 8-bit CPU Interface [7:0] CPU_FRAME W Send Ethernet frame to CPU MAC R Data sequence specified in Processor Interface application note, ZLAN-26. Receive Ethernet frame from CPU MAC Data sequence specified in Processor Interface application note, ZLAN-26. Register Table 4-3, CPU_FRAME_REG (continued) CMD_STATUS_REG Width Access Address CPU interface command status This register is not applicable in SSI+MII, MII-only and Remote/No CPU interface modes. 8/16-bit R/W 4 Default: 00 Bit # Name Type Description 8/16-bit CPU Interface [0] RXBUF_DONE W Set Control Frame Receive buffer ready, after CPU writes a complete frame into the buffer. This bit is self-cleared. RXBUF_RDY R Control Frame receive buffer ready, CPU can write a new frame 1 CPU can write a new control command 0 CPU has to wait until this bit is 1 to write a new control command [1] TXBUF1_DONE W Set Control Frame Transmit buffer1 ready, after CPU reads out a complete frame from the buffer. This bit is self-cleared. TXBUF1_RDY R Control Frame transmit buffer1 ready for CPU to read 1 CPU can read a new control command 1 0 CPU has to wait until this bit is 1 to read a new control command [2] TXBUF2_DONE W Set Control Frame Transmit buffer2 ready, after CPU reads out a complete frame from the buffer. This bit is self-cleared. TXBUF2_RDY R Control Frame transmit buffer2 ready for CPU to read 1 CPU can read a new control command 1 0 CPU has to wait until this bit is 1 to read a new control command [3] TXFIFO_RXDONE W Set this bit to indicate CPU received a whole frame (transmit FIFO frame receive done), and flushed the rest of frame fragment, If occurs. This bit will be self-cleared. TXFIFO_RDY R Transmit FIFO has data for CPU to read [4] RXFIFO_EOF W Set this bit to indicate that the following Write to the Receive FIFO is the last one. This bit will be self-cleared. RXFIFO_SPOK R Receive FIFO has space for incoming CPU frame Register Table 5-4, CMD_STATUS_REG 8

9 [5] RXFIFO_REALIGN W Set this bit to re-start the data that is sent from the CPU to Receive FIFO (re-align). This feature can be used for software debug. For normal operation must be '0'. TXFIFO_EOF R Transmit FIFO End Of Frame This bit will be deasserted during packet reception and will be asserted at the EOF time. Afterwards, this bit will remain asserted until receiving next packet. This means bit [5] is only meaningful when bit [3] (TXFIFO_RDY) is asserted. Bit [3] Bit [5] Result 0 0 Invalid 0 1 No frame 1 0 Frame 1 1 EOF [7:6] RSVD R/W Reserved 16-bit CPU Interface Only [15:8] RSVD R/W Reserved Register Table 5-4, CMD_STATUS_REG (continued) INT_REG Width Access Address Interrupt sources 8/16-bit R 5 Default: N/A Bit # Name Type Description 8/16-bit CPU Interface [0] INT_CPU_FRAME R Ethernet frame interrupt. Ethernet Frame receive buffer has data for processor to read [1] INT_CTL_BUF1 R Control frame 1 interrupt. Control Frame receive buffer 1 has data for processor to read [2] INT_CTL_BUF2 R Control frame 2 interrupt. Control Frame receive buffer 2 has data for processor to read [6:3] RSVD R Reserved [7] INT_CHIP_RESET R Device Timeout Detected interrupt Note: This bit is not self-cleared. After reading, the CPU has to clear the bit writing 0 to it. 16-bit CPU Interface Only [15:8] RSVD R/W Reserved Register Table 6-5, INT_REG 9

10 CTL_FRAME_BUF1 Width Access Address Used to transmit/receive control frames 8/16-bit R/W 6 Default: 00 Bit # Name Type Description 16-bit or serial CPU Interface [15:0] CTL_BUF1 W Send control frame to command engine. Bits [7:0] is even byte, [15:8] is odd byte. R Control frame format specified in Processor Interface application note, ZLAN-26. Receive control frame from command engine. Bits [7:0] is even byte, [15:8] is odd byte. Control frame format specified in Processor Interface application note, ZLAN bit CPU Interface [7:0] CTL_BUF2 W Send control frame to command engine R Control frame format specified in Processor Interface application note, ZLAN-26. Receive control frame from command engine Control frame format specified in Processor Interface application note, ZLAN-26. Register Table 7-6, CTL_FRAME_BUF1 CTL_FRAME_BUF2 Width Access Address Used to receive control frames 8/16-bit R 7 Default: 00 Bit # Name Type Description 16-bit or serial CPU Interface [15:0] CTL_BUF2 R Receive control frame from command engine. Bits [7:0] is even byte, [15:8] is odd byte. Control frame format specified in Processor Interface application note, ZLAN-26. Register Table 8-7, CTL_FRAME_BUF2 10

11 8-bit CPU Interface [7:0] CTL_BUF2 R Receive control frame from command engine 3.2 Write Indirect Register The following sections outline the steps required to write to the configuration registers In 16-Bit Mode Control frame format specified in Processor Interface application note, ZLAN-26. Register Table 8-7, CTL_FRAME_BUF2 (continued) 1. Write the desired register address (16 bit) to INDEX_REG0 (address 0), where the MSb of register address (bit 15) maps to bit 15 of INDEX_REG0 and the LSb of register address (bit 0) maps to bit 0 of INDEX_REG0. 2. Write the desired register data (8 bit) to DATA_REG (address 2), where the MSb of register data (bit 7) maps to bit 7 of DATA_REG, and the LSb of register data (bit 0) maps to bit 0 of DATA_REG. Write 0 s to bit 15 through bit 8 of DATA_REG. NOTE: A special register-write is supported. This allows CPU to write to two consecutive configuration registers in a single write operation. By writing to bit[14] of INDEX_REG0, the CPU can write 16 bits of data to DATA_REG. LSB of DATA_REG is for the 12-bit address specified in INDEX_REG0 and MSB of DATA_REG is for the (address + 1). As well, an incremental write is supported. This allows the CPU to write to the configuration registers incrementally. By writing to bit[15] of INDEX_REG0, the CPU only has to set the start address of the 12-bit configuration register address set and then CPU can continuously write to DATA_REG INC R/W SP W Reserved In 8-Bit Mode Figure 5 - INDEX_REG0 Special Read/Write Access Support 1. Write the LSB (bit 7 to bit 0) of desired register address (16 bit) to INDEX_REG0 (address 0), where bit 7 of register address maps to bit 7 of INDEX_REG0 and bit 0 of register address maps to bit 0 of INDEX_REG0. 2. Write the MSB (bit 15 to bit 8) of desired register address (16 bit) to INDEX_REG1 (address 1), where bit 15 of register address maps to bit 7 of INDEX_REG1 and bit 8 of register address maps to bit 0 of INDEX_REG1. 3. Write the desired register data (8 bit) to DATA_REG (address 2), where the MSb of register data (bit 7) maps to bit 7 of DATA_REG, the LSb of register data (bit 0) maps to bit 0 of DATA_REG In Serial Only or Serial+MII Modes 12 Bit Register Address 1. Issue the Write Command with 3-bit Device_ID 1, 3-bit Addr = 0 (INDEX_REG0), and 16-bit Data = the desired register address. The LSb of Data (bit 0) maps to bit 0 of INDEX_REG0 and the MSb of Data (bit 15) maps to bit 15 of INDEX_REG0 1. The use of Device_ID in serial mode serves as an in-band "chip select". In other modes, this chip select function is achieved using a separate pin (P_CS#). 11

12 2. Issue the Write Command with 3-bit Device ID, 3-bit Addr = 2 (DATA_REG), and 16-bit Data = the desired register data. The bit 0 of Data maps to bit 0 of DATA_REG and the bit 7 of Data maps to bit 7 of DATA_REG. Write 0 s to bit 8 through bit 15 of DATA_REG. NOTE: A special register-write is supported. This allows CPU to write to two consecutive configuration registers in a single write operation. By writing to bit[14] of INDEX_REG0, the CPU can write 16 bits of data to DATA_REG. LSB of DATA_REG is for the 12-bit address specified in INDEX_REG0 and MSB of DATA_REG is for the (address + 1). As well, an incremental write is supported. This allows the CPU to write to the configuration registers incrementally. By writing to bit[15] of INDEX_REG0, the CPU only has to set the start address of the 12-bit configuration register address set and then CPU can continuously write to DATA_REG. 3.3 Read Indirect Register In 16-Bit Mode 1. Write the desired register address (16 bit) to INDEX_REG0 (address 0), where the MSb of register address (bit 15) maps to bit 15 of INDEX_REG0 and the LSb of register address (bit 0) maps to bit 0 of INDEX_REG0. 2. Read the register data (8 bit) from DATA_REG (address 2), where the MSb of register data (bit 7) maps to bit 7 of DATA_REG, and the LSb of register data (bit 0) maps to bit 0 of DATA_REG; bit 15 to bit 8 of DATA_REG are unused. NOTE: An incremental read is supported. This allows the CPU to read from the configuration registers incrementally. By writing to bit[15] of INDEX_REG0, the CPU only has to set the start address of the 12-bit configuration register address set and then CPU can continuously read from DATA_REG In 8-Bit Mode 1. Write the LSB (bit 7 to bit 0) of desired register address (16 bit) to INDEX_REG0 (address 0), where bit 7 of register address maps to bit 7 of INDEX_REG0 and bit 0 of register address maps to bit 0 of INDEX_REG0. 2. Write the MSB (bit 15 to bit 8) of desired register address (16 bit) to INDEX_REG1 (address 1), where bit 15 of register address maps to bit 7 of INDEX_REG1 and bit 8 of register address maps to bit 0 of INDEX_REG1. 3. Read the register data (8 bit) from DATA_REG (address 2), where the MSb of register data (bit 7) maps to bit 7 of DATA_REG, the LSb of register data (bit 0) maps to bit 0 of DATA_REG In Serial Only or Serial+MII Modes 1. Issue the Write Command with 3-bit Device_ID, 3-bit Addr = 0 (INDEX_REG0), and 16-bit Data = the desired register address. The LSb of Data (bit 0) maps to bit 0 of INDEX_REG0 and the MSb of Data (bit 15) maps to bit 15 of INDEX_REG0 2. Issue the Read Command with 3-bit Device ID, 3-bit Addr = 2 (DATA_REG). 3. Read back from Serial Out pin 16-bit Data. The upper 8 bit of Data are 0 s, the bit 7 of Data is the MSb of DATA_REG and the bit 0 is the LSb of DATA_REG The bit 0 of Data maps to bit 0 of DATA_REG and the bit 7 of Data maps to bit 7 of DATA_REG. Bit 8 to bit 15 of DATA_REG are unused. NOTE: An incremental read is supported. This allows the CPU to read from the configuration registers incrementally. By writing to bit[15] of INDEX_REG0, the CPU only has to set the start address of the 12-bit configuration register address set and then CPU can continuously read from DATA_REG. 12

13 4.0 Device Control & Status Registers Validation of CPU interface access to the configuration registers can be done by reading register DA (address 0xFFF) and comparing to expected value of 0xDA. DA Bits [7:0] Always return DA The bootstrap settings sampled by the ZL5040x after reset can be read via registers BOOTSTRAP0~3 (address 0x0E80~3) BT3 BT2 BT1 BT0 BOOTSTRAP0~3 Bits [15:0]: Bits [23:16]: Bits [25:24]: Bits [31:26]: Bootstrap value from TSTOUT[15:0]: Bit [6:0]: TSTOUT[6:0] Bit [8:7]: Invert of TSTOUT[8:7] Bit [9]: TSTOUT[11] Bit [10]: TSTOUT[9] Bit [11]: TSTOUT[10] Bit [14:12]: TSTOUT[14:12] Bit [15]: Always 0 Bootstrap value from M[7:0]_TXEN Bit [16]: M0_TXEN Bit [17]: M1_TXEN... Bit [23]: M7_TXEN Bootstrap value from M9_TXEN, M9_TXER Reserved During reset, a BIST is executed with the results shown in register DCR (address 0x0F01). The BIST test can also be manually invoked or a soft reset issued via register GCR (address 0x0F00). The only difference between a soft reset (via GCR[3]) and a hard reset (via RESIN#) is that the bootstrap pins are not sampled on a soft reset. Other information is available in DCR to validate the Chipset Revision and Product ID. GCR Bit [2]: Start BIST (Default = 0) Write 1 followed by 0 to start the device s built-in self-test. The result is found in the DCR register. Bit [3]: Soft Reset (Default = 0) Write 1 to reset chip 13

14 DCR Bit [2]: Bit [3]: Bits [5:4]: Bits [7:6]: 1: BIST in progress 0: BIST not running 1: RAM Error 0: RAM OK Device Signature (see Data Sheet) Revision (see Data Sheet) 4.1 Enabling Switching of Packets On bootup in managed mode, the ZL5040x will be in an idle state with all configuration registers set to their default values. In order to start switching of packets, the switch must be told when initialization is complete. This is done via register GCR (address 0x0F00), bit [4]. On bootup in unmanaged mode, the ZL5040x will immediately begin switching packets based on the default settings of the configuration registers, or if using the optional EEPROM, based on the EEPROM values. GCR Bit [4]: Initialization Completed (Default = 0) This bit is reserved in unmanaged mode. In managed mode, the CPU writes this bit with 1 to indicate initialization is completed and ready to forward packets. The 0' to '1' transition will toggle TSTOUT[2] from low to high. 4.2 Device ID The device ID is used to uniquely identify the ZL5040x device, and is configured via register DEVICE (address 0x060A), bits [7:5]. DEVICE Bits [7:5]: Device ID (Default 0x0) 4.3 Control of Ethernet Frames to CPU By default in managed mode, the ZL5040x allows Ethernet data frame to the CPU. To disable Ethernet frames from going to the CPU, the following must be done: 1. Remove the CPU from all VLANs if in port-based VLAN mode, remove the CPU port from all the port's bitmaps - set PVMAPn_1[0] = '0' for all ports if in tagged-based VLAN mode, don't include the CPU port in any VLAN ID port bitmap 2. Force BPDU packet as multicast packet set PVMODE[5] = '1' 3. Disable IP Multicast set FEN[4] = '1' (default setting) 14

15 4.4 Device Interrupts Interrupts notification from the ZL5040x to the CPU is via pin P_INT, which is the OR d result of register INT_REG. There are four sources of interrupt: 1. Ethernet frame interrupt (INT_REG, bit [0]) 2. Control command frame buffer 1 interrupt (INT_REG, bit [1]) 3. Control command frame buffer 2 interrupt (INT_REG, bit [2]) 4. Device time-out detected interrupt (INT_REG, bit [7]) Each of the above interrupts can be masked via register INT_MASK0 (address 0x0306). As well, the polarity of P_INT is controlled via register DEVICE (address 0x060A), bit [1]. INT_MASK0 Bit [0]: Bit [1]: Bit [2]: Bits [6:3]: Bit [7]: CPU frame interrupt. CPU frame buffer has data for CPU to read Control Command 1 interrupt. Control Command Frame buffer1 has data for CPU to read Control Command 2 interrupt. Control command Frame buffer2 has data for CPU to read Reserved Device Timeout Detected interrupt DEVICE Bit [1]: CPU Interrupt Polarity 0: Negative Polarity 1: Positive Polarity (Default) 4.5 Device Time-out Detection The Zl5040x has the capability to detect device operation error and to either report the error to the CPU or to reset the device. The cause of the operation error can be caused by alpha particle, power noise, glitch and other misc. environmental effects. The ZL5040x supports a state machine monitoring block which can trigger a reset or interrupt if any state machine is determined to be stuck in a non-idle state for more than 5 seconds. The automatic time-out reset feature can be either enabled or disabled. This is controlled via a bootstrap pin, TSTOUT[12]. When enabled, a reset will be generated when a time-out is detected. If disabled, an interrupt is generated to the CPU, if the interrupt is unmasked, to indicate an error has been detected. Refer to the Programming Timeout Reset, ZLAN-041, for more details. 4.6 EEPROM Usage If in unmanaged mode, an option EEPROM can be used to load up some of the configuration registers (indirect registers) with initial values at reset. The EEPROM can be programmed by the switch using register GCR (address 0x0F00). Setting bit [0] or [1] will initiate an I 2 C access to write the contents of some select configuration registers to the EEPROM. The only difference between these two bits is that bit [1] will invoke a reset after the write. 15

16 GCR Bit [0]: Store configuration (Default = 0) Write 1 followed by 0 to store configuration into external EEPROM Bit [1]: Store configuration and reset (Default = 0) Write 1 to store configuration into external EEPROM and reset chip The EEPROM must also be loaded with a checksum value to allow the switch to confirm the contents when reading. This checksum is stored in register CHECKSUM (address 0x060B). CHECKSUM Bits [7:0]: Checksum content (Default 0) Status of the read/write access to the EEPROM can be monitored via register DCR (address 0x0F01). DCR Bit [0]: Bit [1]: 1: Busy writing configuration to I²C 0: Not busy (not writing configuration to I²C) 1: Busy reading configuration from I²C 0: Not busy (not reading configuration from I²C) Details of general EEPROM usage can be found in application note Ethernet Switch EEPROM Operation, ZLAN Processor Ethernet Frame The CPU interface is also responsible for receiving and transmitting standard Ethernet frames to and from the processor. If FTAG_MODE is enabled for the CPU port (default), the 8-byte FTAG header is also part of the Ethernet frame. In serial+mii mode, receiving and transmitting Ethernet frames to and from the processor is the same as regular frame reception and transmission on any other 10/100M port. The ZL5040x will act as PHY to provide both RXCLK and TXCLK to the CPU. The CPU will use these two clocks to receive and transmit Ethernet frames. In 8/16-bit and serial-only modes, receiving and transmitting Ethernet frames to and from the processor is done using direct access registers. Register CPU_FRAME_REG is used as a FIFO between the CPU and the MAC, with CPU_STATUS_REG indicating the state of the FIFO (See Direct Access Registers on page 6). 5.1 Frame Tag In serial+mii mode, the ZL5040x CPU port supports 3 different modes, as set by ECR4P9 (address 0x0091), bits [4:3]. 1. Normal Mode ( 00 ): In this mode, the packet sent on the CPU MII interface is a standard Ethernet packet. 2. Frame Tag Insertion ( 01 ): A 2-byte frame tag is inserted before the start of the standard Ethernet packet. 3. Frame Tag + Padding Insertion ( 11 ): A 2-byte frame tag plus 6-byte padding is inserted before the start of the standard Ethernet packet. 16

17 ECR4P9 Bits [4:3]: Enable insertion of 2-byte CPU information in CPU frame packet in Serial + MII mode 00: No information is inserted 01: Insert 2-byte of CPU information 10: Reserved 11: Insert 6-byte of padding + 2-byte of CPU information (Default) In port-based VLAN mode, the CPU MII interface must be in No information is inserted mode (ECR4P8[4:3]='00'). In tagged-based VLAN mode, the CPU MII interface supports all three modes (0,2,8 bytes insertion). 5.2 Frame Transmitted by the CPU The frame is transmitted in little endian mode. 4th Byte Transmitted 1st Byte Transmitted Transmitting Frame Status Ethernet Header 0 0 [13:0] Frame Length b 1 [63:48] Destination Info 0 Destination MAC Address Source MAC address Destination MAC Address Source MAC Address VLAN Tag Length/ Type Ethernet Data A) DATA Any Bytes FCS Last Byte Transmitted FCS Figure 6 - Frame Transmitted by the CPU Optional. In 8/16-bit or serial only mode, the ZL5040x will NOT check the FCS of the incoming frame, it will assume that the frame coming in is good all the time (the CPU can send in this field). In MII mode, the ZL5040x will check the FCS of the incoming frame. 17

18 5.2.1 Transmitting Frame Status Definitions [13:0] Frame Length: the number of bytes including Ethernet header, data, padding, and FCS [14] Frame OK: Always write 1. [47:15] Not used (pad with any data) [63:48] Destination Port Info: Used to allow the CPU to override the search engine and specify the destination port info. BIT[63] Substitute frame source address when the frame depart from the device. 0: Use source MAC address in frame 1: Replace source MAC address with CPU address of destination port BIT[62:59] Priority and drop precedence assigned to this frame (Bit[62] is drop precedence). Enter 0x0 to have the switch determine priority and drop precedence. BIT[58] Destination mode. Determine how to decode BIT[57:48]. 0: destination port id specified by BIT [57:48]. BIT[57:55] Shall be all zero. BIT[54:52] Destination device ID. Should be equal to local device ID (register 0x60A[7:5]) and the device ID should be a non-0x0 value. BIT[51:48] Destination port ID. Combined with the device ID (BIT[54:52]) information, the device can pass the frame to the specified device and forward to the specified port. Enter 0x1F to have the switch determine the destination port(s). 1: destination port map specified by BIT [57:48]. BIT[57:48] Destination port map. CPU can send a frame to multiple port at the same time. The map is only local significant Steps To Transmit Ethernet Frame In 8/16-Bit and SSI-Only Modes P_DATA0 A H G F E D C B A MSB byte 0 LSB B C D byte 1 A B C D E F G H byte 2 I J K L M O P Q PHY P O N M L K J I byte 1 P_DATA7 E F G H SWITCH P_DATA8 I J CPU K L M N O P_DATA15 P Figure 7 - Transmitting Byte 16-Bit CPU Bus Little Endian 18

19 P_DATA0 A byte 1 A B C D E F G H PHY H G F E D C B A MSB byte 0 SWITCH LSB B C D E F CPU G P_DATA7 H Figure 8 - Transmitting Byte 8-Bit CPU Bus Little Endian H G F E D C B A MSB byte 0 LSB byte 1 A B C D E F G H byte 2 I J K L M O P Q PHY P O N M L K J I byte 1 Serial Data (A...P) SWITCH CPU Figure 9 - Transmitting Byte Single-Bit Serial CPU Bus Little Endian 1. Poll COMMAND&STATUS[4] until it is asserted. 2. Write Transmit Frame Status (8 bytes) (described in Section 5.2.1, Transmitting Frame Status Definitions on page 18) to CPU_ FRAME_REG. 3. Poll COMMAND&STATUS[4] again (to verify that FIFO has space for incoming data) until it is asserted. 4. Once COMMAND&STATUS[4] is asserted, one can write up to 16 bytes of data at a time. In 8-bit mode, write each byte in increasing order to CPU_ FRAME_REG [7:0]. (See CPU Frame General Structure for Memory Request section in Section 6.5, Formats of Control Commands on page 25 for further details on writing in increasing order). In 16-bit mode, write 2 bytes in increasing order; write even bytes in CPU_FRAME_REG [7:0] and odd bytes in CPU_FRAME_ REG [15:8]. After the 16 bytes are written to the FIFO, the frame engine transfers the data from the FIFO to the external frame data buffer. 19

20 5. Repeat step 3 and 4 until the whole Ethernet frame is complete. Pad the frame with 0 s so the frame aligns to an 8-byte boundary. 6. Poll COMMAND&STATUS[4] until it is asserted. 7. Write h0010 (16-bit mode) or h10 (8-bit mode) to COMMAND&STATUS to indicate the end of the frame In Serial+MII or MII Only Modes Same as transmitting standard Ethernet frame on any other port, except that the 2-byte Frame Tag header is required if mode is enabled for the CPU port. 5.3 Ethernet Frame Received by the CPU The frame is read in little endian mode. 4th Byte Transmitted 1st Byte Transmitted Receiving Frame Status Ethernet Header [31] TAG out [30] TAG in [29:14] VLAN ID [13:0] Frame Length [63:48] Source Info 0 Destination MAC Address Source MAC address Destination MAC Address Source MAC Address VLAN Tag Length/ Type Ethernet Data DATA Any Bytes FCS FCS Last Byte Transmitted Figure 10 - Frame Read by the CPU When frame has a VLANTAG. 20

21 5.3.1 Receiving Frame Status Definitions [13:0] Frame Length: the number of bytes including Ethernet header, data, padding, and FCS [29:14] VLAN ID: 16 LSB of the VLAN tag (tag control information) [30] Tag In = 0: the frame has no tag; Tag In = 1: the frame has a tag [31] Tag Out = 0: not used by the CPU (ignore data) [63:48] Source Info: Bit[63:62]: No use. Bit[61:58]: Classified priority result by search engine. Bit[57:55]: Source device ID. Bit[54:52]: No use. Bit[51:48]: Source port ID Steps To Receive Ethernet Frame In 8/16-Bit and Serial Only Mode P_DATA0 A H G F E D C B A MSB byte 0 LSB B C D byte 2 byte 1 P O N M L K J i H G F E D C B A PHY P O N M L K J I byte 1 P_DATA7 E F G H SWITCH P_DATA8 I J CPU K L M N O P_DATA15 P Figure 11 - Receiving Byte 16-Bit CPU Bus Little Endian 21

22 P_DATA0 A byte 1 H G F E D C B A PHY H G F E D C B A MSB byte 0 LSB B C D E F CPU SWITCH P_DATA7 G H Figure 12 - Receiving Byte: 8-Bit CPU Bus Little Endian H G F E D C B A MSB byte 0 LSB byte 2 byte 1 P O N M L K J i H G F E D C B A PHY P O N M L K J I byte 1 Serial Data (P...A) SWITCH CPU Figure 13 - Receiving Byte Single-Bit Serial CPU Bus Little Endian 1. Wait for a hardware interrupt. Read interrupt register (direct register 5). When bit 0 is set, it indicates an Ethernet frame waiting is asserted. Interrupt is de-asserted when first byte of frame is read out. The interrupt can be dynamically masked when the CPU is busy and does not want to be interrupted. The register INT_MASK0 programs the mask. 2. Read 8 bytes of Receive Frame Status/ Ethernet frame (see Section 5.3.1, Receiving Frame Status Definitions on page 21). In 8-bit mode, each byte is read out in increasing order from CPU_FRAME_REG [7:0]. In 16-bit mode, every 2 bytes are read out in increasing order; even bytes are read out from CPU_FRAME_REG[7:0] and odd bytes from CPU_FRAME_REG [15:8]. 3. Poll COMMAND&STATUS[3] until asserted. 4. Read COMMAND&STATUS[5]; if asserted, the last 8 bytes needs to be read out (step 5), otherwise, repeat steps 2 and 3. 22

23 5. Read last 8 byte of Ethernet frame. 6. Write h0008 (16-bit mode) or h08 (8-bit mode) to COMMAND&STATUS to indicate the end of the frame In Serial+MII or MII Only Modes Same as receiving standard Ethernet frame on any other port, except that the 2-byte Frame Tag header is present if mode is enabled for the CPU port. 6.0 Processor Control Command Frame Control commands can be sent between the CPU and the ZL5040x device using a proprietary Control Command frame format. These proprietary commands are related to such tasks as statistics collection, MAC address learning, aging, etc. All Control Commands have a 40-byte long block reference model; this does not imply, however, that they must contain 40 bytes. If there is no data to be transmitted or read, the operation can be terminated. An 8-byte boundary must be respected. Please refer to Section 6.5, Formats of Control Commands on page 25 or the format of Control Commands. 6.1 Command Engine The command engine acts as a proxy of the CPU. It receives a command from the CPU via a control command frame, decodes it, and executes the command. There are several types of control commands that are used to send and receive information to and from the ZL5040x. The types of control frames from the CPU to the ZL5040x are: 1. Memory Read/Write Request 2. Learn/Delete/Search Unicast MAC Address Request 3. Learn/Delete/Search Multicast MAC Address Request 4. Learn/Delete/Search IP Multicast Address Request There are two types of control frames from the ZL5040x to the CPU: interrupt frames and response frames. The types of interrupt frames from the ZL5040x to the CPU are: 1. Statistic Counter Roll-over Interrupt 2. Learn Unicast MAC Address Interrupt 3. Delete Unicast MAC Address Interrupt The types of response frames from the ZL5040x to the CPU are: 1. Read completed with data 2. Delete Unicast MAC Address (Response from SE when CPU issued Learn Multicast MAC request and no RAM space is available for storage) 3. Delete Multicast MAC Address (Response from SE when CPU issued Learn Multicast MAC request and no RAM space is available for storage) 4. Delete IP Multicast Address (Response from SE when CPU issued Learn IP Multicast request and no RAM space is available for storage) 5. Response to Search Unicast MAC Address 6. Response to Search Multicast MAC Address 7. Response to Search IP Multicast Address 23

24 6.2 Steps To Transmit Control Command 1. Poll COMMAND&STATUS[0] until asserted. 2. Write 40 bytes of Control Command. In 8-bit mode, write each byte in increasing order to CONTROL FRAME BUFFER1 ACCESS REGISTER [7:0]. In 16-bit mode, write 2 bytes in increasing order; write even bytes in CONTROL FRAME BUFFER1 ACCESS REGISTER [7:0], and odd bytes in CONTROL FRAME BUFFER1 ACCESS REGISTER [15:8]. Note: It is not necessary to finish writing the complete 40 bytes of Control Command. As long as the data portion of the Control Command is written, transmission can stop because writing h0001 (16-bit mode) or h01 (8-bit mode) to COMMAND&STATUS indicate end of the Command. 3. To transmit another control command start from step Steps To Receive Command Response 1. Wait a hardware interrupt. Read interrupt register (direct register 5). When bit 1 is set, it indicates a command frame 1 waiting is asserted. When bit 2 is set it indicates a command frame 2 is asserted. Interrupt is deasserted when first byte of frame is read out. The interrupt can be dynamically masked when the CPU doesn t want to be interrupted. The register INT_MASK0 programs the mask. 2. Poll COMMAND & STATUS [1] / COMMAND & STATUS [2] until asserted. 3. Read 40 bytes of Control Command. In 8-bit mode, each byte is read out in increasing order form CONTROL FRAME BUFFER1 ACCESS REGISTER[7:0]/CONTROL FRAME BUFFER2 ACCESS REGISTER[7:0]. In 16- bit mode, every 2 bytes are read out in increasing order; even bytes are read out from CONTROL FRAME BUFFER1 ACCESS REGISTER[7:0]/ CONTROL FRAME BUFFER2 ACCESS REGISTER[7:0], and odd bytes are read out from CONTROL FRAME BUFFER1 ACCESS REGISTER[15:8]/ CONTROL FRAME BUFFER2 ACCESS REGISTER[15:8]. Note: It is not necessary to finish reading out the complete 40 bytes of Control Command, as long as the data portion of the Control Command is read out, because writing h0002/ h0004 (16- bit mode) or h02/ h04 (8-bit mode) to COMMAND&STATUS indicates end of the Command. 6.4 Control Frame Reference Structure 8 th byte 7 th byte 6 th byte 5 th byte 4 th byte 3 rd byte CMD1 CMD0 16 th byte 15 th byte 14 th byte 13 th byte 12 th byte 11 th byte 10 th byte 9 th byte 24 th byte 23 rd byte 22 nd byte 21 st byte 20 th byte 19 th byte 18 th byte 17 th byte 32 nd byte 31 st byte 30 th byte 29 th byte 28 th byte 27 th byte 26 th byte 25 th byte 40 th byte 39 th byte 38 th byte 37 th byte 36 th byte 35 th byte 34 th byte 33 rd byte An empty box represents inconsequential data in the frame. If the empty box is in the middle of the data, the data must be read or sent whether the data is relevant or not. If only empty boxes follow the data, then the transmission of the frame (block) may be suspended, as far as the 8-byte boundary is respected. 24

25 6.5 Formats of Control Commands Requests From CPU to ZL5040x (1,2) CPU Frame General Structure For Memory Request FRAME SIZE ADDR CMD1 CMD0 Data7 Data6 Data5 Data4 Data3 Data2 Data1 Data0 Data15 Data14 Data13 Data12 Data11 Data10 Data9 Data8 Data23 Data22 Data21 Data20 Data19 Data18 Data17 Data16 Data 31 Data30 Data29 Data28 Data27 Data26 Data25 Data24 CMD0 [7:4] Command Code 0001 Memory Read Request 0010 Memory Write Request CMD0 [3:0] and CMD1 [7:0] Select the memory to be read/ written. See Memory Type Select. ADDR SIZE 24-bit memory address for read/write operation. The memory will be read or written in incremental mode from this address (See Internal Memory Addresses and 256 KB Buffer Memory Address for memory start and end address) The memory has a 64-bit bus, so each address represents a 8-byte entry. Memory burst size in 8 byte increments Read/Write 8 bytes Read/Write 16 bytes Read/Write 24 bytes Read/Write 32 bytes FRAME [6:0] The response frame will carry the same frame number. In this way the CPU can track the response. This number can be any from 00h to 7Fh. When writing data to the memory, it is not mandatory to identify the frame, as there is no response from the switch. DATA0~31 Note: Up to 32 bytes of data for write operation When writing a memory read request, the command can be finished before data 0. To indicate end of the command, COMMAND & STATUS[0] must be set. 25

26 Memory Type CMD0 [3:0] CMD1 [7:0] Memory Type Statistic Counter Memory Multicast Queue Allocation Table KB Internal Memory Buffer Manager Memory Rate Control Table Table 1 - Memory Type Select Memory Map Memory Type Start Address End Address Notes Statistic Counter Memory 0x x00004F See Statistic Counter Memory on page 27 Multicast Queue Allocation Table 0x x00001F See Multicast Queue Allocation Table on page KB Internal Memory 0x x007FFF See 256 KB Internal Memory on page 28 Buffer Manager Memory 0x x0000FF See Buffer Manager Memory on page 28 Rate Control Table 0x x00000F See Rate Control Table on page 28 Table 2 - Internal Memory Addresses 26

27 Statistic Counter Memory Statistic Counter Memory See Table Below Address 0x00 to 0x07 Address 0x08 to 0x0F 10/100 Port 0 10/100 Port 1 Address 0x38 to 0x3F Address 0x40 to 0x47 Address 0x48 to 0x4F 10/100 Port 7 RSVD Uplink port bit 63 bit 0 Figure 14 - Statistic Counter Memory Each port has 30 statistic counters. The CPU can read the counters content reading the statistic memory. Following are the counters for each port and the format when read out through the processor interface. Byte 7 Byte 6 Byte 5 Byte 4 Byte 3 Byte 2 Byte 1 Byte 0 0 C[2] C[1] C[0] 1 C[5] C[4] C[3] 2 C[7] C[6] 3 C[11] C[10] C[9] C[8] 4 C[15] C[14] C[13] C[12] 5 C[19] C[18] C[17] C[16] 6 C[24] C[23] C[22] C[21] C[20] 7 C[29] C[28] C[27] C[26] C[25] Table 3 - Statistic Counter Memory Format for Each Port C[0] Byte sent C[15] Oversize frames (frames > max. frame size, or frames >1522B but <= BUF_LIMIT with CRC error) C[1] Unicast frame sent C[16] Frames with length between 128 to 255 bytes C[2] Frame transmission failure C[17] Frames with length between 256 to 511 bytes C[3] Flow control frames sent C[18] Frames with length between 512 to 1023 bytes 27

28 C[4] Non-unicast frame sent C[19] Frames with length between 1024 to max. frame size bytes C[5] Bytes received (good or bad) C[20] Fragment C[6] Frame received (good or bad) C[21] Alignment error (also increments "CRC errors" counter) C[7] Total bytes received C[22] Undersize frames (frames < 64B) C[8] Total frames received C[23] CRC errors (note: frames >1522B but <= BUF_LIMIT with CRC error will be counted as "Oversize frames") C[9] Flow Control Frames Received C[24] Short event C[10] Multicast frames received C[25] Collision C[11] Broadcast frame received C[26] Frames dropped because of Tx (egress) queue congestion C[12] Frames with length of 64 bytes C[27] Frames filtered by the search engine C[13] Jabber frames (frames > 6400B size) C[28] Reserved C[14] Frames with length between 65 to 127 bytes C[29] Late Collision Multicast Queue Allocation Table See Programming QoS Registers, ZLAN-42, for details. 256 KB Internal Memory 256KB Internal Memory Start Address End Address Notes 192KB Frame Data Buffer (FDB) 0x x005FFF See Buffer Allocation Frame Control Block (FCB) 0x x0065FF, ZLAN-47, for details. Multicast Queues 0x x006BFF See Programming QoS Registers, ZLAN-42, for details. VLAN Table 0x006C00 0x006FFF See IEEE 802.1Q VLAN Setup, ZLAN-51, for details. MAC Control Table (MCT) 0x x007FFF Internal Use Only Buffer Manager Memory Internal use only. Rate Control Table See Rate Control, ZLAN-33, for details. Table KB Buffer Memory Address 28

29 (3) Unicast MAC Address Learn Structure The CPU can program a new MAC address in the switch MAC address database and define the port or ports associated with the new MAC address. The CPU can also define the status of the new MAC address. If there is no space in the MAC address database, the switch will send back a Delete MAC Address frame with the same frame number. FRAME VLANID1 VLANID0 CMD1 CMD0 PORT STAT MAC5 MAC4 MAC3 MAC2 MAC1 MAC0 CMD0 [7:4] Command Code CMD0 [3:0] and CMD1 [7:0] 0100 Learn MAC address All 0 s VLANID1 [3:0] VLANID0 [7:0] FRAME [6:0] MAC5 MAC0 4 most significant bits of a 12-bit VLAN ID 8 least significant bits of a 12-bit VLAN ID The response frame will carry the same frame number. In this way the CPU can track the response. This number can be any from 00h to 7Fh. MAC address to be learned. The search engine writes the MAC address to the memory. STAT [7:4] All 0 s Static MAC Address (STAT[2:0]=0x3) If MAC address is being learned as a static MAC address, bit [0] in MAC0 (known as MAC multicast bit, thus, always 0 for unicast addresses) is used to secure the port/trunk number to this MAC address. If set to 1, the port number is static, otherwise, if set to 0, the port number can change. STAT [3] STAT [2:0] Mirror this MAC address. Sometimes referred to the "M" bit. MAC status. See Definition for STAT[2:0]. PORT [7:5] All 0 s PORT [4:0] Port/Trunk number. If [4] = '0', [3:0] indicates port number (0-9) If [4] = '1', [2:0] indicates trunk number (0-7) If the learn request is for a static MAC address, bit [0] in MAC0 is used to secure this port/trunk number to the MAC address. 29

30 Invalid entry 000 Dynamic MAC Address 001 ReservedIP Multicast (Not used by the software) 010 Static MAC Address 011 Reserved 100 Static MAC Address with source and destination filter 101 Static MAC Address with source filter 110 Static MAC Address with destination filter 111 Table 5 - Definition for STAT[2:0] Dynamic MAC Address Mac address subject to aging Static MAC Address MAC address not subject to aging. Use bit [0] in MAC0 to secure this address to the port/trunk number. Static MAC Address with source and destination filter All incoming packets to the port associated to this MAC address will be blocked, if the source or destination MAC addresses are equal to this MAC address. Static MAC Address with source filter - All incoming packets to the port associated to this MAC address will be blocked, if the source MAC address is equal to this MAC address. Static MAC Address with destination filter - All incoming packets to the port associated to this MAC address will be blocked, if the destination MAC address is equal to this MAC address. 30

31 (4,5) Unicast MAC Address Search and Delete Structure The CPU can ask to the search engine to perform a MAC address search in the MAC address database or to delete a MAC address from the MAC address database. FRAME VLANID1 VLANID0 CMD1 CMD0 MAC5 MAC4 MAC3 MAC2 MAC1 MAC0 CMD0 [7:4] Command Code 0000 Delete MAC address 0011 Search MAC address CMD0 [3:0] and CMD1 [7:0] All 0 s VLANID1 [3:0] VLANID0 [7:0] MAC5 MAC0 FRAME [6:0] 4 most significant bits of a 12-bit VLAN ID 8 least significant bits of a 12-bit VLAN ID MAC address to be deleted or searched For MAC address delete structure: It is not mandatory to use the frame number, as there is no response from the ZL5040x. For MAC address search structure: enter a number between 0x00 and 0x7F. The response frame will have the same frame number. (6) IP Multicast Address Learn Structure The CPU can program a new IP multicast address. If there is no space in the IP database, the switch will send back a Delete IP Address frame with the same frame number identity. FRAME CMD1 CMD0 PRTMAP1 PRTMAP0 VLANID1 VLANID0 IP3 IP2 IP1 IP0 CMD0 [7:4] Command Code CMD0 [3:0] and CMD1 [7:0] 1100 Learn IP Multicast address All 0 s 31

32 FRAME [6:0] IP3 IP0 VLANID1 [3:0] VLANID0 [7:0] PRTMAP1 & 0 The response frame will carry the same frame number. In this way the CPU can track the response. This number can be any from 00h to 7Fh. 32-bit IP address 4 most significant bits of a 12-bit VLAN ID 8 least significant bits of a 12-bit VLAN ID 9-bit IP Multicast Port Map PRTMAP1 [7:0] - Port 7 to Port 0 PRTMAP0 [7] - Port 9 PRTMAP0 [6:0] - Reserved (7,8) IP Multicast Address Search and Delete Structure The CPU can ask to the search engine to perform a search in the IP multicast address database or to delete an IP multicast address from the IP multicast database. FRAME CMD1 CMD0 VLANID1 VLANID0 IP3 IP2 IP1 IP0 CMD0 [7:4] Command Code 1000 Delete IP address 1011 Search IP address CMD0 [3:0] and CMD1 [7:0] All 0 s IP3 IP0 VLANID1 [3:0] VLANID0 [7:0] FRAME [6:0] 32-bit IP address 4 most significant bits of a 12-bit VLAN ID 8 least significant bits of a 12-bit VLAN ID Delete IP address structure: It is not mandatory to use the frame number, as there is no response from the ZL5040x. Search IP address structure: enter a number between 0x00 and 0x7F to identify the frame. The response frame will have the same number. 32

33 (9) Multicast MAC Address Learn Structure The CPU can program a new multicast MAC address in the switch MAC address database and define the port or ports associated with the new multicast MAC address. If there is no space in the MAC address database, the switch will send back a Delete Multicast MAC Address frame with the same frame number. FRAME VLANID1 VLANID0 CMD1 CMD0 PRTMAP1 PRTMAP0 MAC5 MAC4 MAC3 MAC2 MAC1 MAC0 CMD0 [7:4] Command Code CMD0 [3:0] and CMD1 [7:0] 0101 Learn Multicast MAC Address All 0 s VLANID1 [3:0] VLANID0 [7:0] FRAME [6:0] MAC5 MAC0 PRTMAP1 & 0 4 most significant bits of a 12-bit VLAN ID 8 least significant bits of a 12-bit VLAN ID The response frame will carry the same frame number. In this way the CPU can track the response. This number can be any from 00h to 7Fh. MAC address to be learned. The search engine writes the MAC address to the memory. 9-bit Multicast Port Map PRTMAP1 [7:0] - Port 7 to Port 0 PRTMAP0 [7] - Port 9 PRTMAP0 [6:0] - Reserved 33