System Design Guide for Slave

Transcription

1 System Design Guide for Slave Motor Business Unit Appliances Company 2012/2/15 Rev. 2 Page 1

2 Revision History Revision Date Change Description /3/3 Initial Release /2/15 P1 Changed title from A Guide to Firmware Development for Slave. P3 Added introduction. P5 Clarified the block diagram. Deleted MNM1221 block diagram. P7 Added XSYNC output timing. P9 Changed from SH7065F to SH7216 example. P10 Deleted XINTRX signal connection. P14 Added bus connection. P35 Added occupied blocks. Minor edits. 2012/2/15 Rev. 2 Page 2

3 Introduction This document is to describe an example of system design for the generic slave. Modes of ASIC MNM1221: 2012/2/15 Rev. 2 Page 3

4 System Structure 2012/2/15 Rev. 2 Page 4

5 Block Diagram for RTEX Circuit COM (green and red) 2 Out Port LINK (green) In Port RJ45 RJ45 PHY MII ASIC MNM bit or 8bit XSYNC CPU Input Capture Node Address (MAC-ID) BCD 2digits 25MHz To prevent ESD 8 Reset If software runaway, PHY and ASIC must be reset for safety. Out Port In Port 2012/2/15 Rev. 2 Page 5

6 Timing Signals of MNM1221 In Slave, XSYNC is output at the same time after all Slaves received the frame. Synchronizing the calculation with this signal, all Slaves simultaneity is realized. In Slave, XTXTIM is not available. Connect to VCC. MNM1221 In RUNNING state, negative pulse is output each after all Slaves received. (pulse width: 1.28us) XTXTIM XSYNC XINTRX Negative pulse is output at received. (pulse width: 1.28us) 2012/2/15 Rev. 2 Page 6

7 XSYNC Output Timing At the same time, XSYNCs of all slaves are outputted. Master Slave XINTRX Timing XSYNC Timing Time TX RX RX TX #1 RX TX #2 RX TX #3 RX TX #4 2012/2/15 Rev. 2 Page 7

8 Consideration for Com. Error In communication error, there is a case where the frame is stopped as well as CRC error. In this case, since the frame cannot be received, XSYNC and XINTRX pulse are not output. Master (NC) Slave (Servo) Noise There is also a missing frame. XSYNC or XINTRX Com. period e.g. 0.5ms Missing The timing pulse is not always output. There is also missing case. 2012/2/15 Rev. 2 Page 8

9 Example for SH7216 (Renesas) 2012/2/15 Rev. 2 Page 9

10 Timing Signal Connection ASIC MNM1221 Com. period e.g. 0.5ms CPU SH7216 Timer XSYNC TIOCxA MTU2 Ch x Capture input XINTRX - - Connect Connect XSYNC XSYNC to to a a capture capture input input of of a a timer timer in in the the CPU. CPU. - - At At the the falling falling edge, edge, the the timer timer is is cleared cleared and and the the interrupt interrupt occurs. occurs. 2012/2/15 Rev. 2 Page 10

11 Timing Chart The first XSYNC Com. Period Tc e.g. 0.5ms Missing If continuously 4 times (typical), timeout is detected. XSYNC TIOCxA Change Timeout detected Compare Value TGRB_x C4 C3 C2 Change Change Change Change Timer TCNT_x C1 Capture Value TGRA_x (Not used) Capture INT TGIA_x Timing margin: Tm Compare match INT TGIB_x Compare match INT enable TGIEB in TIER_x Disable Enable Enable in the first capture interrupt. Disable at timeout detected 2012/2/15 Rev. 2 Page 11

12 Interrupt Setting During normal receiving, the input capture interrupt is used. If missing, the compare match interrupt works. Signal Interrupt Period Trigger Interrupt Enabling TGIA_x MTU2 Input Capture e.g. 0.5ms Normal receiving Always enable. TGIB_x MTU2 Compare Match e.g. 0.5ms Frame missing At the first XSYNC, enable in the capture INT. At timeout detected, disable. Notes: - If the frame missing, the previous data is used for the control. This way is the same as CRC error detected. If the data is command position, previous difference of position is used with assuming velocity is constant. - The input capture is used for clearing the timer at interrupt occurrence, and TGRA_x capture value is not used. - Because XSYNC is output in only RUNNING state, in the time from reset-released to the RUNNING state the process should be done by main loop. 2012/2/15 Rev. 2 Page 12

13 Setting Compare Value To prevent both capture and compare-mach INT in normal receiving, the compare-mach INT timing must be delayed a little. Therefore set as follows: C1 C2 C3 C4 Setting Value Tc + Tm 2Tc + Tm 3Tc + Tm 4Tc + Tm Tc: Communication Period Tm: Timing Margin (Set the larger value than the jitter of XSYNC. ) According to receiving situation, set TGRB_x to the following compare value. In capture INT Set C1 (Initialize) In compare-match INT Each time interrupt, increment the compare value such as from C1 to C /2/15 Rev. 2 Page 13

14 Bus Connection ASIC MNM1221 Pull-ups must be installed on all CPU pins except WAIT to ensure level at reset. CPU SH7216 Pull-down D32 D15 D15 D16 D0 D0 A10 A10 A1 A1 A0 +3.3V MODE1 MODE0 XCS XRD CSn RD BUSMODE XWR WRL XWAIT WAIT 2012/2/15 Rev. 2 Page 14

15 Timing Chart at Start-up 2012/2/15 Rev. 2 Page 15

16 COM-LED operation Phase of Firmware Firmware operation T = 1ms Timing at Start-up in Master TX Init frame 0.5ms Confirm Ready State Error check of of Slave information Cyclic Start INIT WAITING PREPARE START RUNNING 1ms When error, set COM-LED to RED OFF Blinking GREEN (0.5s ON, 0.5s OFF) GREEN From here, Start NC calculation XTXTIM TX RX Init-A T = 2ms Init-B Invalid Data (NOP) Real-time Valid Data When Slave NOT established, MNM1221 repeats TX. XSYNC XINTRX State of MNM1221 INITIAL RING-CONFIG READY RUNNING 2012/2/15 Rev. 2 Page 16

17 Timing at Start-up in Slave COM-LED Operation Blinking Green OFF (0.5s ON, 0.5s OFF) Firmware Operation Set Initializing Done Register to 1. Solid Green Get the position of my node data in in RX memory. RX TX Init-A T = 2ms Init-B Real-time The first response data is invalid. (All zero) XINTRX XSYNC MNM1221 State INITIAL CONFIG-A CONFIG-B RUNNING 2012/2/15 Rev. 2 Page 17

18 State-Transition at Start-up COM-LED Off Blinking Green (In initializing) Solid Green (In cyclic communication) Master MNM1221 State INITIAL RING CONFIG READY RUNNING Init-A If slave not established, Init-A is continuously transmitted with 2ms period. Init-B Real-time MNM1221 State INITIAL 2ms CONFIG-B RUNNING e.g. 0.5ms Slave COM-LED Off CONFIG-A Blinking Green (Receivable Init-A, B frame) Solid Green (Receivable Real-time frame) 2012/2/15 Rev. 2 Page 18

19 Example Code 2012/2/15 Rev. 2 Page 19

20 Contents of Example Code The example code has basic functions for slave. The received data is moved into RX buffer in RAM, and TX buffer data is transmitted. An application program using this TX/RX buffer is assumed. Files: Name mnm1221_s.h mnm1221_s.c Description Header File Source File Functions: Name Placing Description init_mnm1221_s() After Releasing Reset Initializing get_state_mnm1221_s() Main Loop Reading MNM1221 state int_sync_mnm1221_s() Interrupt by XSYNC Com. Data Exchange timeout_mnm1221_s() At Timeout Detected Operation at Timeout Variables: Name Placing Description my_rx_buf[] CPU internal RAM RX Buffer my_tx_buf[] CPU internal RAM TX Buffer 2012/2/15 Rev. 2 Page 20

21 Programming by Yourself The followings are not included in the example code. Application Reading MAC-ID COM LED Operation Description Depend on your device. Reading rotary SW at power-on According to MNM1221 state and error, control LED. Remark Including detection of command error. Converting BCD to BIN. Error detection for out of setting range. 2 Colors LED (Green / Red) Timeout Detection Continuous CRC Error Detection In RUNNING state, continuously not received. In RUNNING state, continuously CRC error detected. e.g. Cable breaking down If necessary, added for safety. In motion control, mandatory. Note: When the larger value is set to timeout detection or continuous CRC error detection, noise immunity is improved. However, there is a trade-off that the detection time becomes longer and it might cause problem for safety. After careful consideration, set suitable value for application. If error detected, it is necessary to control for safe side such as motion stop. 2012/2/15 Rev. 2 Page 21

22 Location of Example Code MNM1221 State RX INITIAL CONFIG-A Init-A CONFIG-B Init-B Real-time e.g. 0.5ms RUNNING TX XSYNC Reset init_mnm1221_s() get_state_mnm1221_s() Call periodically in main loop. Main Main Loop XSYNC Interrupt Initializing int_sync_mnm1221_s() At Timeout Detected timeout_mnm1221_s() 2012/2/15 Rev. 2 Page 22

23 Flow Chart 2012/2/15 Rev. 2 Page 23

24 Initializing Name init_mnm1221_s() Description Initializing after Reset Start Initializing Variables Initializing MNM1221 Registers Enable Com. Return 2012/2/15 Rev. 2 Page 24

25 Main Loop Name get_state_mnm1221_s() Description Reading State Start Reading MNM1221 State Return 2012/2/15 Rev. 2 Page 25

26 SYNC Interrupt Name int_sync_mnm1221_s() Description Interrupt by XSYNC of MNM1221 Start The First Time? Yes No Set Readout Pointer CRC Error? Yes Put com. data process using the buffer. No Moving Data from MNM1221 to Buffer Error Count Application Moving Data from Buffer to MNM1221 Return 2012/2/15 Rev. 2 Page 26

27 Operation at Timeout Detected Name timeout_mnm1221_s() Description Initializing at Timeout Detected Start Reset MNM1221 Put the process that makes COM LED display blinking Red. Initializing Application (LED operation) Return 2012/2/15 Rev. 2 Page 27

28 TX and RX Buffer Structure 2012/2/15 Rev. 2 Page 28

29 Com. Buffer Structure (16bit) The following figure shows my_rx_buf[] when 16bit access. Also my_tx_buf[]. Bit 15 Bit 8 Bit 7 Bit 0 my_rx_buf[0] byte1 byte0 my_rx_buf[1] byte3 byte2 my_rx_buf[2] byte5 byte4 my_rx_buf[3] byte7 byte6 my_rx_buf[4] byte9 byte8 my_rx_buf[5] byte11 byte10 my_rx_buf[6] byte13 byte12 my_rx_buf[7] byte15 byte14 byte0 to 15 means the contents of the one data block consisting of 16bytes. 2012/2/15 Rev. 2 Page 29

30 Com. Buffer Structure (8bit) The following figure shows my_rx_buf[] when 8bit access. Also my_tx_buf[]. Bit 7 Bit 0 Bit 7 Bit 0 my_rx_buf[0] byte0 my_rx_buf[8] byte8 my_rx_buf[1] byte1 my_rx_buf[9] byte9 my_rx_buf[2] byte2 my_rx_buf[10] byte10 my_rx_buf[3] byte3 my_rx_buf[11] byte11 my_rx_buf[4] byte4 my_rx_buf[12] byte12 my_rx_buf[5] byte5 my_rx_buf[13] byte13 my_rx_buf[6] byte6 my_rx_buf[14] byte14 my_rx_buf[7] byte7 my_rx_buf[15] byte15 byte0 to 15 means the contents of the one data block consisting of 16bytes. 2012/2/15 Rev. 2 Page 30

31 LED Operation 2012/2/15 Rev. 2 Page 31

32 COM LED Operation Control the COM LED as follows: Normally Return Value of get_state_mnm1221_s() 0x0008 (INITIAL) 0x0004 (CONFIG-A) 0x0002 (CONFIG-B) 0x0001 (RUNNING) COM LED OFF Blinking Green (0.5s ON, 0.5s OFF) Solid Green Error Cause of Error Timeout Continuous CRC Error Cyclic-data Not Receivable (e.g. MAC-ID Unmatched) Out of MAC-ID setting range COM LED Blinking Red (0.5s ON, 0.5s OFF) Solid Red Notes: - Latch an error, and hold the error state until clearing operation even if the cause disappears. - The Solid Red shows that system reset is needed for clearing. - The detection time of Timeout and Continuous CRC Error is typically four communication cycle, and adjust it with careful consideration for safety and noise immunity etc 2012/2/15 Rev. 2 Page 32

33 Modifying the Example Code 2012/2/15 Rev. 2 Page 33

34 Bus Access Definition mnm1221_s.h Set the address value according to your system. If 8bit data bus, delete this line. 2012/2/15 Rev. 2 Page 34

35 Occupied Blocks mnm1221_s.c If not one block, change the number of occupied blocks. (1 block = 16 bytes) 2012/2/15 Rev. 2 Page 35

36 Putting Application mnm1221_s.c Int_sync_mnm1221_s() Replace this test function with your application. The time of the calculation must be shorter than communication period. 2012/2/15 Rev. 2 Page 36

37 LED Operation at Timeout mnm1221_s.c Add the operation of COM LED controlling. 2012/2/15 Rev. 2 Page 37

38 Attention for Cyclic Position I/F 2012/2/15 Rev. 2 Page 38

39 Motion at Communication Error In cyclic position interface device, if the command is held the previous value, that is the same as zero velocity command and causes unstable motion. Therefore, at communication error, the estimated command position on the assumption of constant velocity must be used. Cmd. Update Period Bad Com. Error Good Com. Error Command Position Command Position Previous cmd. held. Time Estimated value used. Time Difference of Cmd. Pos. (Velocity) Fluctuation Difference of Cmd. Pos. (Velocity) Time Stable Time Note: The above description is for momentary communication error. If the error continues over the specific value, the motion must be stopped for safety. 2012/2/15 Rev. 2 Page 39

40 Detection of Data Update Timing When data update period is longer than communication period (e.g. update: 1ms and com.: 0.5ms), recognize the update timing with the case continuously twice OK received and update counter changed. Previous Receiving Current Receiving Update Counter Change Update Timing? OK OK Change Yes OK OK Not change No Either or Both Error - Unknown Notes: - OK means nothing of both CRC error and frame missing. - Update Counter is placed at byte0 bit5, 6 in command data block. 2012/2/15 Rev. 2 Page 40