Micrel KSZ8852HL Step-by-Step Programmer s Guide

Transcription

1 Micrel KSZ8852HL Step-by-Step Version 1.1 October 31, Page 1 -

2 Revision History Revision Date Summary of Changes /14/2013 First release /31/2013 Correct section 2, step 9; section 4.1, step 9; section 4.2, step 10 and 17 to address when device is in big-endian mode. Add section to describe register and QMU access when the device is in big-endian mode. - Page 2 -

3 Table of Contents 1 Overview KSZ8852HL Initialization Steps KSZ8852HL Additional Receive Initialization Steps KSZ8852HL Transmit Steps KSZ8852HL Receive Steps Receive Single Frame per DMA Receive Multiple Frames per DMA KSZ8852HL Host Bus Interface (BIU) Bit Data Bus Little-Endian Mode Register Access QMU Access Big-Endian Mode Register Access QMU Access Special Notices for Big-Endian Mode Bit Data Bus Register Access Read From Registers Write To Registers QMU Access Read From RXQ Write To TXQ Special Notices for 8-Bit Data Bus Page 3 -

4 1 Overview This document covers KSZ8852HL-16Bit, and KSZ8852HL-8Bit. Throughout this document, KSZ8852 refers to either KSZ8852HL-16Bit or KSZ8852HL- 8Bit. This document only provides step-by-step procedures detailing the registers and values need to be initialized, steps to transmit frame data to the device, to receive frame data from the device for the KSZ8852 series Two-port Ethernet Switch. Please refer to KSZ8852HL datasheet for detail register information. In order to set a bit in a register, such as step 1 in Initialization, read the register first and modify the target bit only and write it back. - Page 4 -

5 2 KSZ8852HL Initialization Steps Steps Read\write Register Name[bit] Value Description 1 Write GRR [0] 0ffset 0x126 bit 0 1 wait 10ms 0 2 Read CIDER [15-0] 0x8431 0ffset 0x0 Global Soft Reset by write 1 to reset, wait 100ms, write 0 to normal mode. Read the device chip ID, make sure it is correct ID (0x843x for KSZ8852HL); otherwise there are some errors on the host bus interface. 3 Write SGCR1 [8] 0ffset 0x002 bit 8 4 Write SGCR2 [3] 0ffset 0x004 bit 3 5 Write P1CR2 [12] 0ffset 0x6E bit 12 6 Write P1CR4 [5] 0ffset 0x07E bit 5 7 Write P1CR4 [13] 0ffset 0x07E bit 13 8 Write P2CR2 [12] 0ffset 0x86 bit 12 9 Write P2CR4 [5] 0ffset 0x096 bit 5 10 Write P2CR4 [13] 0ffset 0x096 bit Write MARL[15-0] 0ffset 0x110 1 Enable more aggressive back off algorithm in half-duplex mode to enhance performance. 1 Enable Switch don t drop packets when 16 or more collisions occur in half-duplex mode. 0 Disable Force Flow Control. The flow control is enabled based on auto-negotiation result. 1 Force Port 1 in half duplex if auto-nego fails when link partner doesn t support auto-nego (like HUB device). 1 Restart Port 1 auto-negotiation. 0 Disable Force Flow Control. The flow control is enabled base on auto-nego result. 1 Force Port 2 in half duplex if auto-nego is fail when link partner doesn t support auto-nego (like HUB device). 1 Restart Port 2 auto-negotiation. 0x89AB Write QMU MAC address (low). MAC address is generally expressed in the form of 01:23:45:67:89:AB. (we use this MAC as an example). 12 Write MARM[15-0] 0ffset 0x Write MARH[15-0] 0ffset 0x Write MARL[15-0] 0ffset 0x10 15 Write MARM[15-0] 0ffset 0x12 0x4567 0x0123 0x89AB 0x4567 Write QMU MAC address (Medium). MAC address is generally expressed in the form of 01:23:45:67:89:AB. (we use this MAC as an example). Write QMU MAC address (High). MAC address is generally expressed in the form of 01:23:45:67:89:AB. (we use this MAC as an example). Write Switch MAC address (low) for sending PAUSE frame. MAC address is generally expressed in the form of 01:23:45:67:89:AB. (we use this MAC as an example). Write Switch MAC address (Medium) for sending PAUSE frame. MAC address is generally expressed in the form of 01:23:45:67:89:AB. (we use this MAC as an example). - Page 5 -

6 16 Write MARH[15-0] 0ffset 0x14 0x0123 Write Switch MAC address (High) for sending PAUSE frame. MAC address is generally expressed in the form of 01:23:45:67:89:AB. (we use this MAC as an example). 17 Write TXFDPR [14] 0ffset 0x Write TXCR [15-0] 0ffset 0x Write RXFDPR[14] 0ffset 0x186 1 Enable QMU Transmit Frame Data Pointer Auto Increment. 0x00EE Enable QMU Transmit flow control / Transmit padding / Transmit CRC, and IP/TCP/UDP checksum generation. 1 Enable QMU Receive Frame Data Pointer Auto Increment. 20 Write RXFCTR[15-0] 0ffset 0x19C 21 Write RXCR1 [15-0] 0ffset 0x Write RXCR2 [15-0] 0ffset 0x Write RXQCR[15-0] 0ffset 0x Write ISR [15-0] 0ffset 0x192, 0x0001 0x7CE0 0x0115 0x0230 0xFFFF Configure Receive Frame Threshold for one frame. Enable QMU Receive flow control / Receive all broadcast frames /Receive unicast frames, and IP/TCP/UDP checksum verification etc. Enable QMU Receive UDP Lite frame checksum verification/generation, IPv4/IPv6 UDP fragment frame pass, drop the received frame if SA is same as device MAC address, and QMU Flow Control Pause Timer. Enable QMU Receive IP Header Two-Byte Offset /Receive Frame Count Threshold/RXQ Auto-Dequeue frame. Clear the interrupts status. 25 Write IER [15-0] 0ffset 0x190, 26 Write TXCR [0] 0ffset 0x170, bit 0 27 Write RXCR1 [0] 0ffset 0x174, bit 0 0xE000 Enable Link Change\Transmit\Receive interrupt if your host processor can handle the interrupt, otherwise do not need to do this step. 1 Enable QMU Transmit. 1 Enable QMU Receive. - Page 6 -

7 2.1 KSZ8852HL Additional Receive Initialization Steps To minimize host CPU interrupt overhead, the KSZ8852 also supports generate only one receive interrupt after device RXQ received multiple frames. In order to configure this interrupt scheme, the following addition receives initialization steps need to be set. Steps Read\write Register Name[bit] Value Description 20 Write RXFCTR[15-0] 0ffset 0x19C 0x0004 Configure Receive Frame Threshold for multiplex frames, e.g. four frames Write RXDTTR[15-0] 0ffset 0x18C 23 Write RXQCR[15-0] 0ffset 0x182 0x03E8 0x02B0 Configure Receive Duration Threshold, e.g. 1ms. Device will still generate receive interrupt if RXQ only received one frame, but device timer already exceeds the threshold set in this register. Enable QMU Receive IP Header Two-Byte Offset /Receive Frame Count Threshold/ Receive Duration Timer Threshold /RXQ Auto-Dequeue frame. - Page 7 -

8 3 KSZ8852HL Transmit Steps The host transmit driver must write each frame data to align with double word boundary at end. For example, the driver has to write up to 68 bytes if transmit frame size is 65 bytes. Steps Read\write Register Name[bit] Value Description 0 Transmit data frame from the upper layer to KSZ8852 device by a complete packet frame data. For every complete packet frame data transmit to KSZ8852 device, process the following the steps. There are two variables are needed from the upper layer to transmit a data packet frame. (1). Packet data pointer (ptxdata). It points to the host CPU system memory space contains the complete Ethernet packet data. (2). Packet length (txpacketlength). The Ethernet packet data length not includes CRC. 1 Read TXMIR [12-0] 0ffset 0x178 >= (txpacketlength+4) Read value from TXMIR to check if QMU TXQ has enough amount of memory for the Ethernet packet data plus 4-byte frame header. Compare the read value with (txpacketlength+4), if less than (txpacketlength+4), Exit 1. 2 Write IER [15-0] 0ffset 0x190, 3 Write RXQCR[3] 0ffset 0x182 bit Disable all the device interrupts generation. 1 Start 2 QMU DMA transfer operation to write frame data from host CPU to the TxQ. 4 Write REG_QDR_DUMMY 3 0x8000 Write TXIC to the control word of the frame header through REG_QDR_DUMMY dummy address. 5 Write REG_QDR_DUMMY txpacketlength Write txpacketlength to the byte count of the frame header through REG_QDR_DUMMY dummy address. 1 Or ask upper layer to stop sending frames to the device since the device is not ready, and then exit. When the ISR driver gets the Transmit interrupt (TXIE bit SET from ISR), tell upper layer that the device is ready to resume sending frames. 2 Once QMU DMA transfer operation is started, the host must not access any other device registers. 3 REG_QDR_DUMMY is the dummy address to be accessed to QMU TxQ or RxQ when we start QMU transfer operation which regardless QMU address and byte enable signals with AEN, RDN, or WRN signals. - Page 8 -

9 6 UINT16 *ptxdata; int lengthinword=((txpacketlength+3)>>2) * 2; Write frame data pointer by ptxdata to the QMU TXQ through REG_QDR_DUMMY dummy address in 16-bit until finished the full packet length (lengthinword) in DWORD alignment. 7 Write REG_QDR_DUMMY *ptxdata++ Write 2-byte 4 of frame data pointer by ptxdata to the QMU TXQ through REG_QDR_DUMMY dummy address. Increase ptxdata pointer by 2. 8 lengthinword --; if (lengthinword > 0 ) goto Step 7; else goto Step 9; 9 Write RXQCR[3] 0ffset 0x182 bit 3 10 Write TXQCR[0] 0ffset 0x180 bit 0 11 Write IER [15-0] 0ffset 0x190, Subtract lengthinword by 1. 0 Stop QMU DMA transfer operation. 1 TxQ Manual-Enqueue. 0xE000 Enable the device interrupts again. Exit. 4 If it is 8-Bit bus interface, you should write 1-byte of frame date pointer by ptxdata to the QMU TXQ through REG_QDR_DUMMY dummy address. Increase ptxdata pointer by 1 and Subtract lengthinword by 1. Modify Step 6 for lengthinword as: lengthinword=((txpacketlength+3)>>2) * 4; - Page 9 -

10 4 KSZ8852HL Receive Steps There are two methods of receiving frames from QMU RXQ. First one just reads single frame from RXQ per DMA transfer operation. Second one will read multiplex frames per DMA transfer operation. If host processor can provide DMA channel moving the data, the second method will have better performance. The following sections describe receiving steps on these two different methods. The host receive driver must read each frame data to align with double word boundary at end. For example, the driver has to read up to 68 bytes if received frame size is 65 bytes. 4.1 Receive Single Frame per DMA Host driver reads single frame from RXQ per DMA transfer operation. Steps Read\write Register Name[bit] Value Description 0 There are two methods to receive a complete Ethernet packet from KSZ8851 device to upper layer either as a result of polling or servicing an interrupt. (1). By polling, set a timer routine to periodically execute step 1. (2). By servicing an interrupt, when interrupt occurs, execute step 1 from the ISR routine. Allocate a system memory space (address by prxdata) which is big enough to hold an Ethernet packet frame for each received frame from QMU RXQ. 1 Read ISR [13] 0ffset 0x192, bit 13 2 Write IER [15-0] 0ffset 0x190, 3 Write ISR [13] 0ffset 0x192, bit 13 4 Read RXFC[7-0] 0ffset 0x1B8 1 Read value from ISR to check if RXIS Receive Interrupt is set. If not set, Exit Disable all the device interrupts generation. 1 Acknowledge (clear) RXIS Receive Interrupt bit. rxframecount Read current total amount of received frame count from RXFC, and save in rxframecount. 5 if (rxframecount > 0 ) goto Step 6; else goto step 20; 6 Read RXFHSR [15-0] 0ffset 0x17C rxstatus Loop reading all frames from RXQ. If rxframecount <= 0, goto step 20 Read received frame status from RXFHSR to check if this is a good frame. 7 Read RXFHBCR [10-0] 0ffset 0x17E rxpacketlength Read received frame byte size from RXFHBCR to get this received frame - Page 10 -

11 length (4 byte CRC is included, and ), And store into rxpacketlength variable. if rxstatus s bit_15 is 0, or if rxstatus s bit_0, bit_1, bit_10, bit_11, bit_12, bit_13 are 1, and rxpacketlength = 0, received a error frame, goto step 8, Else received a good frame, goto step 9. 8 Write RXQCR [0] 0ffset 0x182 bit 0 9 Write RXFDPR[10-0] 0ffset 0x Write RXQCR[3] 0ffset 0x182 bit 3 1 Issue the RELEASE error frame command for the QMU to release the current error frame from RXQ. goto step 19; 0 Reset QMU RXQ frame pointer to zero, other bits remain unchanged. 1 Start 5 QMU DMA transfer operation to read frame data from the RXQ to host CPU. 11 Read REG_QDR_DUMMY pdummy Dummy read 2-byte if it is 16-bit data bus interface, or read 1-byte if it is 8-bit data bus interface from the QMU RXQ through REG_QDR_DUMMY dummy address. 12 Read REG_QDR_DUMMY pdummy Read out 2-byte Status Word of frame header from the QMU RXQ through REG_QDR_DUMMY dummy address. 13 Read REG_QDR_DUMMY pdummy Read out 2-byte Byte Count of frame header from the QMU RXQ through REG_QDR_DUMMY dummy address. 14 UINT16 *prxdata; int lengthinword=((rxpacketlength +3) >> 2) * 2; Read frame data to system memory pointer by prxdata from the QMU RXQ through REG_QDR_DUMMY dummy address in DWORD alignment until finished the full packet length by lengthinword. 15 Read REG_QDR_DUMMY *prxdata ++ Read 2-byte 6 of frame data to system memory pointer by prxdata from the 5 Once QMU DMA transfer operation is started, host must not access any other device registers. 6 If it is 8-Bit bus interface, read 1-byte of frame data to system memory pointer by prxdata from the QMU RXQ through REG_QDR_DUMMY dummy address. Increase prxdata pointer by 1 and Subtract rxpacketlength by 1. Modify Step 14 for lengthinword as: lengthinword=((txpacketlength+3)>>2) * 4; - Page 11 -

12 QMU RXQ through REG_QDR_DUMMY dummy address. Increase prxdata pointer by lengthinword --; if (lengthinword > 0 ) goto Step 15; else goto Step 17; Subtract lengthinword by Write RXQCR[3] 0ffset 0x182 bit 3 0 Stop QMU DMA transfer operation. 18 Pass this received frame to the upper layer protocol stack. Because Receive IP Header Two-Byte Offset feature is enabled, there are two extra bytes before the valid frame data, and two extra bytes count additional to 4-byte CRC is included in the frame header Byte Count (RXFHBCR). In order to pass the correct received frame (not include CRC) pointer by prxdata and received frame length rxpacketlength to the upper layer protocol stack, the driver need to do: (1). Increase data pointer prxdata by 2-byte to the beginning of Ethernet packet data, prxdata += 2; (2). Minus 2 extra bytes from rxpacketlength to the upper layer. rxpacketlength -= 2; (3). Minus 4-byte CRC length from rxpacketlength to the upper layer. rxpacketlength -= 4; (4). Pass received frame to upper layer protocol stack. toupperlayer (prxdata, rxpacketlength ); 19 rxframecount = rxframecount 1; goto step Write IER [15-0] 0ffset 0x190 0xE000 Finished reading one frame, subtract rxframecount by 1. Loop again. Enable the device interrupts again. Exit. NOTE: Following are interaction between device and driver for device to update register RXFC (received frame count), RXFHSR (received frame status), and RXFHBCR (received frame length): If RXIS is set in register ISR: (1). When Software clears RXIS in register ISR, device updates frame count in register RXFC; (2). When Software reads frame count from register RXFC, device updates current frame header information in register RXFHSR/RXFHBCR; (3). When Software reads current frame header information from register RXFHSR/RXFHBCR, device updates next frame header information in register RXFHSR/RXFHBCR if frame count is more than 1. In sequence of software reading register RXFHSR/RXFHBCR, high byte of register RXFHBCR must in last. (4). Software reads current frame data from device RXQ. (5). If frame count is more than 1, go to step (3), loop again until finished all frames are read out with current frame count. - Page 12 -

13 4.2 Receive Multiple Frames per DMA Host driver reads multiple frames from RXQ per DMA transfer operation. Steps Read\write Register Name[bit] Value Description 0 There are two methods to receive a complete Ethernet packet from KSZ8851 device to upper layer either as a result of polling or servicing an interrupt. (1). By polling, set a timer routine to periodically execute step 1. (2). By servicing an interrupt, when interrupt occurs, execute step 1 from the ISR routine. Since we need to record received multiplex frames header information (status and frame length) before read the multiplex frames from QMU RXQ in one DMA transfer operation, we need a array or link list structure that has two variable to store each received frame status rxstatus, and frame length rxlength. Eg, the sample array structure to store received multiplex frame header information: typedef struct { USHORT rxstatus; USHORT rxlength; } FR_HEADER_INFO; FR_HEADER_INFO rxframeheader[ MAX_FRAMES_IN_RXQ ]; Allocate a system memory space (address by prxdata) which is big enough to hold an Ethernet packet frame for each received frame from QMU RXQ. 1 Read ISR [13] 0ffset 0x192, bit 13 2 Write IER [15-0] 0ffset 0x190, 3 Write ISR [13] 0ffset 0x192, bit 13 1 Read value from ISR to check if RXIS Receive Interrupt is set. If not set, Exit Disable all the device interrupts generation. 1 Acknowledge (clear) RXIS Receive Interrupt bit. 4 Read RXFC[7-0] 0ffset 0x1B8 5 int i = 0; if (rxframecount > 0 ) goto Step 6; else goto step 9; 6 Read RXFHSR [15-0] 0ffset 0x17C 7 Read RXFHBCR [10-0] 0ffset 0x17E rxframecount rxframeheader[i]. rxstatus rxframeheader[i]. rxlength Read current total amount of received frame count from RXFC, and save in rxframecount. Loop reading all frames header information from RXFHSR and RXFHBCR. If rxframecount <= 0, goto step 9. Read received frame status from RXFHSR to rxstatus array variable. Read received frame byte size from RXFHBCR to rxlength array variable. - Page 13 -

14 8 rxframecount = rxframecount 1; i +=1; goto step 5. 9 rxframecount = i; i=0; 10 Write RXFDPR[10-0] 0ffset 0x Write RXQCR[3] 0ffset 0x182 bit 3 Finished store one frame header information, subtract rxframecount by 1, Increase array index by 1. Loop again. Restore total amount of received frame count rxframecount again to start read frame data from RXQ. 0 Reset QMU RXQ frame pointer to zero, and other bits remain unchanged. 1 Start QMU DMA transfer operation to read frame data from the RXQ to host CPU. 12 Read REG_QDR_DUMMY pdummy Dummy read 2-byte if it is 16-bit data bus interface, read 1-byte if it is 8-bit data bus interface from the QMU RXQ through REG_QDR_DUMMY dummy address. 13 if (rxframecount > 0 ) goto Step 14; else goto step 28; 14 #define RX_ERRORS 0x3C03 if ( (rxframeheader[i]. rxstatus & RX_ERRORS ) (rxframeheader[i]. rxlength <= 0 )) error frame, goto step 15; else good frame, goto step 21; 15 Write RXQCR[3] 0ffset 0x182 bit 3 16 Write RXQCR[0] 0ffset 0x182 bit 0 Loop reading all frames from RXQ. If rxframecount <= 0, goto step 28. Check received frame status rxframeheader[i]. rxstatus to see if this is a good frame, and received frame length rxframeheader[i]. rxlength. 0 This is an error frame. Stop QMU DMA transfer operation. 1 Issue the RELEASE error frame command for the QMU to release the current error frame from RXQ. 17 Write RXFDPR[10-0] 0ffset 0x186 0 Reset QMU RXQ frame pointer to zero, and other bits remain unchanged. 18 Write RXQCR[3] 0ffset 0x182 bit 3 1 Then, Start the DMA transfer operation again for the next frame. 19 Read REG_QDR_DUMMY pdummy Dummy read 2-byte if it is 16-bit data bus interface, or read 1-byte if it is 8-bit data bus interface from the QMU RXQ through REG_QDR_DUMMY dummy address. 20 goto step 27; Go for processing the next frame. 21 Read REG_QDR_DUMMY pdummy Read out 2-byte Status Word of frame header from the QMU RXQ through REG_QDR_DUMMY dummy address. - Page 14 -

15 22 Read REG_QDR_DUMMY pdummy Read out 2-byte Byte Count of frame header from the QMU RXQ through REG_QDR_DUMMY dummy address. 23 UINT16 *prxdata; int lengthinword; lengthinword =(( rxframeheader[i]. rxlength +3) >> 2) * 2; Read frame data to system memory pointer by prxdata from the QMU RXQ through REG_QDR_DUMMY dummy address in DWORD alignment until finished the full packet length in lengthinword. 24 Read REG_QDR_DUMMY *prxdata ++ Read 2-byte 7 of frame data to system memory pointer by prxdata from the QMU RXQ through REG_QDR_DUMMY dummy address. Increase prxdata pointer by lengthinword --; if (lengthinword > 0 ) goto Step 24; else goto Step 26; 26 Pass this received frame to the upper layer protocol stack. Subtract lengthinword by 1. Because Receive IP Header Two-Byte Offset feature is enabled, there are two extra bytes before the valid frame data, and two extra bytes count additional to 4-byte CRC is included in the frame header Byte Count (RXFHBCR). In order to pass the correct received frame (not include CRC) pointer by prxdata and received frame length rxpacketlength to the upper layer protocol stack, the driver need to do: (1). Increase data pointer prxdata by 2-byte to the beginning of Ethernet packet data, prxdata += 2; (2). Minus 2 extra bytes from rxpacketlength to the upper layer. rxlength -= 2; (3). Minus 4-byte CRC length from rxpacketlength to the upper layer. rxlength -= 4; (4). Pass received frame to upper layer protocol stack. toupperlayer (prxdata, rxframeheader[i]. rxlength); 27 rxframecount = rxframecount 1; i +=1; goto step Write RXQCR[3] 0ffset 0x182 bit 3 29 Write IER [15-0] 0ffset 0x190 Finished reading one frame, subtract rxframecount by 1. Increase array index by 1. Loop again. 0 Stop QMU DMA transfer operation. 0xE000 Enable the device interrupts again. Exit. 7 If it is 8-Bit bus interface, read 1-byte of frame data to system memory pointer by prxdata from the QMU RXQ through REG_QDR_DUMMY dummy address. Increase prxdata pointer by 1 and Subtract rxpacketlength by 1. Modify Step 23 for lengthinword as: lengthinword=((txpacketlength+3)>>2) * 4; - Page 15 -

16 5 KSZ8852HL Host Bus Interface (BIU) The KSZ8852HL BIU for host interface is a generic shared data bus interface, designed to communicate with embedded processors. Shared Data bus SD[15:0] for Address, Data and Byte Enable, Command (CMD), Chip Select Enable (CSN), Read (RDN), Write (WRN) and Interrupt (INTRN). The BIU host interface is an indirect access data bus interface. The Data Bus SD[15:0] specifies the address or data depending on the CMD control signal. The BIU supports an 8-bit or 16-bit host standard data bus. Depending on the size of the physical data bus, the KSZ8852HL can support 8-bit or 16-bit data transfers Bit Data Bus For a 16-bit data bus mode, the KSZ8852 allows an 8-bit and 16-bit data transfer. The CMD determines whether SD[15:0] is the address or data bus by following table. Host CPU KSZ8852HL-16Bit HA2 HD[15:0] CMD SD[15:0] /CS /WR /RD IRQ CSN WRN RDN INTRN Figure 6.1. Host Data Bus Interface to the device 16-Bit bus HD: Host Data Bus. SD: KSZ8852HL-16Bit Shared Data Bus. X: don t care. CMD SD15 SD14 SD13 SD12 SD11 SD10 SD9 SD8 SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0 1 BE3 BE2 BE1 BE0 X A10 A9 A8 A7 A6 A5 A4 A3 A2 X X 0 D15 D13 D12 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Table 6.1. KSZ Bit Shared Data Bus Operation for Register Access - Page 16 -

17 The KSZ8852 supports either Little-Endian or Big-Endian processors. Device Endian mode can be configured by strapping option or by Bit[11] (Endian Mode Selection) in register 0x186 (RXFDPR). Please refer to the datasheet for endian mode configuration details. Bit[10] (Bus Endian mode) in register 0x108 (CCR) represent the current device endian mode status. The following sections descript how to access the device registers and QMU in different endian mode Little-Endian Mode The register address field when CMD= 1 consists of only A[10:2] to access register location in DWORD boundary, and the BE[3:0] - byte enable field specifies the byte to be accessed. The following table shows how BE[3:0] field are encoded to address A1, A0 (1) To read a BYTE at a time: A1 A0 BE3 BE2 BE1 BE (2) To read a WORD at a time: A1 A0 BE3 BE2 BE1 BE The following sections describe how to access KSZ8852 registers in 16-bit bus interface in Little-Endian mode. - Page 17 -

18 Register Access To access KSZ8852 device registers, two steps are always needed to set values to the SD bus; the first step is to write the address/be[3:0] (byte enable) data to SD bus with CMD high, and the second step is to read/write data from/to SD bus with CMD is low. If device is configured as little-endian mode, the second step s data format is in which the least signification byte (LSB) is at the 0 address end as following: MSB LSB Word Data 15-8 Data 7 0 And the first step s BE[3:0] to access internal 32-bit alignment registers as following: Operation Data Bus BEn Access Address No. D31-D24 D23-D16 D15-D8 D7-D0 BE3 BE2 BE1 BE0 Size Byte 4n Data 7-0 Asserted 4n+1 Data 7-0 Asserted 4n+2 Data 7-0 Asserted 4n+3 Data 7-0 Asserted Word 4n Data 15-8 Data 7-0 Asserted Asserted 4n+2 Data 15-8 Data 7-0 Asserted Asserted Read From Registers While CMD pin is connected to host address line A2, along with Chip Select Enable (CS) and Read (RDN) signals, the driver reads data from registers in following steps: 1. CMD=1: Write address command - register offset value along with BE[3:0] to SD[15:0] 2. CMD=0: Read register value from SD[15:0]. Example 1: read 2-byte from register 0x0 at external IO base address 0x1F Write 0x3000 Write value 0x3000 (register offset 0x0 with BE1/BE0), 2 Read 0x8431 Read value (will be chip ID 0x8431), From 0x1F From address 0x1F (the address line A2 is low CMD is low). - Page 18 -

19 W x3000 R x8431 Example 2: read 2-byte from register 0x12 at external IO base address 0x1F Write 0xC012 Write value 0xC012 (register offset 0x12 with BE3/BE2), 2 Read value Read value, From 0x1F From address 0x1F (the address line A2 is low CMD is low). W xC012 R x1234 Example 3: read 1-byte from register 0x10 at external IO base address 0x1F Assume register 0x10 to register 13 contains value 0x Write 0x1010 Write value 0x1010 (register offset 0x10 with BE0), 2 Read 0xXX78 Read 2-byte value 0xXX78, D15-8 is invalid, only D7-0 is valid. From 0x1F From address 0x1F (the address line A2 is low CMD is low). W x1010 R 0 X X X X X X X X xXX78 Example 4: read 1-byte from register 0x11 at external IO base address 0x1F Assume register 0x10 to register 13 contains value 0x Write 0x2011 Write value 0x2011 (register offset 0x11 with BE1), 2 Read 0x56XX Read 2-byte value 0x56XX, only D15-8 is valid, D7-0 is invalid, From 0x1F From address 0x1F (the address line A2 is low CMD is low). W x2011 R X X X X X X X X 0x56XX - Page 19 -

20 Example 5: read 1-byte from register 0x12 at external IO base address 0x1F Assume register 0x10 to register 13 contains value 0x Write 0x4012 Write value 0x4012 (register offset 0x12 with BE2), 2 Read 0xXX34 Read 2-byte value 0xXX34, D15-8 is invalid, only D7-0 is valid, From 0x1F From address 0x1F (the address line A2 is low CMD is low). W x4012 R 0 X X X X X X X xXX34 Example 6: read 1-byte from register 0x13 at external IO base address 0x1F Assume register 0x10 to register 13 contains value 0x Write 0x8013 Write value 0x8013 (register offset 0x13 with BE3), 2 Read 0x12XX Read 2-byte value 0x12XX, only D15-8 is valid, D7-0 is invalid, From 0x1F From address 0x1F (the address line A2 is low CMD is low). W x8013 R X X X X X X X X 0x12XX Write To Registers Assuming CMD pin is connected to host address line A2, along with Chip Select Enable (CS) and Write (WRN) signals, the driver writes data to registers in following steps: 1. CMD=1: Write address command - register offset value along with BE[3:0] to SD[15:0]. 2. CMD=0: Write value to SD[15:0]. Example 1: write 2-byte value (0x1234) to register 0x220 at external IO base address 0x1F Write 0x3220 Write value 0x3220 (register offset 0x220 with BE1/BE0), - Page 20 -

21 2 Write 0x1234 Write 2-byte value 0x1234, To 0x1F To address 0x1F (the address line A2 is low CMD is low). W x3220 W x1234 Example 2: write 2-byte value (0x5678) to register 0x222 at external IO base address 0x1F Write 0xC222 Write value 0xC222 (register offset 0x222 with BE3/BE2), 2 Write 0x5678 Write 2-byte value 0x5678, To 0x1F To address 0x1F (the address line A2 is low CMD is low). W xC222 W x5678 Example 3: write 1-byte value (0xAB) to register 0x220 at external IO base address 0x1F Write 0x1220 Write value 0x1220 (register offset 0x220 with BE0), 2 Write 0x00AB Write 2-byte value 0x00AB, D15-8 don t care, only D7-0 is valid, To 0x1F To address 0x1F (the address line A2 is low CMD is low). W x1220 W x00AB Example 4: write 1-byte value (0xCD) to register 0x221 at external IO base address 0x1F Write 0x2221 Write value 0x2221 (register offset 0x221 with BE1), 2 Write 0xCD00 Write 2-byte value 0xCD00, only D15-8 is valid, D7-0 don t care, To 0x1F To address 0x1F (the address line A2 is low CMD is low). - Page 21 -

22 W x2221 W xCD00 Example 5: write 1-byte value (0xEF) to register 0x222 at external IO base address 0x1F Write 0x4222 Write value 0x4222 (register offset 0x222 with BE2), 2 Write 0x00EF Write 2-byte value 0x00EF, D15-8 don t care, only D7-0 is valid, To 0x1F To address 0x1F (the address line A2 is low CMD is low). W x4222 W x00EF Example 6: write 1-byte value (0x56) to register 0x223 at external IO base address 0x1F Write 0x8223 Write value 0x8223 (register offset 0x223 with BE3), 2 Write 0x5600 Write 2-byte value 0x5600, only D15-8 is valid, D7-0 don t care, To 0x1F To address 0x1F (the address line A2 is low CMD is low). W x8223 W x Page 22 -

23 QMU Access To access KSZ8852HL 16-Bit mode device s QMU RXQ/TXQ in little-endian mode, it only needs one step to read/write data from/to SD bus with CMD low Read From RXQ The device allows a transfer operation from the host CPU to read frame data from QMU RXQ frame buffer with Chip Select Enable (CS), Read (RDN) while CMD pin (A2) is always low after RXQCR bit 3 ( Start DMA Access ) is set, which starts the QMU transfer operation. Like section 4.1 steps 15 (external IO base address 0x1F000000), 15 Read 0x1F *prxdata ++ Read 2-byte of frame data to system memory pointer by prxdata from the QMU RXQ through 0x1F address (the address line A2 is low CMD is low). Increase prxdata pointer by Write To TXQ The device allows a transfer operation from the host CPU to write frame data to QMU TXQ frame buffer with Chip Select Enable (CS), Write (WRN) signals while CMD pin (A2) is always low after RXQCR bit 3 ( Start DMA Access ) is set, which starts the QMU transfer operation. Like section 3, steps 7 (external IO base address 0x1F000000), 7 Write 0x1F *ptxdata++ Write 2-byte of frame data pointer by ptxdata to the QMU TXQ through 0x1F address (the address line A2 is low CMD is low). Increase ptxdata pointer by 2. - Page 23 -

24 5.1.2 Big-Endian Mode The register address field when CMD= 1 consists of only A[10:2] to access register location in DWORD boundary, and the BE[3:0] - byte enable field specifies the byte to be accessed. The following table show how BE[3:0] field are encoded to address A1, A0 (1) To read a BYTE at a time: A1 A0 BE3 BE2 BE1 BE (2) To read a WORD at a time: A1 A0 BE3 BE2 BE1 BE The following sections describe how to access KSZ8852 registers in 16-bit bus interface in Big- Endian mode. - Page 24 -

25 Register Access To access KSZ8852 device registers, it always needs two steps to set value to SD bus; the first step is to write the address/be[3:0] (byte enable) data to SD bus with CMD high, and the second step is to read/write data from/to SD bus with CMD low. If device is configured as big-endian mode, the second step s data format is in which the most signification byte (MSB) is at the 0 address end as following: LSB MSB Word Data 7-0 Data 15 8 And the first step s BE[3:0] to access internal 32-bit alignment registers as following: Operation Data Bus BEn Access Address No. D7-D0 D15-D8 D23-D16 D31-D24 BE3 BE2 BE1 BE0 Size Byte 4n Data 7-0 Asserted 4n+1 Data 7-0 Asserted 4n+2 Data 7-0 Asserted 4n+3 Data 7-0 Asserted Word 4n Data 15-8 Data 7-0 Asserted Asserted 4n+2 Data 15-8 Data 7-0 Asserted Asserted Read From Registers While CMD pin is connected to host address line A2, along with Chip Select Enable (CS) and Read (RDN) signals, the driver reads data from registers in the following steps: 3. CMD=1: Write address command - register offset value along with BE[3:0] to SD[15:0] 4. CMD=0: Read register value from SD[15:0]. Example 1: read 2-byte from register 0x0 at external IO base address 0x1F Write 0xC000 Write value 0xC000 (register offset 0x0 with BE3/BE2), 2 Read 0x8431 Read value (will be chip ID 0x8431), From 0x1F From address 0x1F (the address line A2 is low CMD is low). - Page 25 -

26 W xC000 R x8431 Example 2: read 2-byte from register 0x12 at external IO base address 0x1F Write 0x3012 Write value 0x3012 (register offset 0x12 with BE1/BE0), 2 Read value Read value, From 0x1F From address 0x1F (the address line A2 is low CMD is low). W x3012 R x1234 Example 3: read 1-byte from register 0x10 at external IO base address 0x1F Assume register 0x10 to register 13 contains value 0x Write 0x8010 Write value 0x8010 (register offset 0x10 with BE3), 2 Read 0xXX78 Read 2-byte value 0xXX78, D15-8 is invalid, only D7-0 is valid. From 0x1F From address 0x1F (the address line A2 is low CMD is low). W x8010 R 0 X X X X X X X X xXX78 Example 4: read 1-byte from register 0x11 at external IO base address 0x1F Assume register 0x10 to register 13 contains value 0x Write 0x4011 Write value 0x4011 (register offset 0x11 with BE2), 2 Read 0x56XX Read 2-byte value 0x56XX, only D15-8 is valid, D7-0 is invalid, From 0x1F From address 0x1F (the address line A2 is low CMD is low). W x4011 R X X X X X X X X 0x56XX - Page 26 -

27 Example 5: read 1-byte from register 0x12 at external IO base address 0x1F Assume register 0x10 to register 13 contains value 0x Write 0x2012 Write value 0x2012 (register offset 0x12 with BE1), 2 Read 0xXX34 Read 2-byte value 0xXX34, D15-8 is invalid, only D7-0 is valid, From 0x1F From address 0x1F (the address line A2 is low CMD is low). W x2012 R 0 X X X X X X X xXX34 Example 6: read 1-byte from register 0x13 at external IO base address 0x1F Assume register 0x10 to register 13 contains value 0x Write 0x1013 Write value 0x1013 (register offset 0x13 with BE0), 2 Read 0x12XX Read 2-byte value 0x12XX, only D15-8 is valid, D7-0 is invalid, From 0x1F From address 0x1F (the address line A2 is low CMD is low). W x1013 R X X X X X X X X 0x12XX Write To Registers Assuming CMD pin is connected to host address line A2, along with Chip Select Enable (CS) and Write (WRN) signals, the driver writes data to registers in the following steps: 3. CMD=1: Write address command - register offset value along with BE[3:0] to SD[15:0]. 4. CMD=0: Write value to SD[15:0]. Example 1: write 2-byte value (0x1234) to register 0x220 at external IO base address 0x1F Write 0xC220 Write value 0xC220 (register offset 0x220 with BE3/BE2), - Page 27 -

28 2 Write 0x1234 Write 2-byte value 0x1234, To 0x1F To address 0x1F (the address line A2 is low CMD is low). W xC220 W x1234 Example 2: write 2-byte value (0x5678) to register 0x222 at external IO base address 0x1F Write 0x3222 Write value 0x3222 (register offset 0x222 with BE1/BE0), 2 Write 0x5678 Write 2-byte value 0x5678, To 0x1F To address 0x1F (the address line A2 is low CMD is low). W x3222 W x5678 Example 3: write 1-byte value (0xAB) to register 0x220 at external IO base address 0x1F Write 0x8220 Write value 0x8220 (register offset 0x220 with BE3), 2 Write 0x00AB Write 2-byte value 0x00AB, D15-8 don t care, only D7-0 is valid, To 0x1F To address 0x1F (the address line A2 is low CMD is low). W x8220 W x00AB Example 4: write 1-byte value (0xCD) to register 0x221 at external IO base address 0x1F Write 0x4221 Write value 0x4221 (register offset 0x221 with BE2), 2 Write 0xCD00 Write 2-byte value 0xCD00, only D15-8 is valid, D7-0 don t care, To 0x1F To address 0x1F (the address line A2 is low CMD is low). - Page 28 -

29 W x4221 W xCD00 Example 5: write 1-byte value (0xEF) to register 0x222 at external IO base address 0x1F Write 0x2222 Write value 0x2222 (register offset 0x222 with BE1), 2 Write 0x00EF Write 2-byte value 0x00EF, D15-8 don t care, only D7-0 is valid, To 0x1F To address 0x1F (the address line A2 is low CMD is low). W x2222 W x00EF Example 6: write 1-byte value (0x56) to register 0x223 at external IO base address 0x1F Write 0x1223 Write value 0x1223 (register offset 0x223 with BE0), 2 Write 0x5600 Write 2-byte value 0x5600, only D15-8 is valid, D7-0 don t care, To 0x1F To address 0x1F (the address line A2 is low CMD is low). W x1223 W x Page 29 -

30 QMU Access To access KSZ8852HL 16-Bit mode device s QMU RXQ/TXQ in big-endian mode, it only needs one step to read/write data from/to SD bus with CMD low Read From RXQ The device allows a transfer operation from the host CPU to read frame data from QMU RXQ frame buffer with Chip Select Enable (CS), Read (RDN) while CMD pin (A2) is always low after RXQCR bit 3 ( Start DMA Access ) is set, which starts the QMU transfer operation. Like section 4.1 steps 15 (external IO base address 0x1F000000), 15 Read 0x1F *prxdata ++ Read 2-byte of frame data to system memory pointer by prxdata from the QMU RXQ through 0x1F address (the address line A2 is low CMD is low). Increase prxdata pointer by Write To TXQ The device allows a transfer operation from the host CPU to write frame data to QMU TXQ frame buffer with Chip Select Enable (CS), Write (WRN) signals while CMD pin (A2) is always low after RXQCR bit 3 ( Start DMA Access ) is set, which starts the QMU transfer operation. Like section 3, steps 7 (external IO base address 0x1F000000), 7 Write 0x1F *ptxdata++ Write 2-byte of frame data pointer by ptxdata to the QMU TXQ through 0x1F address (the address line A2 is low CMD is low). Increase ptxdata pointer by 2. - Page 30 -

31 Special Notices for Big-Endian Mode Even when the KSZ8852HL is strapped at big-endian mode, the device still can be changed to little-endian mode at run time through the Bit[11] (Endian Mode Selection) in register 0x186 (RXFDPR). You need to be careful when programming register 0x186 in the following steps not to change device to little-endian mode: Section 4.1 Receive Single Frame step 9. Section 4.2 Receive Multiple Frames step 10 and step 17. When writing the packet frame to the device TxQ, the 2-byte control word and 2-byte byte count in the frame header need to have their high and low bytes swapped by the processor driver before being written to the device TxQ. You need to modify Section 3 Transmit step 4, and 5. Like this: 4 Write REG_QDR_DUMMY 0x0080 Write TXIC to the control word of the frame header through REG_QDR_DUMMY dummy address. 5 Write REG_QDR_DUMMY swap_len= (txpacketlength<<8) & 0xff00) (txpacketlength>>8) & 0x00ff) Write swap_len to the byte count of the frame header through REG_QDR_DUMMY dummy address. - Page 31 -

32 5.2 8-Bit Data Bus For an 8-bit data bus mode, the KSZ882HL only allows an 8-bit data transfer. The CMD determines whether SD[7:0] is the address or data bus by following table. Host CPU KSZ88522HL-8Bit HA0 HD[7:0] /CS CMD SD[7:0] SD[15:8] CSN /WR /RD IRQ WRN RDN INTRN GND Figure 6.2 Host Data Bus Interface to the device 8-Bit bus HD: Host Data Bus. SD: KSZ8852HL - 8Bit Shared Data Bus. X: don t care. Step CMD SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0 1 1 A7 A6 A5 A4 A3 A2 A1 A0 2 1 X X X X X A10 A9 A8 3 0 D7 D6 D5 D4 D3 D2 D1 D0 Table 6.2 KSZ Bit Shared Data Bus Operation for Register Access Since it needs 11-bit address to access entire KSZ Bit mode registers, the device is designed when CMD= 1, first data write to SD bus is lower register address A[7:0], the second data write to SD bus is higher register address A[10:A8]. NOTE: The host accesses to device register must follow Step 1~3 from Table 6.2 in continual sequence. The following sections describe how to access KSZ8852HL registers in 8-bit bus interface. - Page 32 -

33 5.2.1 Register Access To access KSZ8852HL registers, it always needs three steps to set value to SD bus; the first step is writing the address A[7:0] data to SD bus with CMD high, the second step is writing the address A[10:8] data to SD bus with CMD high, and the third step is reading/writing data from/to SD bus with CMD is low Read From Registers While CMD pin is connected to host address line A2, along with Chip Select Enable (CS) and Read (RDN) signals, the driver read data from registers in following steps: 1. CMD=1: Write address command - register offset value A[7:0] to SD[7:0]. 2. CMD=1: Write address command - register offset value A[10:8] to SD[2:0]. 3. CMD=0: Read register value from SD[7:0]. Example 1: read 2-byte from register 0x0 at external IO base address 0x1F Write 0x00 Write value 0x00 (register offset A[7:0]), 2 Write 0x00 Write value 0x00 (register offset A[10:8]), 3 Read 0x31 Read value (will be low byte of chip ID 0x31), From 0x1F From address 0x1F (the address line A2 is low CMD is low). 4 Write 0x01 Write value 0x01 (register offset A[7:0]), 5 Write 0x00 Write value 0x00 (register offset A[10:8]), 6 Read 0x84 Read value (will be high byte of chip ID 0x84), From 0x1F From address 0x1F (the address line A2 is low CMD is low). - Page 33 -

34 Op CMD SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0 Hex W x00 W x00 R x31 W x01 W x00 R x84 Example 2: read 1-byte from register 0x10 at external IO base address 0x1F Assume register 0x10 to register 13 contains value 0x Write 0x10 Write value 0x10 (register offset A[7:0]), 2 Write 0x00 Write value 0x00 (register offset A[10:8]), 3 Read 0x78 Read 1-byte value 0x78. From 0x1F From address 0x1F (the address line A2 is low CMD is low). Op CMD SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0 Hex W x10 W x00 R x78 Example 3: read 1-byte from register 0x11 at external IO base address 0x1F Assume register 0x10 to register 13 contains value 0x Write 0x11 Write value 0x11 (register offset A[7:0]), 2 Write 0x00 Write value 0x00 (register offset A[10:8]), 3 Read 0x56 Read 1-byte value 0x56. From 0x1F From address 0x1F (the address line A2 is low CMD is low). Op CMD SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0 Hex W x11 W x00 R x56 - Page 34 -

35 Example 4: read 1-byte from register 0x12 at external IO base address 0x1F Assume register 0x10 to register 13 contains value 0x Write 0x12 Write value 0x12 (register offset A[7:0]), 2 Write 0x00 Write value 0x00 (register offset A[10:8]), 3 Read 0x34 Read 1-byte value 0x34. From 0x1F From address 0x1F (the address line A2 is low CMD is low). Op CMD SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0 Hex W x12 W x00 R x34 Example 5: read 1-byte from register 0x13 at external IO base address 0x1F Assume register 0x10 to register 13 contains value 0x Write 0x13 Write value 0x13 (register offset A[7:0]), 2 Write 0x00 Write value 0x00 (register offset A[10:8]), 3 Read 0x12 Read 1-byte value 0x12. From 0x1F From address 0x1F (the address line A2 is low CMD is low). Op CMD SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0 Hex W x13 W x00 R x12 - Page 35 -

36 Write To Registers Assuming CMD pin is connected to host address line A2, along with Chip Select Enable (CS) and Write (WRN) signals, the driver write data to registers in following steps: 1. CMD=1: Write address command - register offset value A[7:0] to SD[7:0]. 2. CMD=1: Write address command - register offset value A[10:8] to SD[2:0]. 3. CMD=0: Write value to SD[7:0]. Example 1: write 2-byte value (0x1234) to register 0x220 at external IO base address 0x1F Write 0x20 Write value 0x20 (register offset A[7:0]), 2 Write 0x02 Write value 0x02 (register offset A[10:8]), 3 Write 0x34 Write lower 1-byte value 0x34, To 0x1F To address 0x1F (the address line A2 is low CMD is low). 4 Write 0x21 Write value 0x21 (register offset A[7:0]), 5 Write 0x02 Write value 0x02 (register offset A[10:8]), 6 Write 0x12 Write higher 1-byte value 0x12, To 0x1F To address 0x1F (the address line A2 is low CMD is low). Op CMD SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0 Hex W x20 W x02 W x34 W x21 W x02 W x12 Example 2: write 1-byte value (0xAB) to register 0x220 at external IO base address 0x1F Write 0x20 Write value 0x20 (register offset A[7:0]), - Page 36 -

37 2 Write 0x02 Write value 0x02 (register offset A[10:8]), 3 Write 0xAB Write 1-byte value 0xAB, To 0x1F To address 0x1F (the address line A2 is low CMD is low). Op CMD SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0 Hex W x20 W x02 W xAB Example 3: write 1-byte value (0xCD) to register 0x221 at external IO base address 0x1F Write 0x21 Write value 0x21 (register offset A[7:0]), 2 Write 0x02 Write value 0x02 (register offset A[10:8]), 3 Write 0xCD Write 1-byte value 0xCD, To 0x1F To address 0x1F (the address line A2 is low CMD is low). Op CMD SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0 Hex W x21 W x02 W xCD Example 4: write 1-byte value (0xEF) to register 0x222 at external IO base address 0x1F Write 0x22 Write value 0x22 (register offset A[7:0]), 2 Write 0x02 Write value 0x02 (register offset A[10:8]), 3 Write 0xEF Write 1-byte value 0xEF, To 0x1F To address 0x1F (the address line A2 is low CMD is low). - Page 37 -

38 Op CMD SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0 Hex W x22 W x02 W xEF Example 5: write 1-byte value (0x56) to register 0x223 at external IO base address 0x1F Write 0x23 Write value 0x23 (register offset A[7:0]), 2 Write 0x02 Write value 0x02 (register offset A[10:8]), 3 Write 0x56 Write 1-byte value 0x56, To 0x1F To address 0x1F (the address line A2 is low CMD is low). Op CMD SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0 Hex W x23 W x02 W x QMU Access To access KSZ8852HL 8-Bit mode QMU RXQ/TXQ, it only needs one step to read/write data from/to SD bus with CMD is low Read From RXQ The device allows a transfer operation from the host CPU to read frame data from QMU RXQ frame buffer with Chip Select Enable (CS), Read (RDN) while CMD pin (A2) is always low after RXQCR bit 3 ( Start DMA Access ) is set, which starts the QMU transfer operation. Like section 4.1 steps 15 (external IO base address 0x1F000000), 15 Read 0x1F *prxdata ++ Read 1-byte of frame data to system memory pointer by prxdata from the QMU RXQ through 0x1F address (the address line A2 is low CMD is low). Increase prxdata pointer by 1. - Page 38 -

39 Write To TXQ The device allows a transfer operation from the host CPU to write frame data to QMU TXQ frame buffer with Chip Select Enable (CS), Write (WRN) signals while CMD pin (A2) is always low after RXQCR bit 3 ( Start DMA Access ) is set, which starts the QMU transfer operation. Like section 3, steps 7 (external IO base address 0x1F000000), 7 Write 0x1F *ptxdata++ Write 1-byte of frame data pointer by ptxdata to the QMU TXQ through 0x1F address (the address line A2 is low CMD is low). Increase ptxdata pointer by Special Notices for 8-Bit Data Bus At KSZ462HLI 8-Bit mode, all registers MUST be accessed by low byte first then high byte with only one exception RXQCR register. When the bit 3 of RXQCR register (SDA Start DMA Access) is set, the QMU access starts immediately and any device access afterward is related to QMU. So the high byte of RXQCR need to be written first before SDA is set. The SDA is set only at four steps and there are: Section 3 Transmit step 3. Section 4.1 Receive Single Frame step 10. Section 4.2 Receive Multiple Frames step 11 and step 18. QMU Access The frame format for the transmit queue and receive queue are shown in the following tables in the 8-bit format. The TXQ will be written and RXQ will be read in the 8-bit operation. Transmit Queue (TXQ) Frame Format Packet Memory Bit 7 Bit 0 Address Offset 0 Low byte of Control Word - Transmit Frame ID 1 High byte of Control Word. E.g. 0x80 to set the transmit interrupt. 2 Low byte of Byte Count. E.g. (length & 0xff) 3 High byte of Byte Count. E.g. (length >> 8) 4 - up Transmit Packet Data (maximum size is 2000) - Page 39 -