HI Fully Integrated MIL-STD-1553 BC/RT/MT. HI-6200, HI-6202 Families. December HI-6200 Rev. C

Transcription

1 HI-6200 Fully Integrated MIL-STD-1553 BC/RT/MT HI-6200, HI-6202 Families December 2018 HI-6200 Rev C

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3 Overview 1 Overview The HI-6200 family is a fully integrated and dual redundant MIL-STD-1553 BC/RT/MT interface solution which includes 1553 protocol, SRAM and dual transceivers in single 80-pin plastic PQFP and QFN package configurations The devices are software compatible with the Data Device Corporation (DDC ) Mini-ACE, Enhanced Mini-ACE, Micro-ACE, Mini-ACE Mark3 and Total-ACE families of MIL-STD-1553 Terminals and offer additional features such as Error-Correcting Code (ECC) SRAM The compact single-chip monolithic design offers a significant space and cost saving over the older traditional multi-chip module approach 11 Bus Controller The BC is a programmable message-sequencing engine programmed using a set of 20 instruction op codes It greatly reduces the host s processing workload by autonomously supporting multi-frame message scheduling, message retry schemes, storage of message data in on-chip RAM, asynchronous message insertion and status/error reporting The Enhanced BC mode also includes a General Purpose Queue and user-defined interrupts to further enhance host communication 12 Remote Terminal The RT has been fully validated by a recognized independent third party RT memory management options include single, double, and 2 circular buffer modes for individual subaddresses The RT performs comprehensive error checking including word and format validation and checks for various transfer errors The RT supports flexible interrupt conditions, command illegalization and a programmable busy bit by subaddress In addition, the devices have an auto-boot feature necessary for MIL-STD-1760 compliance, whereby the terminal can initialize as an online RT with the busy bit set following power turn-on The HI provides a cost effective RT-only device 13 Monitor Terminal The family supports three monitor modes including a word monitor mode, a selective message monitor mode and a combined RT/Monitor Mode For new applications it is recommended to implement the selective message monitor mode Selective Message Monitor allows monitoring of 1553 messages and provides the ability to filter based on RT address, T/R bit and subaddress with no host processor intervention 14 Host Processor Interface Each device provides an 8/16-bit parallel host bus interface supporting a variety of processor configurations including shared RAM and DMA The host interface supports both non-multiplexed and multiplexed address/ data buses, non-zero wait mode for interfacing to processor address/data buses, and zero wait mode for interfacing to microcontroller I/O ports 15 Built in Test The family provides an autonomous built-in self-test capability The testing includes both RAM and protocol logic tests which may be initiated by the host processor Note: DDC, Mini-ACE, Enhanced Mini-ACE, Micro-ACE, Mini-ACE Mark3 and Total-ACE are registered trademarks of Data Device Corporation, Bohemia, NY, USA There is no affiliation between Data Device Corporation and Holt Integrated Circuits Inc 3

4 Overview 16 Features Dual Redundant MIL-STD-1553A/B/1760 Channel BC/RT/MT or RT/MT Modes RT-only device available (HI-6202) 64Kx16 ECC SRAM External RT Address Inputs MIL-STD-1760 RT Auto Boot +33V single supply operation Built-in Self-Test Generic 8/16-bit Processor Interface -40 C to +85 C or -55 C to +125 C No Limitations on transmit duty cycle 80-Pin PQFP package 12mm x 12mm x 16mm 80-Pin QFN package 12mm x 12mm x 08mm 17 Application Benefits Simplified Board Design and Layout Third Party RT Validated Single Die for Improved Reliability Fully Software Compatible to DDC ACE, Mini-ACE, Enhanced Mini-ACE, Micro-ACE, Mini-ACE Mark3 and Total-ACE 4

5 Overview 18 Block Diagram Shared RAM TX_INH A Host Data Bus D15 - D0 Data Buffers Data Bus Dual Encoder/Decoders Transceiver A Bus A Host Address Bus A15 - A0 Address Buffers Address Bus MIL-STD-1553 BC/RT/MT Protocol & Memory Management Transceiver B Bus B Host & Memory Control Signals Interrupt Request INT Host & Memory Interface Logic TX_INH B RT Address Bus RTAD4 - RTAD0, RTADP, RTADD_LAT Message Status CLK_IN, Control & Protocol Inputs 5

6 2 Registers and Command/Status Words Table 1 summarizes the device registers and corresponding addresses Table 1 Register Summary Hex Address Access Register Name Hard Reset Default 0x0000 RD/WR Interrupt Mask Register 1 0x0000 0x0001 RD/WR Configuration Register 1 0x0002 RD/WR Configuration Register 2 0x0003 WR Start/Reset Register 0x0003 RD Non-Enhanced BC or RT Command Stack Pointer / Enhanced BC Instruction List Pointer Register 0x0004 RD/WR BC Control Word / RT Subaddress Control Word Register 0x0005 RD/WR Time Tag Register 0x0006 RD Interrupt Status Register 1 0x0007 RD/WR Configuration Register 3 0x0008 RD/WR Configuration Register 4 0x0009 RD/WR Configuration Register 5 0x000A RD/WR RT/Monitor Data Stack Address Register 0x000B RD BC Frame Time Remaining Register 0x000C RD BC Time Remaining to Next Message Register 0x000D RD/WR Non-Enhanced BC Frame Time / Enhanced BC Initial Instruction Pointer / RT Last Command/MT Trigger Word Register 0x000E RD RT Status Word Register 0x000F RD RT BIT Word Register 0x0010 Test Mode Register 0 0x0011 Test Mode Register 1 0x0012 Test Mode Register 2 0x0013 Test Mode Register 3 0x0014 Test Mode Register 4 0x0015 Test Mode Register 5 0x0016 Test Mode Register 6 6

7 Hex Address Access Register Name Hard Reset Default 0x0017 Test Mode Register 7 0x0018 RD/WR Configuration Register 6 0x0019 RD/WR Configuration Register 7 0x001A Reserved 0x001B RD BC Condition Code Register 0x001B WR BC General Purpose Flag Register 0x001C RD BIT Test Status Register 0x001D RD/WR Interrupt Mask Register 2 0x001E RD Interrupt Status Register 2 0x001F RD/WR BC General Purpose Queue Pointer / RT-MT Interrupt Status Queue Pointer Register 7

8 21 Interrupt Mask Register #1, Read/Write 0x0000 Interrupt Mask Registers #1 is used to enable/disable interrupt requests for various operational conditions Bit No R/W Reset Bit Description 15 (MSB) 0 Reserved 14 R/W 0 Two Bit RAM Error Detected Setting this bit to logic 1 will generate an interrupt request in response to a two bit RAM error Bit 14 in Configuration Register #2 must be set to logic 1 to enable two bit error detection Note: The device ECC SRAM will automatically detect and correct single bit RAM errors Corrected single bit errors are not logged 13 R/W 0 BC/RT Transmitter Timeout 12 R/W 0 BC/RT Command Stack Rollover 11 R/W 0 MT Command Stack Rollover 10 R/W 0 MT Data Stack Rollover 9 R/W 0 Handshake Fail 8 R/W 0 BC Retry 7 R/W 0 RT Address Parity Error 6 R/W 0 Time Tag Rollover 5 R/W 0 RT Circular Buffer Rollover 4 R/W 0 BC Control Word/RT Subaddress Control Word EOM 3 R/W 0 BC End of Frame 2 R/W 0 Format Error 1 R/W 0 BC Status Set/RT Mode Code/MT Pattern Trigger 0 (LSB) R/W 0 End of Message 8

9 22 Configuration Register #1, Read/Write 0x0001 Configuration Registers #1 is used to select the device s mode of operation and for software control of operational attributes such as RT Status Word bits, RT Memory Management mode selection, Time-Tagging, etc Specific bit functionality depends on the selected mode of operation Table 2 summarizes the relevant bits for each mode Table 2 Configuration Register #1 Bit Summary by Mode of Operation BIT BC FUNCTION (Bits 11-0, Enhanced Mode Only) RT WITHOUT ALTERNATE STATUS RT WITH ALTERNATE STATUS (Enhanced Mode Only) MONITOR FUNCTION (Bits 12-0, Enhanced Mode Only) 15 (MSB) RT/BC-MT (Logic 0) (Logic 1) (Logic 1) (Logic 0) 14 MT/BC-RT (Logic 0) (Logic 0) (Logic 0) (Logic 1) 13 Current Area B/A Current Area B/A Current Area B/A Current Area B/A 12 Message Stop-On-Error Message Monitor Enabled (MMT) Message Monitor Enabled Message Monitor Enabled 11 Frame Stop-On-Error Dynamic Bus Control Acceptance S10 Trigger Word Enabled 10 9 Status Set Stop-On-Message Status Set Stop-On-Frame Busy S09 Start-On-Trigger Service Request S08 Stop-On-Trigger 8 Frame Auto-Repeat SSFLAG S07 Not Used 7 External Trigger Enabled RTFLAG (Enhanced Mode Only) S06 External Trigger Enabled 6 Internal Trigger Enabled Not Used S05 Not Used 5 Intermessage Gap Timer Enabled Not Used S04 Not Used 4 Retry Enabled Not Used S03 Not Used 3 Doubled / Single Retry Enabled Not Used S02 Not Used 2 BC Enabled (Read Only) Not Used S01 Monitor Enabled (Read Only) 1 BC Frame In Progress (Read Only) Not Used S00 Monitor Triggered (Read Only) 0 (LSB) BC Message In Progress (Read Only) RT Message In Progress (Enhanced mode only, Read Only) RT Message In Progress (Read Only) Monitor Active (Read Only) Notes: 1 The combined RT/Message Monitor mode uses the RT WITHOUT ALTERNATE STATUS or the RT WITH ALTERNATE STATUS bit definitions not the MONITOR FUNCTION bit definitions 9

10 2 In the alternate RT Status Word mode, bit 10 (Message Error) may also be set for an illegalized message (Broadcast-T/R bit subaddress-word count/mode code) Modes of operation are configured using a combination of bits 15, 14 and 12 in Configuration Register #1 and bit 15 in Configuration Register #3 See Table 3 for a summary of the bit combinations Table 3 Modes of Operation Config Reg #1 Config Reg #3 Bit 15 Bit 14 Bit 12 Bit 15 Mode 0 0 X 0 Non-ENHANCED BC (See Notes) (no Monitor modes available) 0 0 X 1 ENHANCED BC (no Monitor modes available) X Word Monitor Word Monitor (non-enhanced mode set) Message Monitor (ENHANCED mode set) 1 0 X 0 Non-ENHANCED RT (no Monitor modes available) ENHANCED RT/Word Monitor ENHANCED RT/Message Monitor 1 1 X X Idle Notes: 1 Following hardware reset (MSTCLR asserted) or software reset (by means of the Start/Reset Register), BC/RT/ MT versions of the device will initialize to (non-transmitting) BC mode, while RT only versions will initialize to Idle mode In both cases, the values of bits 15 and 14 will initialize to logic 0 2 Notes 2 thru 6 are only applicable to the BC/RT/MT versions of the device: If the device is switched from RT to combined RT/Monitor mode in the middle of an RT message, the message will be completed 3 If the device is switched from combined RT/Monitor mode to RT mode in the middle of an RT message or Monitor message, the message will be completed 4 If the device is switched from either RT mode or Monitor mode to either BC mode or Idle mode in the middle of an RT message, the message will be aborted 5 If the device is switched from non-enhanced RT mode to Idle mode, there is no effect 6 If the device is switched from (ENHANCED or non-enhanced) BC mode to Idle mode in the middle of a message, the message will be aborted 7 In BC Mode ((bits [15, 14] in Configuration Register #1 set to [0, 0] respectively), bit 12 of Configuration Register #1 functions as MESSAGE STOP-ON-ERROR bit and has no affect on mode of operation 10

11 23 Configuration Register #2, Read/Write 0x0002 Bit No R/W Reset Bit Description 15 (MSB) R/W 0 Enhanced Interrupts 14 R/W 0 Two Bit RAM Error Detect Setting this bit to logic 1 enables two bit RAM error detection An interrupt may be generated for detection of two bit errors by setting bit 14 in the Interrupt Mask Register #1 Note: The device ECC SRAM will automatically detect and correct single bit RAM errors, regardless of the state of this bit Corrected single bit errors are not logged 13 R/W 0 Busy Lookup Table Enable 12 R/W 0 Rx Subaddress Double Buffer Enable 11 R/W 0 Overwrite Invalid Data 10 R/W Word Boundary Disable 9 R/W 0 Time Tag Resolution 2 8 R/W 0 Time Tag Resolution 1 7 R/W 0 Time Tag Resolution 0 6 R/W 0 Clear Time Tag on Synchronize 5 R/W 0 Load Time Tag on Synchronize 4 R/W 0 Interrupt Status Auto Clear 3 R/W 0 Level / Pulse Interrupt Request 2 R/W 0 Clear Service Request 1 R/W 0 Enhanced RT Memory Management 0 (LSB) R/W 0 Separate Broadcast Data 11

12 24 Command Stack Pointer Register/ Enhanced BC Instruction List Register, Read Only 0x0003 This register provides the host processor read access to the current value of the Stack Pointer for RT, MT and nonenhanced BC modes Bit No R/W Reset Bit Description 15 (MSB) R 0 Command Stack Pointer, bit 15 0 (LSB) R 0 Command Stack Pointer, bit 0 25 Start/Reset Register, Write Only 0x0003 Bit No R/W Reset Bit Description 15 (MSB) 0 Reserved 14 0 Reserved 13 0 Reserved 12 0 Reserved 11 W 0 Clear RT Halt 10 W 0 Clear Self-Test Register 9 W 0 Initiate RAM Self-Test 8 W 0 Reserved 7 W 0 Initiate Protocol Self-Test 6 W 0 BC/MT Stop-On-Message 5 W 0 BC Stop-On-Frame 4 W 0 Time Tag Test Clock 3 W 0 Time Tag Reset 2 W 0 Interrupt Reset 1 W 0 BC/MT Start 0 (LSB) W 0 Reset 12

13 26 BC Control Word Register, Read/Write 0x0004 Bit No R/W Reset Bit Description 15 (MSB) R/W 0 Transmit Time Tag for Synchronize Mode Command 14 R/W 0 Message Error Mask 13 R/W 0 Service Request Bit Mask 12 R/W 0 Busy Bit Mask 11 R/W 0 Subsystem Flag Bit Mask 10 R/W 0 Terminal Flag Bit Mask 9 R/W 0 Reserved Bits Mask 8 R/W 0 Retry Enabled 7 R/W 0 Bus Channel A/B 6 R/W 0 Off-Line Self-Test 5 R/W 0 Mask Broadcast Bit 4 R/W 0 EOM Interrupt Enable 3 R/W A/B Select 2 R/W 0 Mode Code Format 1 R/W 0 Broadcast Format 0 (LSB) R/W 0 RT-to-RT Format 13

14 27 RT Subaddress Control Word Register, Read/Write 0x0004 Bit No R/W Reset Bit Description 15 (MSB) R/W 0 Rx: Double/Global Buffer Enable 14 R/W 0 Tx: EOM INT 13 R/W 0 Tx: CIRC BUF INT 12 R/W 0 Tx: Memory Management 2 (MM2) 11 R/W 0 Tx: Memory Management 1 (MM1) 10 R/W 0 Tx: Memory Management 0 (MM0) 9 R/W 0 Rx: EOM INT 8 R/W 0 Rx: CIRC BUF INT 7 R/W 0 Rx: Memory Management 2 (MM2) 6 R/W 0 Rx: Memory Management 1 (MM1) 5 R/W 0 Rx: Memory Management 0 (MM0) 4 R/W 0 BCST: EOM INT 3 R/W 0 BCST: CIRC BUF INT 2 R/W 0 BCST: Memory Management 2 (MM2) 1 R/W 0 BCST: Memory Management 1 (MM1) 0 (LSB) R/W 0 BCST: Memory Management 0 (MM0) 14

15 28 Time Tag Register, Read/Write 0x0005 Bit No R/W Reset Bit Description 15 (MSB) R/W 0 Time Tag, bit 15 0 (LSB) R/W 0 Time Tag, bit 0 The resolution of the Time Tag Register (μs/lsb) is programmable by means of bits 9, 8, and 7 of Configuration Register #2, Read/Write 0x0002 on page 11 See Table 4 below Table 4 Time Tag Register Resolution Configuration Register #2 BIT9 TTR2 BIT8 TTR1 BIT7 TTR0 Time Tag Resolution Rollover Time (Modulus) μs 4194 sec μs 2097 sec μs 1048 sec μs 524 ms μs 262 ms μs 131 ms TEST MODE N/A EXTERNAL CLOCK (see NOTE) N/A 15

16 29 Interrupt Status Register #1, Read Only 0x0006 Bit No R/W Reset Bit Description 15 (MSB) R 0 Master Interrupt 14 R 0 Two Bit RAM Error Detected This bit, if enabled by bit 14, Interrupt Mask Register #1, will be set when a two bit RAM error is detected Bit 14 in Configuration Register #2, must be set to logic 1 to enable two bit error detection Note: Single bit RAM errors are automatically detected and corrected by the on-chip ECC SRAM 13 R 0 Transmitter Timeout 12 R 0 BC/RT Command Stack Rollover 11 R 0 MT Command Stack Rollover 10 R 0 MT Data Stack Rollover 9 R 0 Handshake Fail 8 R 0 BC Retry 7 R 0 RT Address Parity Error 6 R 0 Time Tag Rollover 5 R 0 RT Circular Buffer Rollover 4 R 0 BC Control Word / RT Subaddress Control Word EOM 3 R 0 BC End of Frame 2 R 0 Format Error 1 R 0 BC Status Set / RT Mode Code / MT Pattern Trigger 0 (LSB) R 0 End of Message 16

17 210 Configuration Register #3, Read/Write 0x0007 Bit No R/W Reset Bit Description 15 (MSB) R/W 0 Enhanced Mode Enable 14 R/W 0 BC/RT Command Stack Size 1 13 R/W 0 BC/RT Command Stack Size 0 12 R/W 0 MT Command Stack Size 1 11 R/W 0 MT Command Stack Size 0 10 R/W 0 MT Data Stack Size 2 9 R/W 0 MT Data Stack Size 1 8 R/W 0 MT Data Stack Size 0 7 R/W 0 Illegalization Disabled 6 R/W 0 Override Mode T/R Error 5 R/W 0 Alternate Status Word Enable 4 R/W 0 Illegal Rx Transfer Disable 3 R/W 0 Busy RX Transfer Disable 2 R/W 0 RTFAIL / RTFLAG Wrap Enable 1 R/W A Mode Codes Enable 0 (LSB) R/W 0 Enhanced Mode Code Handling 17

18 211 Configuration Register #4, Read/Write 0x0008 Bit No R/W Reset Bit Description 15 (MSB) R/W 0 External Bit Word Enable 14 R/W 0 Inhibit Bit Word If Busy 13 R/W 0 Mode Command Override Busy 12 R/W 0 Expanded BC Control Word Enable 11 R/W 0 Broadcast Mask ENA/XOR 10 R/W 0 Retry If 1553A and Message Error 9 R/W 0 Retry if Status Set 8 R/W 0 1st Retry ALT/ SAME Bus 7 R/W 0 2nd Retry ALT/ SAME Bus 6 R/W 0 Valid Message Error / No Data 5 R/W 0 Valid Busy Bit / No Data 4 R/W 0 MT Tag Gap Option 3 R/W 0 Latch RT Address with Configuration Register #5 2 R/W 0 Test Mode 2 1 R/W 0 Test Mode 1 0 (LSB) R/W 0 Test Mode 0 18

19 212 Configuration Register #5, Read/Write 0x0009 Bit No R/W Reset Bit Description 15 (MSB) R/W 0 12 / 16 MHz Clock Select 14 R/W 0 Single-Ended Select 13 R/W 0 External Tx Inhibit A 12 R/W 0 External Tx Inhibit B 11 R/W 0 Expanded Crossing Enabled 10 R/W 0 Response Time Out Select 1 9 R/W 0 Response Time Out Select 0 8 R/W 0 Gap Check Enabled 7 R/W 0 Broadcast Disabled 6 R/W 0 RT Address Latch / Transparent 5 R/W 0 RT Address 4 4 R/W 0 RT Address 3 3 R/W 0 RT Address 2 2 R/W 0 RT Address 1 1 R/W 0 RT Address 0 0 (LSB) R/W 0 RT Address Parity 213 RT/Monitor Data Stack Address Register, Read/Write 0x000A Bit No R/W Reset Bit Description 15 (MSB) R/W 0 RT/Monitor Data Stack Address, bit 15 0 (LSB) R/W 0 RT/Monitor Data Stack Address, bit 0 19

20 214 BC Frame Time Remaining Register, Read Only 0x000B Bit No R/W Reset Bit Description 15 (MSB) R 0 BC Frame Time Remaining, bit 15 0 (LSB) R 0 BC Frame Time Remaining, bit BC Message Time Remaining Register, Read Only 0x000C Bit No R/W Reset Bit Description 15 (MSB) R 0 BC Message Time Remaining, bit 15 0 (LSB) R 0 BC Message Time Remaining, bit Non-Enhanced BC Frame Time/Enhanced BC Initial Instruction Pointer / RT Last Command / MT Trigger Register, Read/Write 0x000D Bit No R/W Reset Bit Description 15 (MSB) R/W 0 Non-Enhanced BC Frame Time/Enhanced BC Initial Instruction Pointer / RT Last Command / MT Trigger Register, bit 15 0 (LSB) R/W 0 Non-Enhanced BC Frame Time/Enhanced BC Initial Instruction Pointer / RT Last Command / MT Trigger Register, bit 0 20

21 217 RT Status Word Register, Read Only 0x000E Bit No R/W Reset Bit Description 15 (MSB) R 0 Logic 0 14 R 0 Logic 0 13 R 0 Logic 0 12 R 0 Logic 0 11 R 0 Logic 0 10 R 0 Message Error 9 R 0 Instrumentation 8 R 0 Service Request 7 R 0 Reserved 6 R 0 Reserved 5 R 0 Reserved 4 R 0 Broadcast Command Received 3 R 0 Busy 2 R 0 SSFLAG 1 R 0 Dynamic Bus Control Accept 0 (LSB) R 0 Terminal Flag 21

22 218 RT Bit Word Register, Read Only 0x000F Bit No R/W Reset Bit Description 15 (MSB) R 0 Transmitter Timeout 14 R 0 Loop Test Failure B 13 R 0 Loop Test Failure A 12 R 0 Handshake Failure 11 R 0 Transmitter Shutdown B 10 R 0 Transmitter Shutdown A 9 R 0 Terminal Flag Inhibited 8 R 0 Bit Test Fail 7 R 0 High Word Count 6 R 0 Low Word Count 5 R 0 Incorrect Sync Received 4 R 0 Parity/Manchester Error Received 3 R 0 RT to RT Gap / Sync / Address Error 2 R 0 RT to RT No Response Error 1 R 0 RT to RT 2nd Command Word Error 0 (LSB) R 0 Command Word Contents Error 22

23 219 Configuration Register #6, Read/Write 0x0018 Bit No R/W Reset Bit Description 15 (MSB) R/W 0 Enhanced Bus Controller 14 R/W 0 Enhanced CPU Access 13 R/W 0 Command Stack Pointer Increment on EOM (RT, MT) 12 R/W 0 Global Circular Buffer Enable 11 R/W 0 Global Circular Buffer Size 2 10 R/W 0 Global Circular Buffer Size 1 9 R/W 0 Global Circular Buffer Size 0 8 R/W 0 Disable Invalid Messages to Interrupt Statu Queue 7 R/W 0 Disable Valid Messages to Interrupt Status Queue 6 R/W 0 Interrupt Status Queue Enable 5 R/W 0 RT Address Source 4 R/W 0 Enhanced Message Monitor 3 R/W 0 Reserved 2 R/W 0 64-Word Register Space Clock Select Bits [1,0] These two bits select the Clock Frequency according to the table below Clock Select Bit 1 Clock Select Bit 0 Clock Frequency (MHz) 1 0 (LSB) R/W

24 220 Configuration Register #7, Read/Write 0x0019 Bit No R/W Reset Bit Description 15 (MSB) R/W 0 Memory Management Base Address R/W 0 Memory Management Base Address R/W 0 Memory Management Base Address R/W 0 Memory Management Base Address R/W 0 Memory Management Base Address R/W 0 Memory Management Base Address 10 9 R/W 0 Reserved 8 R/W 0 Reserved 7 R/W 0 Reserved 6 R/W 0 Reserved 5 R/W 0 Reserved 4 R/W 0 RT Halt Enable 3 R/W B Response Time 2 R/W 0 Enhanced Time Tag Synchronize 1 R/W 0 Enhanced BC Watchdog Timer Enabled 0 (LSB) R/W 0 Mode Code Reset / INCMD Select 24

25 221 BC Condition Code Register, Read Only 0x001B Bit No R/W Reset Bit Description 15 (MSB) R 0 Logic 1 14 R 0 Retry 1 13 R 0 Retry 0 12 R 0 Bad Message 11 R 0 Message Status Set 10 R 0 Good Block Transfer 9 R 0 Format Error 8 R 0 No Response 7 R 0 General Purpose Flag 7 6 R 0 General Purpose Flag 6 5 R 0 General Purpose Flag 5 4 R 0 General Purpose Flag 4 3 R 0 General Purpose Flag 3 2 R 0 General Purpose Flag 2 1 R 0 Equal Flag / General Purpose Flag 1 0 (LSB) R 0 Less Than Flag / General Purpose Flag 0 Notes: 1 If the device is not online in enhanced BC mode, the BC Condition Code Register will always return a value of 0x

26 222 BC General Purpose Flag Register, Write Only 0x001B Bit No R/W Reset Bit Description 15 (MSB) W 0 Clear General Purpose Flag 7 14 W 0 Clear General Purpose Flag 6 13 W 0 Clear General Purpose Flag 5 12 W 0 Clear General Purpose Flag 4 11 W 0 Clear General Purpose Flag 3 10 W 0 Clear General Purpose Flag 2 9 W 0 Clear General Purpose Flag 1 8 W 0 Clear General Purpose Flag 0 7 W 0 Set General Purpose Flag 7 6 W 0 Set General Purpose Flag 6 5 W 0 Set General Purpose Flag 5 4 W 0 Set General Purpose Flag 4 3 W 0 Set General Purpose Flag 3 2 W 0 Set General Purpose Flag 2 1 W 0 Set General Purpose Flag 1 0 (LSB) W 0 Set General Purpose Flag 0 26

27 223 BIT Test Status Flag Register, Read Only 0x001C Bit No R/W Reset Bit Description 15 (MSB) R 0 Protocol Built-In Test Complete 14 R 0 Protocol Built-In Test In-Progress 13 R 0 Protocol Built-In Test Passed 12 R 0 Protocol Built-In Test Abort 11 R 0 Protocol Built-In Test Complete / In-Progress 10 R 0 Logic 0 9 R 0 Logic 0 8 R 0 Logic 0 7 R 0 RAM Built-In Test Complete 6 R 0 RAM Built-In Test In-Progress 5 R 0 RAM Built-In Test Passed 4 R 0 Logic 0 3 R 0 Logic 0 2 R 0 Logic 0 1 R 0 Logic 0 0 (LSB) R 0 Logic 0 27

28 224 Interrupt Mask Register #2, Read/Write 0x001D Bit No R/W Reset Bit Description 15 (MSB) R/W 0 Not Used 14 R/W 0 BC Op Code Parity Error 13 R/W 0 RT Illegal Command/Message MT Message Received 12 R/W 0 General Purpose Queue / Interrupt Status Queue Rollover 11 R/W 0 Call Stack Pointer Register Error 10 R/W 0 BC Trap Op Code 9 R/W 0 RT Command Stack 50% Rollover 8 R/W 0 RT Circular Buffer 50% Rollover 7 R/W 0 Monitor Command Stack 50% Rollover 6 R/W 0 Monitor Data Stack 50% Rollover 5 R/W 0 Enhanced BC IRQ3 4 R/W 0 Enhanced BC IRQ2 3 R/W 0 Enhanced BC IRQ1 2 R/W 0 Enhanced BC IRQ0 1 R/W 0 Bit Test Complete 0 (LSB) R/W 0 Not Used 28

29 225 Interrupt Status Register #2, Read Only 0x001E Bit No R/W Reset Bit Description 15 (MSB) R 0 Master Interrupt 14 R 0 BC Op Code Parity Error 13 R 0 RT Illegal Command/Message MT Message Received 12 R 0 General Purpose Queue / Interrupt Status Queue Rollover 11 R 0 Call Stack Pointer Register Error 10 R 0 BC Trap Op Code 9 R 0 RT Command Stack 50% Rollover 8 R 0 RT Circular Buffer 50% Rollover 7 R 0 Monitor Command Stack 50% Rollover 6 R 0 Monitor Data Stack 50% Rollover 5 R 0 Enhanced BC IRQ3 4 R 0 Enhanced BC IRQ2 3 R 0 Enhanced BC IRQ1 2 R 0 Enhanced BC IRQ0 1 R 0 Bit Test Complete 0 (LSB) R 0 Interrupt Chain Bit 29

30 226 BC General Purpose Queue Pointer Register / RT, MT Interrupt Status Queue Pointer Register, Read/Write 0x001F Bit No R/W Reset Bit Description 15 (MSB) R/W 0 Queue Pointer Base Address R/W 0 Queue Pointer Base Address R/W 0 Queue Pointer Base Address R/W 0 Queue Pointer Base Address R/W 0 Queue Pointer Base Address R/W 0 Queue Pointer Base Address 10 9 R/W 0 Queue Pointer Base Address 9 8 R/W 0 Queue Pointer Base Address 8 7 R/W 0 Queue Pointer Base Address 7 6 R/W 0 Queue Pointer Base Address 6 5 R/W 0 Queue Pointer Address 5 4 R/W 0 Queue Pointer Address 4 3 R/W 0 Queue Pointer Address 3 2 R/W 0 Queue Pointer Address 2 1 R/W 0 Queue Pointer Address 1 0 (LSB) R/W 0 Queue Pointer Address 0 30

31 The following sections list various Command and Status Words stored in RAM 227 BC Mode Block Status Word Bit No Bit Description 15 (MSB) EOM 14 SOM 13 Channel B / A 12 Error Flag 11 Status Set 10 Format Error 9 No Response Timeout 8 Loop Test Fail 7 Masked Status Set 6 Retry Count 1 5 Retry Count 0 4 Good Data Block Transfer 3 Wrong Status Address / No Gap 2 Word Count Error 1 Incorrect Sync Type 0 (LSB) Invalid Word 31

32 228 RT Mode Block Status Word Bit No Bit Description 15 (MSB) EOM 14 SOM 13 Channel B / A 12 Error Flag 11 RT to RT Format 10 Format Error 9 No Response Timeout 8 Loop Test Fail 7 Data Stack Rollover 6 Illegal Command Word 5 Word Count Error 4 Incorrect Data Sync 3 Invalid Word 2 RT to RT Gap / Sync / Address Error 1 RT to RT 2nd Command Error 0 (LSB) Command Word Contents Error 32

33 Command Word Bit No Bit Description 15 (MSB) Remote Terminal Address Bit 4 14 Remote Terminal Address Bit 3 13 Remote Terminal Address Bit 2 12 Remote Terminal Address Bit 1 11 Remote Terminal Address Bit 0 10 Transmit / Receive 9 Subaddress / Mode Code Bit 4 8 Subaddress / Mode Code Bit 3 7 Subaddress / Mode Code Bit 2 6 Subaddress / Mode Code Bit 1 5 Subaddress / Mode Code Bit 0 4 Data Word Count / Mode Code Bit 4 3 Data Word Count / Mode Code Bit 3 2 Data Word Count / Mode Code Bit 2 1 Data Word Count / Mode Code Bit 1 0 (LSB) Data Word Count / Mode Code Bit 0 33

34 230 Word Monitor Identification Word Bit No Bit Description 15 (MSB) Gap Time (MSB) Gap Time (LSB) 7 Word Flag 6 This RT 5 Broadcast 4 Error 3 Command / Data 2 Channel B / A 1 Contiguous Data / Gap 0 (LSB) Mode_Code 34

35 231 Message Monitor Mode Block Status Word Bit No Bit Description 15 (MSB) EOM 14 SOM 13 Channel B / A 12 Error Flag 11 RT to RT Transfer 10 Format Error 9 No Response Timeout 8 Good Data Block Transfer 7 Data Stack Rollover 6 Reserved 5 Word Count Error 4 Incorrect Sync 3 Invalid Word 2 RT to RT Gap / Sync / Address Error 1 RT to RT 2nd Command Error 0 (LSB) Command Word Contents Error 35

36 232 RT/Monitor Interrupt Status Word (For Interrupt Status Queue) Bit No Message Interrupt Event Non-Message Interrupt Event 15 (MSB) Transmitter Timeout Not Used 14 Illegal Command Not Used 13 Monitor Data Stack 50% Rollover Not Used 12 Monitor Data Stack Rollover Not Used 11 RT Circular Buffer 50% Rollover Not Used 10 RT Circular Buffer Rollover Not Used Monitor Command (Descriptor) Stack 50% Rollover Monitor Command (Descriptor) Stack Rollover RT Command (Descriptor) Stack 50% Rollover RT Command (Descriptor) Stack Rollover Not Used Not Used Not Used Not Used 5 Handshake Fail Not Used 4 Format Error Time Tag Rollover 3 Mode Code Interrupt RT Address Parity Error 2 Subaddress Control Word EOM Protocol Self-Test Complete 1 End-Of-Message (EOM) Two Bit RAM Error Detected 0 (LSB) Logic 1 Logic 0 36

37 Status Word Bit No Bit Description 15 (MSB) Remote Terminal Address Bit 4 14 Remote Terminal Address Bit 3 13 Remote Terminal Address Bit 2 12 Remote Terminal Address Bit 1 11 Remote Terminal Address Bit 0 10 Message Error 9 Instrumentation 8 Service Request 7 Reserved 6 Reserved 5 Reserved 4 Broadcast Command Received 3 Busy 2 SSFLAG 1 Dynamic Bus Control Acceptance 0 (LSB) Terminal Flag 37

38 Signal and Pin Descriptions 3 Signal and Pin Descriptions Table 5 Power and Ground Signal Name Pin Description VDD_CHA Volt transceiver power, Channel A VDD_CHB Volt transceiver power, Channel B Logic_VDD 2, 8, 20, 27, 40, V logic power Logic_GND 1, 7, 19, 26, 39, 48, 50 Logic ground RAM_REG_VDD Volt power for internal RAM voltage regulator Table 6 MIL-STD-1553 Isolation Transformer Connections Signal Name Function Pin Description TX/RX-A Analog I/O 68 TX/RX-A Analog I/O 70 TX/RX-B Analog I/O 71 Analog Transmit/Receive bus connections Connect directly to MIL-STD-1553 isolation transformers TX/RX-B Analog I/O 73 38

39 Signal and Pin Descriptions Table 7 Data Bus Signal Name Function Pin Description D15 (MSB) Digital I/O 42 D14 Digital I/O 41 D13 Digital I/O 38 D12 Digital I/O 37 D11 Digital I/O 36 D10 Digital I/O 35 D9 Digital I/O 24 D8 Digital I/O 23 D7 Digital I/O 22 D6 Digital I/O 21 D5 Digital I/O 18 D4 Digital I/O bit bi-directional tri-state data bus for host read/write operations on registers and shared RAM All bus read/write operations transact 16 bit words, but host bus width can be configured for 8 or 16 bits For a 16-bit bus, all pins D15:0 are used For 8-bit bus width, pins D15:8 are not connected 16-bit words are transacted over an 8-bit bus as a pair of byte operations, with data presented sequentially on pins D7:0 For compatibility with different host processors, the BENDI input determines whether the low order byte is transferred before the high order byte, or vice versa D3 Digital I/O 6 D2 Digital I/O 5 D1 Digital I/O 4 D0 (LSB) Digital I/O 3 39

40 Signal and Pin Descriptions Table 8 Host Address Bus Signal Name Function Pin Description A15 (MSB) Digital Input 44 A14 Digital Input 43 A13 Digital Input 49 A12 Digital Input 33 A11 Digital Input 32 A10 Digital Input 80 A9 Digital Input 30 A8 Digital Input 29 A7 Digital Input bit input address bus for host read/write operations on registers and shared RAM A6 Digital Input 34 A5 Digital Input 16 A4 Digital Input 15 A3 Digital Input 14 A2 Digital Input 12 A1 Digital Input 11 A0 (LSB) Digital Input 10 40

41 Signal and Pin Descriptions Table 9 Host Interface Signal Name Function Pin Description Chip Enable, active low CE Digital Input 52 When asserted, this pin enables host read or write accesses to device RAM or registers This pin is normally connected to a Chip Select output from the host s bus interface and is used by the host to select the device for a transfer to/from either RAM or registers BWID Digital Input 58 Configuration pin for host bus width High selects 16-bit bus width, low selects 8-bit bus width Configuration pin for host bus read/write control signal style BTYPE Digital Input 55 High selects Intel style using separate read strobe OE (output enable) and write strobe WE Low selects Motorola style using single active-low read/write strobe STR and read/write select signal, R/W Read / Write R/W / WE Digital Input 57 Read/write direction signal R/W when BTYPE pin is low Active-low Write Enable WE when BTYPE pin is high Used for host read or write accesses to device RAM or registers This pin or the CE pin should be high during all address transitions STR / OE Digital Input 46 Active-low common read/write strobe STR when BTYPE pin is low Active-low Output Enable OE when BTYPE pin is high Used for host read or write accesses to device RAM or registers WPOL Digital Input 59 Configuration pin for WAIT output polarity When the WPOL pin is low, the wait output is active low (WAIT) When WPOL is high, the wait output is active high (WAIT) Host bus read cycle WAIT or WAIT output The WPOL input pin sets the output polarity for this wait output WAIT / WAIT Digital Output 53 RAM Read cycles are slower than write cycles, but prefetching speeds up data availability for multi-word sequential address read cycles For every new RAM read cycle, the device asserts WAIT Connected to the processor WAIT or WAIT input, this action inserts one or more processor wait states (depending on processor clock frequency) while the HI-6200 fetches the first word After reading each HI-6200 RAM address, the device prefetches and retains data from the next address If the next bus access reads that sequential address, the data is ready without WAIT assertion Thus WAIT assertion only occurs for the first word read NOTE: Register reads don t use prefetch therefore will have a WAIT cycle during every address read, whether sequential or not 41

42 Signal and Pin Descriptions Signal Name Function Pin Description Most Significant Byte/Least Significant Byte MSB / LSB Digital Input 74 For 8-bit bus width, the input signal (MSB / LSB) is used to indicate which byte of the 16-bit word is currently being transferred (MSB or LSB) The logic sense of MSB / LSB is controlled by the BENDI input (see BENDI pin description and Table 10) If BENDI is connected to logic 0, MSB / LSB should be asserted low (logic 0 ) to indicate the transfer of the least significant byte and high (logic 1 ) to indicate the transfer of the most significant byte If BENDI is connected to logic 1, MSB / LSB should be asserted low (logic 0 ) to indicate the transfer of the most significant byte and high (logic 1 ) to indicate the transfer of the least significant byte See Table 10 MSB / LSB is Don t Care for 16-bit bus width BENDI Digital Input 65 Big Endian Configuration Pin The BENDI pin works in conjunction with the MSB / LSB and BWID pins to determine the endianness or byte order of 16-bit word transfers to the HI-6200 Table Table 10 below summarizes the interoperability of the three pins MEM / REG Digital Input 45 Memory or Register Selects between memory access (MEM / REG = "1") or register access (MEM / REG = "0") Usually connected to either a CPU address line or address decoder output Table 10 BENDI Pin Functionality The BENDI and MSB / LSB pins are used as outlined below to set the order for byte accesses when transacting 16-bit words on 16-bit or 8-bit host busses WR RD BENDI BWID MSB / LSB μp/hi-6200 Data Bus Pins HI-6200 internal RAM or Register 16-bit Word HI-6200 internal RAM or Register 16-bit Word μp/hi-6200 Data Bus Pins D[7:0] Bits[7:0] Bits[7:0] D[7:0] D[7:0] Bits[15:8] Bits[15:8] D[7:0] 0 1 X D[15:0] Bits[7:0], Bits[15:8] Bits[7:0], Bits[15:8] D[15:0] D[7:0] Bits[15:8] Bits[15:8] D[7:0] D[7:0] Bits[7:0] Bits[7:0] D[7:0] 1 1 X D[15:0] Bits[15:8], Bits[7:0] Bits[15:8], Bits[7:0] D[15:0] 42

43 Signal and Pin Descriptions Table 11 RT Address Signal Name Function Pin Description RTAD4 (MSB) Digital Input 63 RTAD3 RTAD2 RTAD1 Digital Input Digital Input Digital Input RT Address inputs If bit 5 of Configuration Register #6, RT ADDRESS SOURCE, is programmed to logic "0" (default), then the RT address is provided by these 5 input signals and RT address parity is provided by the RTADP signal described below If RT ADDRESS SOURCE is programmed to logic "1", then the RT address and parity are under software control, via data lines D5-D0 In this case, the RTAD4 RTAD0 and RTADP signals are not used RTAD0 (LSB) Digital Input 78 Remote Terminal Address Parity RTADP Digital Input 79 This input signal must provide an odd parity sum with RTAD4 RTAD0 in order for the RT to respond to non-broadcast commands That is, there must be an odd number of logic "1"s from among RTAD4 RTAD0 and RTADP RT Address Latch Input signal used to control the internal RT address latch If RT_AD_LAT is connected to logic "0", then the RT is configured to accept a hardwired RT address from RTAD4 RTAD0 and RTADP If RT_AD_LAT is initially logic "0", and then transitions to logic "1", the values presented on RTAD4 RTAD0 and RTADP will be latched internally on the rising edge of RT_AD_LAT If RT_AD_LAT is connected to logic "1", then the RT address is latchable under host processor control In this case, there are two possibilities: 1 If bit 5 of Configuration Register #6, RT ADDRESS SOURCE, is programmed to logic "0" (default), then the source of the RT Address is the RTAD4 RTAD0 and RTADP input signals RT_AD_LAT Digital Input 60 2 If RT ADDRESS SOURCE is programmed to logic "1", then the source of the RT Address is the lower 6 bits of the processor data bus, D5 D1 (for RTAD4 0) and D0 (for RTADP) In either of these two cases (with RT_AD_LAT = "1"), the processor will cause the RT address to be latched by: 1 Writing bit 15 of Configuration Register #3, ENHANCED MODE ENABLE, to logic "1" 2 Writing bit 3 of Configuration Register #4, LATCH RT ADDRESS WITH CONFIGURATION REGISTER #5, to logic "1" 3 Writing to Configuration Register #5 In the case of RT ADDRESS SOURCE = "1", then the values of RT address and RT address parity must be written to the lower 6 bits of Configuration Register #5, via D5 D0 In the case where RT ADDRESS SOURCE = "0", the bit values presented on D5 D0 become "don't care" 43

44 Signal and Pin Descriptions Table 12 Miscellaneous Signals Signal Name Function Pin Description In-command or Mode Code Reset The function of this pin is controlled by bit 0 of Configuration Register #7, MODE CODE RESET/INCMD SELECT If this register bit is logic "0" (default), INCMD will be active on this pin For BC, RT, or Selective Message Monitor modes, INCMD is asserted low whenever a message is being processed INCMD / MCRST Digital Output 56 In Word Monitor mode, INCMD will be asserted low for as long as the monitor is online For RT mode, if MODE CODE RESET/INCMD SELECT is programmed to logic "1", MCRST will be active In this case, MCRST will be asserted low for two clock cycles following receipt of a Reset remote terminal mode command In BC or Monitor modes, if MODE CODE RESET/INCMD SELECT is logic "1", this signal is inoperative; ie, in this case, it will always output a value of logic "1" Subsystem Flag (RT) or External Trigger (BC/Word Monitor) input In RT mode, if this input is asserted low, the Subsystem Flag bit will be set in the RT Status Word If the SSFLAG input is logic "0" while bit 8 of Configuration Register #1 (SUBSYSTEM FLAG) has been programmed to logic "1", the Subsystem Flag RT Status Word bit will become logic "1," but bit 8 of Configuration Register #1, SUBSYSTEM FLAG, will return logic "1" when read That is, the sense on the SSFLAG input has no effect on the SUBSYSTEM FLAG register bit SSFLAG / EXT_TRIG Digital Input 75 In the non-enhanced BC mode, this signal operates as an External Trigger input In BC mode, if the external BC Start option is enabled (bit 7 of Configuration Register #1), a low to high transition on this input will issue a BC Start Command, starting execution of the current BC frame In the enhanced BC mode, during the execution of a Wait for External Trigger (WTG) instruction, the BC will wait for a low-to-high transition on EXT_TRIG before proceeding to the next instruction In the Word Monitor mode, if the external trigger is enabled (bit 7 of Configuration Register #1), a low to high transition on this input will initiate a monitor start This input has no effect in Message Monitor mode 44

45 Signal and Pin Descriptions Signal Name Function Pin Description Interrupt Request output If the LEVEL / PULSE interrupt bit (bit 3) of Configuration Register #2 is logic "0", a negative pulse of approximately 500 ns is output on INT to signal an interrupt request If LEVEL / PULSE is logic 1, a low level interrupt request output will be asserted on INT The level interrupt will be cleared (high) after either: INT Digital Output 54 1 The processor writes a value of logic "1" to INTERRUPT RESET, bit 2 of the Start/Reset Register; or 2 If bit 4 of Configuration Register #2, INTERRUPT STATUS AUTO-CLEAR is logic "1", then reading the Interrupt Status Register (#1 and/or #2) that is requesting an interrupt enabled by the corresponding Interrupt Mask Register will clear INT However, for the case where both Interrupt Status Register #1 and Interrupt Status Register #2 have bits set reflecting interrupt events, it will be necessary to read both interrupt status registers in order to clear INT CLOCK_IN TX_INH_A TX_INH_B Digital Input Digital Input Digital Input MHz, 40 MHz, 20 MHz, or 16 MHz clock input 67 Transmitter inhibit inputs for Channel A and Channel B For normal operation, these inputs should be connected to logic "0" To force a shutdown of Channel A and / or Channel B, a value of logic 66 "1" should be applied to the respective TX_INH input MSTCLR Digital Input 9 Master Clear Active low Reset input, normally asserted low following power turnon RSTBITEN Digital Input 64 If this input is set to logic 1, the Built-In-Self-Test (BIST) will be enabled after hardware reset (for example, following power-up) A logic 0 input disables both the power-up and user-initiated automatic BIST RTBOOT Digital Input 31 If RTBOOT is connected to logic 0, the device will initialize in RT mode with the Busy status word bit set following power turn-on If RTBOOT is hardwired to logic 1, the device will initialize in either Idle mode (for an RT-only part), or in BC mode (for a BC/RT/MT part) TAG_CLK Digital Input 25 Time Tag Clock External clock that may be used to increment the Time Tag Register This option is selected by setting Bits 7, 8 and 9 of Configuration Register #2 to Logic "1" TESTMODE Digital Input 61 Factory test pin DO NOT CONNECT 45

46 Signal and Pin Descriptions Table 13 HI-620x3PCxF QFN and HI-620x3PQxF PQFP Package Pinouts Pin Signal Pin Signal Pin Signal Pin Signal 1 Logic_GND 21 D6 41 D14 61 TESTMODE 2 Logic_VDD 22 D7 42 D15 62 RTAD3 3 D0 23 D8 43 A14 63 RTAD4 4 D1 24 D9 44 A15 64 RSTBITEN 5 D2 25 TAG_CLK 45 MEM / REG 65 BENDI 6 D3 26 Logic_GND 46 STR / OE 66 TX_INH_B 7 Logic_GND 27 Logic_VDD 47 RAM_REG_VDD 67 TX_INH_A 8 Logic_VDD 28 A7 48 Logic_GND 68 TX/RX-A 9 MSTCLR 29 A8 49 A13 69 VDD_CHA 10 A0 30 A9 50 Logic_GND 70 TX/RX-A 11 A1 31 RTBOOT 51 Logic_VDD 71 TX/RX-B 12 A2 32 A11 52 CE 72 VDD_CHB 13 CLOCK_IN 33 A12 53 WAIT 73 TX/RX-B 14 A3 34 A6 54 INT 74 MSB / LSB 15 A4 35 D10 55 BTYPE 75 SSFLAG / EXT_TRIG 16 A5 36 D11 56 INCMD / MCRST 76 RTAD2 17 D4 37 D12 57 R/W / WE 77 RTAD1 18 D5 38 D13 58 BWID 78 RTAD0 19 Logic_GND 39 Logic_GND 59 WPOL 79 RTADP 20 Logic_VDD 40 Logic_VDD 60 RT_AD_LAT 80 A10 46

47 Host Interface 4 Host Interface The HI-6200 uses a parallel bus interface for communications with the host Host interface to registers and RAM is enabled through the Chip Enable (CE) pin, and accessed via 16-bit data bus and several host-originated control signals described below Timing is identical for register operations and RAM operations via the host bus interface, with the exception that RAM read operations are sped up by prefetching, which eliminates WAIT states during sequential RAM address reads (see below) The bus interface is compatible with the two prevalent host bus control signal methods: Intel style interface, characterized by separate strobes for read and write operations (OE and WE), and Motorola style interface, characterized by a single read/write strobe (STR) and a data direction signal (R/W) Bus control style is selected using the BTYPE configuration pin, which sets the function of two other input pins to serve as either OE and WE, or STR and R/W The BWID configuration pin selects either 8- or 16-bit bus widths When the BWID pin is connected to ground (logic 0 ), 8-bit mode is selected; two bytes are sequentially transferred for each 16-bit word operation and all transacted data uses bus data pins D7:0 (bus data pins D15:8 are not used) The BENDI and MSB / LSB pins are used in conjunction with each other to define the byte order When the BWID pin is connected high or left unconnected, 16-bit bus width is used and data is transacted on bus data pins D15:0 For 16-bit bus operation, the MSB/LSB pin is Don t Care and byte order is defined by the BENDI pin The interoperability of BWID, BENDI and MSB / LSB pins is outlined in detail in section Signal and Pin Descriptions, Table Bus Wait States and Data Prefetch for RAM Reads The HI-6200 has a WAIT output pin that tells the host to add wait states when additional access time is needed during bus read cycles For compatibility with different host processors, the state of the WPOL input pin sets the WAIT output as active high or active low The WAIT output can be ignored when the host processor read cycle time is always slow enough to work with the HI-6200 bus When using faster host processors, cycle time is sometimes slowed down by configuring the processor to add one or more wait states during every read or write cycle, but slow-down affects all cycles, even when unnecessary Data prefetch is a technique used by the HI-6200 to speed up host multi-word read access to RAM by eliminating wait states Prefetching occurs when HI-6200 logic requests data before it is actually needed Because RAM locations are often read sequentially, performance improves when data is prefetched in address sequence order For every host read cycle, the device first reads the addressed location, then prefetches the following address, to speed up access in the likely event that the following word will be read next For the HI-6200, WAIT is always asserted for the first word fetched in any RAM read sequence The first read cycle has a long access time because there is no prefetch This may be the first byte read in 8-bit mode, or the first word read in 16-bit mode After each word (or byte) is fetched for a read operation, the next word (or byte) is prefetched to speed-up the read cycle time when sequential address read sequences occur After the first word read, the following words read in sequence are accessed without WAIT, resulting in faster overall multi-word read timing As long as bytes or words are read in address order, additional wait states are unnecessary For fastest read access under all conditions, the user can set host processor bus timing (by adjusting processor wait states for the chip select assigned to the HI-6200) to match the faster read cycle time for prefetched data, while the HI-6200 WAIT output adds one or more additional wait states for the slower initial read cycle NOTE: Register reads don t use prefetch therefore will have a WAIT cycle during every address read Timing diagrams for host read and write operations are shown in the following pages Separate diagrams show Intel style and Motorola style control interfaces 47

48 Host Interface 42 Host RAM Read Operation Timing After the first byte is read, prefetch allows faster access times for successive reads, as long as read addresses are sequential WAIT is always asserted during the first read cycle and is never asserted for successive read cycles to sequential addresses This allows the default host bus configuration for the HI-6200 chip select to match the timing characteristics of the faster successive cycles, while the slower initial cycle is handled on a WAIT-controlled exception basis WAIT can be optionally inverted using the WPOL pin Host RAM read operations for 8-bit bus width (Figure 1) and 16-bit bus width (Figure 2) using Motorola style bus control (pin BTYPE =0) are shown below See for timing parameter values showing two successive 16-bit words (4 bytes) read from sequential addresses A15:1 ADDRESS ADDRESS + 1 A0 LB CS R / W STR twas t NSR t INACT t SR8 t INACT t SR8 t INACT t SR8 WAIT output t W t RA2 t RA2 t RA2 BYTE D7:0 High-Z High-Z BYTE High-Z BYTE High-Z BYTE t RA1 All timing intervals equal 0 ns MIN unless otherwise indicated Figure 1 Host Read for 8-bit bus width using Motorola style bus control (pin BTYPE = 0) 48

49 Host Interface showing a three word read access from sequential addresses A15:1 ADDRESS ADDRESS +1 ADDRESS +2 CS R / W tinact tsr16 tinact tsr16 STR twas t NSR WAIT output t W t RA2 t RA2 D15:0 WORD WORD High-Z High-Z High-Z WORD High-Z t RA1 All timing intervals equal 0 ns MIN unless otherwise indicated After first byte or word is read, prefetch allows faster access times for successive reads, as long as read addresses are sequential Figure 2 Host Read for 16-bit bus width using Motorola style bus control (pin BTYPE = 0) 49

50 Host Interface The following figures show host RAM read operations for 8-bit bus width (Figure 3) and 16-bit bus width (Figure 4) using Intel style bus control (pin BTYPE =1) showing two successive 16-bit words (4 bytes) read from sequential addresses A15:1 ADDRESS ADDRESS + 1 A0 LB CS WE OE twas t NSR t INACT t SR8 t INACT t SR8 t INACT t SR8 WAIT output t W t RA2 t RA2 t RA2 BYTE D7:0 High-Z High-Z BYTE High-Z BYTE High-Z BYTE t RA1 All timing intervals equal 0 ns MIN unless otherwise indicated Figure 3 Host Read for 8-bit bus width using Intel style bus control (pin BTYPE = 1) showing a three word read access from sequential addresses A15:1 ADDRESS ADDRESS +1 ADDRESS +2 CS WE tinact tsr16 tinact tsr16 OE t NSR twas WAIT output t W t RA2 t RA2 D15:0 WORD WORD High-Z High-Z High-Z WORD High-Z t RA1 All timing intervals equal 0 ns MIN unless otherwise indicated After first byte or word is read, prefetch allows faster access times for successive reads, as long as read addresses are sequential Figure 4 Host Read for 16-bit bus width using Intel style bus control (pin BTYPE = 1) 50

51 Host Interface 43 Host Register Read Operation Timing Host register read operations are identical to RAM read operations with the exception that there is no prefetching for sequential address reads and therefore every address read will have a WAIT cycle This is shown below in Figure 5 and Figure 6 for Motorola style and Intel style bus control respectively When using 8-bit bus width, all register reads behave in a similar fashion to their respective RAM reads, except all register read accesses have a WAIT cycle for each address that is read Showing two 16-bit words read from sequential or non-sequential Register addresses A15:1 REG ADDRESS REG ADDRESS CS R / W t INACT STR t WAS t NSR WAIT output t W D15:0 WORD High-Z High-Z WORD High-Z t RA1 t RA1 All timing intervals equal 0 ns MIN unless otherwise indicated Figure 5 Host sequential (or non-sequential) Register Read for 16-bit bus width using Motorola style bus control 51

52 Host Interface Showing two 16-bit words read from sequential or non-sequential Register addresses A15:1 REG ADDRESS REG ADDRESS CS WE t INACT OE t WAS t NSR WAIT output t W D15:0 WORD High-Z High-Z WORD High-Z t RA1 t RA1 All timing intervals equal 0 ns MIN unless otherwise indicated Figure 6 Host sequential (or non-sequential) Register Read for 16-bit bus width using Intel style bus control 52