Why Does Solid State Disk Lower CPI?

Transcription

1 Why Does Solid State Disk Lower CPI? Blaine Gaither, Jay Veazey, Paul Cao Revision: June 23, 2010 " 2010 Hewlett-Packard Development Company, L.P. The information contained herein is subject to change without notice

2 The Goal for this presentation is to explain the SSD Anomaly: On some high IO-rate CPU bound benchmarks Solid State Disks (SSDs) improve performance Order Entry 6% Brokerage Firm 3% These benchmarks have little idle time when run with magnetic storage. CPU Utilization 99% Magnetic Disk and SSD versions: Run the same OS and database Execute the same driver paths Execute the same instructions per IO How do faster disks help a workload that is CPU-bound? We explain how this can happen B. Gaither, October 6,

3 SSDs Influence On The Number Of Active Transactions Facts: Both benchmarks have a large number of processes in flight SSD Reduces the IO wait time thus improving response time Transactions stay resident in the system for shorter periods. Little s Law 1 N = λ * R Number of Items in the system = throughput * response time As the response time is reduced The number of active transactions (processes or threads) in the system is reduced 1 Little, J. D. C. A Proof of the Queueing Formula L = λ W Operations Research, 9, (1961). B. Gaither, October 6,

4 Reduced Process Count Impacts: Reduces number of processes sharing fixed resources Cache, TLB More cache per remaining processes (or threads) Fewer capacity faults Fewer conflict evictions The effect is: As if the cache were larger More cache/ process Lowers Miss Rate Lowers CPI Shorter IO waits = Shorter time during which get lines stolen Long term impacts Small cache SKUs may be more viable for $/performance Lock contention is reduced: Fewer contending threads Holding locks less time Software structures (lists queues) get smaller I will concentrate here on cache effects B. Gaither, October 6,

5 Transforming Miss-rate to Residency-time Use Little s law Number of transaction in a system = Throughput * Responsetime N = λ R Think of a cache as a box: Every cache miss places a new line in the box. (λ = Cache miss rate) The cache box holds a finite number of lines (N) The time the average line spends in the box is (R) Thus, for caches, Residency-time = Number of lines in the cache / (cache misses rate) Little s Law also teaches Doubling the cache size at least doubles the cache residency time It s the Law! B. Gaither, October 6,

6 An Extended Residency Time Model We model the behavior of the average set in a setassociative cache. Arrivals are assumed to be : Distributed uniformly across the cache sets True for most OLTP workloads IID Arrivals to each set see an N-way fully associative cache One associativity per way of a N-way set-associative cache It takes N misses to the set to age a line out of the cache set In the following slides we model the typical set with an Erlang distribution with a shape of N. Real distribution may be somewhat more Platykurtic (Flat) B. Gaither, October 6,

7 Nehalem-EP Cache Residency Estimated distribution of time that an avg. line resides in the cache OLTP Estimated % of working set stolen over the period a software thread is stalled. Little working set left in cache 80% of working set still in cache B. Gaither, October 6,

8 SSDs Improve Instruction Execution Rate OLTP SSD latency Magnetic Disk latency Lower latency disk means more workingset remains in cache. Thus reduced cache Miss rate Improved miss rate: Lowers memory wait Lowers CPI Improves Instruction execution speed Improves throughput B. Gaither, October 6,

9 Brokerage Firm Observations DL380 G6 2x Intel X5570, 96GB, SAS Quantity Description Processor 2/8/16 Intel Xeon 2.93 GHz X5570 Memory 96 GB 12x8 GB Disk controller 1 4 HP P411 SA Disk controller 2 1 HP P410i SA Data drives GB 15k SFF SAS Log drives GB 15k SFF SAS Data enclosure 1 16 MSA70 Log enclosure 1 Internal bay DL380 G6 2x Intel X5570, 96GB, SSD Quantity Description Processor 2/8/16 Intel Xeon 2.93 GHz X5570 Memory 96 GB 12x8 GB Disk controller 1 4 HP P411 SA Disk controller 2 1 HP P410i SA Data drives 64 60GB SSD Log drives GB 15k SFF SAS Data enclosure 1 8 MSA70 Log enclosure 1 Internal bay SSD Delivered a 3% throughput improvement 4.7 % reduction in CPI Due to improved cache miss rate 32% reduction in lowest level cache miss rate Result of combination of fewer active threads, and Improved disk latency interaction with cache residency time Impact of cache effects clearly shown Improved throughput coupled with lower CPU utilization Further improvement in throughput possible With better tuning to increase the CPU utilization B. Gaither, October 6,

10 Order Entry Observations SSD Delivered a 6.2% throughput improvement 4.7 % reduction in CPI Due to improved cache miss rate 9% reduction in cache miss rate Result of combination of fewer active threads, and Improved disk latency interaction with cache residency time 3.1% reduction in instruction path length Probably due to fewer active threads 5% Lower CPU Utilization Combination of lower CPI and reduced instruction path length. Further throughput improvements might be possible with more tuning. B. Gaither, October 6,

11 Implications For IO Intensive Workloads Fast Storage Can: Improve Cache Hit Rate Reduce Instruction Path Length Cache Analysis Techniques are applicable to other periodic activity: Do the data structures for loop X fit in the cache? How long does an iteration take compared to cache residency time? How many guests can share an LLC How big a cache is needed to contain a loop in a technical, or realtime application. If a loop iteration takes too long, Little s Law tells you how much bigger the cache needs to be How long does it take a workload to Warm-up the cache. Can apply to buffer caches or any level or type of storage B. Gaither, October 6,

12 Backup B. Gaither, October 6,

13 SSD Latency Behavior Most SSDs at the time of writing are based upon NAND flash technology Flash component read speed is up to 25us Flash is non-volatile Unlike dynamic RAM Remembers even if power is lost. Collects errors from Cosmic rays Just like DRAM But it collects errors when it is unpowered too. Drives compensate with sophisticated error correction coding B. Gaither, October 6,

14 Observed SSD Latency Anomaly While preparing for a benchmark, engineers observed strange latency behavior Very long latencies once in a while. Following data from a disk stress workload. Some IOs have 85ms latency? What causes these disk sabbaticals? Observations on a Windows system with XPERF B. Gaither, October 6,

15 FLASH Wear-out Flash is subject to wear out Can only write to a flash location a limited number of times Before it is worn out and doesn t remember. This is different than magnetic disk. Drives compensate with Wear leveling Provide excess capacity to replace worn out blocks Virtualizes the logical block address on the physical medium This takes some sophisticates firmware House keeping has to run sometime. We work with disk vendors to minimize these effects. B. Gaither, October 6,

16 1 Little, J. D. C. A Proof of the Queueing Formula L = λ W Operations Research, 9, (1961). B. Gaither, October 6,