DELL NFV Summit. Making Network Function Virtualization (NFV) a Reality. Rajesh Gadiyar, Director of Architecture, Network Platforms Group

Transcription

1 DELL NFV Summit Making Network Function Virtualization (NFV) a Reality. Rajesh Gadiyar, Director of Architecture, Network Platforms Group

2 Legal Disclaimer INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. A "Mission Critical Application" is any application in which failure of the Intel Product could result, directly or indirectly, in personal injury or death. SHOULD YOU PURCHASE OR USE INTEL'S PRODUCTS FOR ANY SUCH MISSION CRITICAL APPLICATION, YOU SHALL INDEMNIFY AND HOLD INTEL AND ITS SUBSIDIARIES, SUBCONTRACTORS AND AFFILIATES, AND THE DIRECTORS, OFFICERS, AND EMPLOYEES OF EACH, HARMLESS AGAINST ALL CLAIMS COSTS, DAMAGES, AND EXPENSES AND REASONABLE ATTORNEYS' FEES ARISING OUT OF, DIRECTLY OR INDIRECTLY, ANY CLAIM OF PRODUCT LIABILITY, PERSONAL INJURY, OR DEATH ARISING IN ANY WAY OUT OF SUCH MISSION CRITICAL APPLICATION, WHETHER OR NOT INTEL OR ITS SUBCONTRACTOR WAS NEGLIGENT IN THE DESIGN, MANUFACTURE, OR WARNING OF THE INTEL PRODUCT OR ANY OF ITS PARTS. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined". Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The information here is subject to change without notice. Do not finalize a design with this information. The products described in this document may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an order number and are referenced in this document, or other Intel literature, may be obtained by calling , or go to: Intel processor numbers are not a measure of performance. Processor numbers differentiate features within each processor family, not across different processor families: Go to: Learn About Intel Processor Numbers Intel, the Intel logo, Itanium, Intel Atom, Intel Xeon Phi, Intel AppUp, and Xeon are trademarks of Intel Corporation in the U.S. and/or other countries. *Other names and brands may be claimed as the property of others. Copyright 2015 Intel Corporation. All rights reserved

3 INTEL Strategy OVERVIEW

4 4:1 Network Workload Consolidation on IA Application Processing Control Plane Processing Packet Processing Signal Processing Firewall, OpenSSL, Call Processing Stack, BSS/OSS BGP, OSPF, RIP, SCTP, SIP, MGCP, PDCP, RLC/RRC Classification, Traffic Management, QoS Scheduling, Network Overlays, DPI, IPSEC Video Transcoding, Baseband Processing, Speech Codecs BGP Routing QoS Scheduling Video Transcode Network Platforms Group 4

5 SDN + NFV Driving Architectural Transformation From This, Today Traditional networking topology Monolithic vertical integrated box TEM proprietary solutions To This, the Vision Networking within VMs Standard x86 server hardware Open SDN standard solutions ADC* Network Security Router ADC VM Network Security VM Router SDN + NFV > _ Hypervisor (e.g. ESXi, KVM, Hyper-V, etc.) TEM/OEM Proprietary OS ASIC, DSP, FPGA, ASSP Processor NIC Silicon Acceleration Switch Silicon Open Software TPM 5

6 Enable the Transformation with Intel ONP Reference architecture Industry Consortia Advance Open Source and Standards Intel ONP Deliver Open Reference Designs Enable Open Ecosystem on IA Intel Network Builders Intel Network Builders Collaborate on Trials and Deployments Telecom Cloud Enterprise 6

7 KEY PILLARS for ACCELERATING NFV High Volume Server based NFV deployments Best-In-Class Performance/Watt/$$ Open Architecture allows large choice of VNFs Service Assurance Security

8 Tick-Tock Development Model: Sustained Processor Leadership Intel Microarchitecture code name Nehalem Intel Microarchitecture code name Sandy Bridge Intel Microarchitecture code name Haswell Intel Microarchitecture Next Generation Nehalem Westmere Sandy Bridge Ivy Bridge Haswell Broadwell Future Future 45nm 32nm 32nm 22nm 22nm 14nm 14nm 10nm New Microarchitecture New Process Technology New Microarchitecture New Process Technology New Microarchitecture New Process Technology New Microarchitecture New Process Technology TOCK TICK TOCK TICK TOCK TICK All products, computer systems, dates and figures specified are preliminary based on current expectations, and are subject to change without notice. TOCK TICK

9 KEY CONSIDERATIONS for NFV Infrastructure (NFVi] Data Plane on IA

10 Network Functions Virtualization (NFV) Today Telcos deliver a network service by chaining network functions (NF) residing on physical appliances. With NFV, the Telcos will utilize an ordered set of cooperating Virtual Network Functions (VNFs) known as Service Function Chain (SFC) Network Functions Switch Router VPN Firewall Load Balancer Virtual Switch Hypervisor Virtual Switch Hypervisor Physical Hardware Physical Hardware Current Model Services in dedicated hardware or physical boxes that are Network Topology dependent Inflexible deployment model, requires changing forwarding behavior NFV Model NFV is about dynamic provisioning of network services as Virtual Network Functions (VNF) on high volume servers as virtual machines 10

11 NFV on an Intel Platform Network elements are typically designed for peak performance with guaranteed throughput and (low) latency Key platform ingredients are required to support deterministic performance, latency and jitter Packet Processing HW and SW Virtualization Hardware Assists Platform Quality of Service Security & Attestation (DPDK, OVS with DPDK Netdev, Hyperscan, Intel Quick Assist) (Posted Interrupts, VMFUNC, Extended Page Tables, vapic) (Cache Monitoring / Allocation, Memory Bandwidth Monitoring) (Platform Security, Network Security, Encrypted Storage, Trust & Attestation) Data Plane Development Kit (DPDK)

12 Data PLANE Technologies

13 Data Plane Development Kit - Fully Open Source Community Intel Contributions Latest version of DPDK Community patches Community mailing lists and support Fellow Traveler Contributions Open-Source Community Patches and Support Call To Action: Register Yourself Value Proposition - Optimized Linux * User Space Library focused on data plane implementation on general purpose processors - Multi-architecture: x86, IBM Power, TileGX - Multi-NIC support - Easy to use examples to demonstrate usage and performance - User friendly license (majority BSD) - Scales from high end multi-processor systems to low end SoCs New Capabilities with DPDK - DPDK performance in guest and host Virtualization provides Consolidation of appliances and services in NFV environments and SDN architectures High performance virtual switching (e.g. OVS) solutions to build on Data centers and Converged Networks, Intel Rack Scale Architectures

14 Virtualization on Intel Architecture Platforms Rich set of virtualization hardware assists including: Extended Page Tables Virtual Processor ID Descriptor Table Exiting VMX Preemption Timer Pause Loop Exiting Address Translation Services Interrupt Remapping Queued Invalidations Large Page Support (Intel Virtualization Technology for Directed I/O) Recent Additions: EPT Accessed & Dirty Bits APIC Virtualization Posted Interrupts VMM Function Calls (VMFUNC) Software Optimizations to limit FPU based exits 14 TRANSFORMING NETWORKING COMMUNICATIONS & STORAGE & STORAGE 14

15 Software Defined Infrastructure Platform QoS Cache QoS Memory QoS I/O & Device QoS Cache Monitoring Tech (CMT) Per-thread L3 Occupancy Monitoring 4 Resource Monitoring ID s per logical thread Memory BW Monitoring (MBM) Per-thread Memory Bandwidth Monitoring Leverages RMID infrastructure HP LP? IMC Cache Allocation Tech (CAT) Per-thread L3 Occupancy Control Intel Xeon D introduces 16 Classes of Service Cache HP LP Key Technologies for Improved Visibility and Performance Determinism TRANSFORMING NETWORKING COMMUNICATIONS & STORAGE & STORAGE

16 Expanding DPDK API to address hardware acceleration Pktgen Traffic generator Example Applications Future features Event system Light weight threads Storage and file systems Network Stacks DPDK API EAL METER ETHDEV LPM Crypto Device DPI Device Classification Device Compression Device Future Device MALLOC MBUF SCHED QoS e1000 ixgbe af_pkt i40e Classification ACL AES-NI Hyperscan RRC QAT NBT MEMPOOL RING TIMER CMDLINE KVARGS Core Libraries KNI POWER IVSHME M JOBSTAT Platform bonding vmxnet3 xenvirt enic mlx4 Focus to Date others fm10k virtio ring cxgbe memnic Packet Access (PMD) TABLE Classify PIPELINE HASH IP Frag REORDE R Utilities external memory manager SoCs* SoC PMD Simple SOC model DPDK Architecture QAT 3 rd Party 3 rd Party 3 rd Party DPDK-AE (Acceleration Enhancements) 3 rd Party DPDK - A Programmable, High Performance Industry Standard Data Plane API

17 DPDK Continues to Deliver HIGH Performance IPV4 L3 Forwarding Performance for 64B System Configuration 37 Gbps 62.5 Gbps Gbps Gbps Gbps Limited by PCIe slots. Can scale higher Hardware Platform Wildcat Pass Beta CPU E v3 Chipset Wellsburg B0 Sockets 2 Cores per Socket 12 (24 threads) LL CACHE 30 MB QPI/DMI 9.6GT/s PCIe (4 NICs) Gen3x8 Socket 1 3 NICs socket 0 MEMORY Micron DDR MHz 1R ECC, 1DPC, 8GB/DIMM, 8DIMMs total NIC X520-4 NIC Mbps 10,000 BIOS SE5C610.86B Intel Confi dentia Disclaimer: Software and workloads used in performance tests may have been optimized for performance only on Intel microprocessors. Performance tests, such as SYSmark and MobileMark, are measured using specific computer systems, components, software, operations and functions. Any change to any of those factors may cause the results to vary. You should consult other information and performance tests to assist you in fully evaluating your contemplated purchases, including the performance of that product when combined with other products. E (2.1GHz, 8C/16T) DP; PCH: Patsburg; LLC: 20MB; 16 x 10GbE Gen2 x8; 4 memory channels per 1600MT/s, 8 memory channels total; DPDK l E5-2658v2 (2.4GHz, 10C/20T) DP; PCH: Patsburg; LLC: 20MB; 22 x 10GbE Gen2 x8; 4 memory channels per 1867MT/s, 8 memory channels total; DPDK *Projection data on 2 sockets extrapolated from 1S run on Wildcat Pass system with E v3. Software OS Kernel version Other Socket 0: 12x 10GbE using 6C (139.5 Mpps) Socket 1: 14x 10GbE using 7C (162.6 Mpps) Ubuntu LTS 64 bit generic DPDK1.7.0 All HW Prefetchers are enabled 17

18 Open vswitch Performance Focus Optimize Flow cache matching with Data Plane Development Kit (DPDK) functions VM DPDK shmem qemu VM virtio qemu Target Bottlenecks in Guest virtio implementation ovs-switchd ovs-switchd User Space Forwarding Tunnels netdev IVSHEM DPDK netdev vhost DPDK Libraries Target Bottlenecks in vhost implementation TAP socket PMD Improve tunnel header processing using DPDK routines NIC Enable vectorization in the physical port PMD Systematically Addressing the Bottlenecks 18

19 10 Gbps 10 Gbps 5 Gbps 5 Gbps 5 Gbps 5 Gbps Open Vswitch (DPDK Netdev) Performance VNF 1 VNF 2 VNF 3 VNF 4 DPDK vswitch NIC 40 Gbps Switching (<2 CPU Cores) Open Vswitch w/ DPDK Netdev delivers Scalable, High Perf switching 19

20 Service Orchestration

21 INTEL s approach to NFV MANO OSS/BSS NFV Orchestrator (NFVO) Ensure Scalability Create Well- Defined, Open Interfaces Expose & Leverage Enhanced Platform Capabilities EMS EMS VNF VNF VNF Service, VNF & Infrastructure Descriptors NS Catalog VNF Catalog NFV Instances VNF Manager VNF Manager (VNFM) (VNFM) VNF Manager (VNFM) NFVI Resources Virtual Compute Compute HW NFVI Virtual Storage Virtualization Layer Storage HW Virtual Network Network HW Virtualized Infrastructure Manager (VIM) NFV-MANO 21

22 Why the need for Platform Awareness? Intel Confidential TRANSFORMING NETWORKING & STORAGE 22

23 Enhanced Platform Awareness Features Non-Uniform Memory Architecture (NUMA) CPU & Memory configuration (co-located memory and socket) NUMA I/O Device Locality configuration (co-located PCI device and socket) CPU Pinning Huge Page Support (2MB/1GB) I/O Pass-through (Full PCIe pass-through of the I/O device to the guest) I/O Pass-through (Virtual Function (SR-IOV) pass-through of the I/O device to the guest) QAT TXT HW offload API for RRC (Ruby Rapids) AES-NI, AVX, SSE4.2, RD RAND (Instruction Set Extensions) CPU Model (explicit model match) CPU llc (cache size) vswitches (type, capability) - OVS specified, with or without either DPDK/HWOA LLC utilization CPU ddio (direct i/o) CAT (cache allocation) Enhanced Platform Awareness (EPA) leading to improved SLA 23

24 Use Case Traction Consumer VoLTE, WiFi Calling, RCS vims, vtas Charging, Policy, etc. PCRF, DPI Business Network on Demand Virtual Managed Services SD-WAN, SD- Transport, SD-VPN, DC-DC ve-cpe Wholesale IoT, MVNO Services vepc Intel Confidential 24

25 Summary Intel has a compelling Platform Roadmap. Significant investment and focus on Network Transformation with SDN/NFV Improving Data Plane Performance for a best-in-class NFVi is a significant area of focus over the next few years Intel Network Builders building an ecosystem of VNF vendors and solutions ready for commercial deployments

26 Thank you 26

27 Requirements for NFV Data Plane Programmability Scalability Efficiency High Performance Security SW Programmable & Flexible Control Plane & Policy Controls Scales across multi-core CPU options Generational Scalability Best-In-Class Perf/Watt/$$ Seamless integration of platform accelerators 40G/100G/nx100G line rate over time Real time latency & jitter characteristics Data Security encompassing Platform Security, Network Security, Storage Security, Trust & Attestation

28 NFV Security Web Service Security Services Cloud Instance More data through the cloud More workloads per server Security & network functions as services