The Dual Round Robin Matching Switch with Exhaustive Service

Transcription

1 The Dual Round Robin Matching Switch with Exhaustive Sevice Yihan Li, Shivenda S. Panwa, H. Jonathan Chao Abstact Vitual Output Queuing is widely used by fixed-length highspeed switches to ovecome head-of-line blocking. This is done by means of matching algoithms. Maximum matching algoithms have good pefomance, but thei implementation complexity is quite high. Maximal matching algoithms need speedup to guaantee good pefomance. Iteative algoithms (such as PIM and islip) use multiple iteations to convege on a maximal match. The Dual Round-Robin Matching (DRRM) scheme has pefomance simila to islip and lowe implementation complexity. The objective of matching algoithms is to educe the matching ovehead fo each time slot. In this pape we pesent the Exhaustive Sevice Dual Round-Robin Matching (EDRRM) algoithm, which amotizes the cost of a match ove multiple time slots. While EDRRM suffes fom a thoughput below 00% fo small switch sizes, it is conjectued to achieve an asymptotic 00% thoughput unde unifom taffic. Simulations show that it achieves high thoughput unde nonunifom taffic. Its delay pefomance is not sensitive to taffic bustiness, switch size and packet length. In an EDRRM switch cells belonging to the same packet ae tansfeed to the output continuously, which leads to good packet delay pefomance and simplifies the implementation of packet eassembly. Keywods switching, scheduling, Vitual Output Queueing, Dual Round Robin, polling. I. ITRODUCTIO FIXED-LEGTH switching technology is widely accepted as an appoach to achieve high switching efficiency fo high speed packet switches. Vaiable-length IP packets ae segmented into fixed-length cells at inputs and ae eassembled at the outputs. Packet switches based on Input Queuing (IQ) ae desiable fo high speed switching, since the intenal opeation speed is only slightly highe than the input line. Howeve, an Input Queuing switch has a citical dawback [], []: the thoughput is limited to 58:6% due to the head-of-line (HOL) blocking phenomena. Output Queuing (OQ) switches have the optimal delaythoughput pefomance fo all taffic distibutions, but the - times speed-up in the fabic limits the scalability of this achitectue. Vitual Output Queuing (VOQ) is used to ovecome the dawbacks and combine the advantages of an Input Queuing switch and an Output Queuing switch. In a VOQ switch, each input maintains queues, one fo each output. By using VOQ, no additional speedup is equied and HOL blocking can be eliminated. Yihan Li is a Ph.D. candidate in the Electical and Compute Engineeing Depatment, Polytechnic Univesity, Booklyn, Y, USA. yli@photon.poly.edu. Shivenda S. Panwa and H. Jonathan Chao ae on the faculty of the Electical and Compute Engineeing Depatment, Polytechnic Univesity, Booklyn, Y, USA. panwa@catt.poly.edu, chao@antioch.poly.edu. This wok is suppoted in pat by the ew Yok State Cente fo Advanced Technology in Telecommunications (CATT), and also in pat by the ational Science Foundation unde gants ITR00857 and ITR Addess: Electical and Compute Engineeing Depatment, Polytechnic Univesity, Six MetoTech Cente, Booklyn, Y, 0-80, USA. Fax: Consideable wok has been done on scheduling algoithms fo VOQ switches. It has been poved that by using a maximum weight matching algoithm 00% thoughput can be eached fo i.i.d. aivals (unifom o nonunifom) [] [] [5]. But maximum match is not pactical to implement in hadwae due to its complexity, and may not guaantee fainess and quality of sevice. A numbe of pactical maximal matching algoithms have been poposed [6] [7] [8], but maximal matching algoithm cannot achieve as high a thoughput as maximum matching algoithms. Iteative algoithms such as PIM [9] and islip [0] [5], use multiple iteations to convege on a maximal matching. The Dual Round-Robin Matching (DRRM) switch [] [] builds and impoves on the ideas incopoated in islip. It has been poven that DRRM can achieve 00% thoughput unde i.i.d. and unifom taffic []. Futhemoe, the DRRM scheme povides fainess and pevents stavation. It has lowe implementation complexity compaed to algoithms with simila pefomance and is scalable. Accoding to simulation esults [], unde unifom busty taffic, the aveage delay of a DRRM switch vaies appoximately linealy with bust length, but unde nonunifom taffic the thoughput dops below 00%. In this pape a vaiation of DRRM, Exhaustive sevice DRRM (EDRRM) is pesented to impove switching pefomance unde busty and nonunifom taffic. The implementation of EDRRM and DRRM ae compaable with both having lowe complexity than islip. The only pefomance dawback of EDRRM is that it does not achieve 00% thoughput unde unifom taffic fo a ange of switch sizes. We conjectue that fo an EDRRM switch of lage size, thoughputs appoaching 00% ae achievable unde unifom taffic. Simulation esults pesented in this pape and analysis esults in [] suppot, though not igoously pove, this conjectue. Fo smalle switch sizes, we demonstate this popety though simulations. Compaed to DRRM and is- LIP, EDRRM has highe thoughput unde nonunifom taffic. The delay of EDRRM is less sensitive to taffic bustiness, and inceases much slowe with switch size. EDRRM is neithe a maximum matching no a maximal matching algoithm. Unlike any maximum o maximal matching algoithm, which ty to find as many matches as possible in each time slot, EDRRM achieves efficiency by looking at the matching ovehead ove time. In EDRRM the cost in wasted slot times to get a match may be lage, but the cost is amotized ove a VOQ busy peiod. We believe that this is a new appoach with both theoetical and pactical implications. Most of the pevious wok only consides the cell delay that a cell suffes fom the time it entes a VOQ to the time it is tansfeed to the destination output pot. Additional delay is incued at the Output Reassembly Module (ORM) of each output to eassemble packets []. Multiple queues ae needed at each ORM if cells belonging to diffeent packets ae inteleaved at the

2 same output. When a cell it tansfeed though the switch fabic to the output, it is deliveed into one of the queues of the ORM. The cells belonging to the same packet will be deliveed to the same queue and can only leave the queue until the whole packet is eassembled. The total delay a packet suffes includes the cell delay and the time needed fo eassembly. Thus the cell delay is not enough to evaluate the delay pefomance of a packet switch. In this pape we measue the packet delay as well as the cell delay of EDRRM and compae them to those of DRRM and islip. It shows that unde unifom i.i.d. taffic, even when the cell delay of EDRRM is highe, the packet delay is lowe, and it is not sensitive to switch size and packet length. At the same time, since all the cells belonging to the same packet ae tansfeed to the output continuously, only one queue is needed in each ORM, which futhe simplifies the switch implementation. In section II we biefly oveview the DRRM algoithm and its pefomance. In section III the EDRRM algoithm is descibed in detail. In section IV the thoughput, aveage cell delay and aveage packet delay pefomance of an EDRRM switch is discussed. II. THE DRRM ALGORITHM AD ITS PERFORMACE In the DRRM scheme each input pot maintains VOQs. The algoithm has two steps: Step : Request. Each input sends an output equest coesponding to the fist nonempty VOQ in a fixed ound-obin ode, stating fom the cuent position of the pointe. The pointe emains at that nonempty VOQ if the selected output is not ganted in step. The pointe of the input abite is incemented by one location beyond the selected output if, and only if, the equest is ganted in step. Step : Gant. If an output eceives one o moe equests, it chooses the one that appeas next in a fixed ound-obin schedule stating fom the cuent position of the pointe. The output notifies each equesting input whethe o not its equest was ganted. The pointe of the output abite is incemented to one location beyond the ganted input. If thee ae no equests, the pointe emains whee it is. The pefomance of the DRRM scheme has been shown and compaed with that of islip in []. Unde unifom and i.i.d. taffic the thoughput of a DRRM switch is 00%, and the aveage cell delay inceases with switch size fo a given. The pefomance unde nonunifom taffic is also consideed in []. Simulation esults show that unde the hot-spot taffic, thoughput fo the hot-spot output of a DRRM switch is 00%. Fo anothe nonunifom taffic scenaio simulations show that the thoughput of both DRRM and islip dops below 00%. III. THE EXHAUSTIVE SERVICE DRRM SCHEME In the DRRM scheme, when an input and an output ae matched, only one cell will be tansfeed fom the input to the matched output. Afte that both the input and the output will incement thei pointes by one and in the next time slot this input-output pai will have the lowest pioity to get matched to each othe. This behavio is simila to the limited sevice policy [5] in a polling system. In ode to impove on DRRM s pefomance unde non-unifom taffic, we modified the DRRM scheme so that wheneve an input is matched to an output, all the cells in the coesponding VOQ will be tansfeed in the following time slots befoe any othe VOQ of the same input can be seved. This is called the exhaustive sevice policy [5] in polling systems. We theefoe call this the Exhaustive sevice DRRM (EDRRM) scheme. In EDRRM, the pointes of inputs and outputs ae updated in a diffeent way fom DRRM. In a time slot if an input is matched to an output, one cell in the coesponding VOQ will be tansfeed. Afte that, if the VOQ becomes empty, the input will update its abite pointe to the next location in a fixed ode; othewise, the pointe will emain at the cuent VOQ so that a equest will be sent to the same output in the next time slot. If an input sends a equest to an output but gets no gant, the input will update its abite pointe to the next location in a fixed ode, which is diffeent fom DRRM whee the input pointe will emain whee it is until it gets a gant. The eason fo this modification is as follows. In EDRRM if an input cannot get a gant fom an output, it means that the output is most likely in a stable maiage with anothe input fo all the cells waiting in the VOQ, and the unsuccessful input is likely to wait fo a long time to get a gant fom this output. It will be bette fo the input to seach fo anothe fee output than to wait fo this busy one. Since an output has no idea if the cuently seved VOQ will become empty afte this sevice, outputs will not update thei abite pointes afte cell tansfe. A detailed desciption of the two step EDRRM algoithm follows: Step : Request. Each input moves its pointe to the fist nonempty VOQ in a fixed ound-obin ode, stating fom the cuent position of the pointe, and sends a equest to the output coesponding to the VOQ. The pointe of the input abite is incemented by one location beyond the selected output if the equest is not ganted in Step, o if the equest is ganted and afte one cell is seved this VOQ becomes empty. Othewise, the pointe emains at that (nonempty) VOQ. Step : Gant. If an output eceives one o moe equests, it chooses the one that appeas next in a fixed ound-obin schedule stating fom the cuent position of the pointe. The output notifies each equesting input whethe o not its equest was ganted. The pointe of the output abite emains at the ganted input. If thee ae no equests, the pointe emains whee it is. Input Input Input Input Input Abites Request Phase Gant Phase g equest Fig.. An example of EDRRM gant g Output Abites Figue shows an example of the EDRRM abitation algoithm.,, and ae abite pointes fo inputs,, and g g

3 , and g, g, g and g ae abite pointes fo outputs,, and. At the beginning of the time slot points to output while g does not point to input, which means that in the last time slot input was not matched to output, and now input equests output fo a new sevice. Similaly, equests output fo a new sevice. Since points to output and g points to input, it is possible that in the last time slot input was matched to output and in this time slot output will continue to tansfe a cell fom input because the VOQ is not empty. Input and output have a simila situation with input and output. In the gant phase, output gants the only equest it eceives fom input and updates g to, output gants the equest fom input and output gants the equest fom input. The equest fom input to output is not ganted, so moves to. By the end of this time slot, the st VOQ of input and the d VOQ of input ae still nonempty so that and ae not updated; is updated to because the nd VOQ of input becomes empty. The implementation complexity of EDRRM s switching fabic is identical to that of DRRM. Since the opeational step and data exchange is limited, the DRRM abitation mechanism can be implemented in a distibuted manne to make the switch simple and moe scalable. The length of each contol message in DRRM is only th of that in islip. In [] it is shown that by using a token-tunneling technique a switch capacity of moe than one teabit/sec is achievable with existing electonic technology. The ORM of EDRRM is simple than that of DRRM since only one queue is maintained. Usually when cells of diffeent packets ae inteleaved, queues ae needed in each ORM, one fo each input. In the next section, we will show that EDRRM has pefomance compaable with DRRM and islip unde unifom independent taffic, and has bette pefomance unde busty taffic and nonunifom taffic. IV. SIMULATED PERFORMACE OF EDRRM In this section the thoughput and delay pefomance of EDRRM is shown by simulation esults and compaed with that of DRRM. A. Thoughput DRRM is poved to have 00% thoughput unde unifom and i.i.d. taffic in []. Accoding to simulation esults the thoughput of EDRRM unde unifom and i.i.d. taffic is close to, but not quite 00%. Figue shows the thoughput of EDRRM with diffeent switch size unde unifom and i.i.d. taffic with 00% aival ate. ote that the thoughput fist deceased and then inceases with switch size. We conjectue that fo lage the thoughput will appoach 00% asymptotically. This conjectue is futhe suppoted by the analysis in []. Long simulation un lengths pevented us fom consideing switch sizes lage than. While this is cetainly a weakness of EDRRM as compaed to DRRM and islip, we believe that this is an acceptable tadeoff given its pefomance advantages unde moe typical taffic ings. We will conside these next. In this pape we conside fou nonunifom taffic pattens and compae the thoughput of EDRRM to those of DRRM and is- LIP. thoughput % conf. int switch size Fig.. The thoughput of EDRRM switch unde unifom taffic Patten : Hot-spot taffic, which efes to a taffic patten whee many inputs send taffic to one output line (the hot-spot) at the same time, thus oveing it. The hot-spot thoughput of EDRRM is 00%, which is the same as that of DRRM and highe than that of islip. Patten : In this patten the aival ate fo each input is the same, while the ing fo each output is also the same. Fo input i a faction p,» p<of aivals ae destined to output i, and othe aivals ae unifomly destined to othe outputs. When p =, this coesponds to the unifom case. When p =, all the aiving cells of input i ae destined to output i. Figue compaes the thoughput of EDRRM, DRRM and is- LIP unde this taffic patten fo diffeent switch sizes. It shows that EDRRM has highe thoughput than DRRM. The figue also shows that fo EDRRM switch, the thoughput unde unifom aivals (when p = ) is compaable to the thoughput unde nonunifom aivals (when p> ). In a DRRM switch each VOQ gets unifom sevice. On the othe hand, in an EDRRM switch all the cells in a VOQ will be seved when the VOQ wins the sevice no matte what the aival ate is fo this VOQ. When the system is stable, the sevice ate fo a VOQ is close to the aival ate, which leads to a high thoughput. ote that anothe attactive featue of EDRRM is that it automatically adapts to changes in taffic flow though the switch, i.e., no paamete has to be set to optimize pefomance fo a given non-unifom taffic flow. This is impotant since it simplifies switch taffic management as taffic flows change with time. Also note that, as in Figue, the oveall thoughput fist dops with switch size and then inceases with. We see that with inceasing switch size, the EDRRM switch can maintain close to 00% thoughput fo this nonunifom taffic patten. Patten : In this patten the aival ate fo each input is the same. Fo input i a faction f of aivals ae destined to output i, and othe aivals ae destined to output (i +)mod. Table I compaes the thoughput of EDRRM, DRRM and islip unde this taffic patten fo diffeent f with switch size. EDRRM has a highe thoughput than DRRM o islip. Patten : In this patten the aival ate fo each input is the

4 TABLE I THE THROUGHPUT UDER OUIFORM TRAFFIC PATTER f EDRRM DRRM islip TABLE II THE THROUGHPUT UDER OUIFORM TRAFFIC PATTER size 8 6 EDRRM DRRM islip same. Fom input i the taffic to output i + j is two times the to output i + j +, 0» j». Table II compaes the thoughput of EDRRM, DRRM and islip unde this taffic patten fo diffeent switch sizes. The thoughput of EDRRM is always above 90%, which is much highe than the thoughputs of DRRM and islip. Though not pesented hee, a limit on the maximum numbe of cells that can be seved continuously in a VOQ can be enfoced by means of a counte to avoid unfainess in case one output is occupied fo long peiods of time by one input unde some exteme taffic patten EDRRM x EDRRM 8x8 EDRRM 6x6 EDRRM x DRRM x DRRM 8x8 DRRM 6x6 DRRM x islip x islip 8x8 islip 6x6 islip x aveage cell delay of an EDRRM switch unde unifom taffic and a heavy is lage than that of a DRRM switch. This is due to the moe efficient DRRM scheduling mechanism unde unifom, heavy taffic. mean cell delay (time slots) EDRRM x EDRRM 8x8 EDRRM 6x6 DRRM x DRRM 8x8 DRRM 6x Fig.. The aveage cell delay unde unifom taffic fo diffeent switch sizes Figue 5 shows the aveage cell delay of an EDRRM switch, a DRRM switch and an islip switch with switch size 6 6 unde unifom busty taffic with a geometically distibuted bust length of 6 cells. It shows that the aveage delays of DRRM and islip ae simila to each othe and much lage than the aveage delay of EDRRM unde heavy. Since the pefomance of islip and DRRM ae oughly compaable [], we will compae the pefomance of EDRRM with DRRM fom this point onwad EDRRM DRRM islip thoughput nonunifom paamete p Fig.. The thoughput fo diffeent switch sizes unde nonunifom taffic patten B. Aveage cell delay Figue shows the aveage cell delay of EDRRM and DRRM unde unifom and i.i.d. taffic with diffeent switch sizes. The Fig. 5. The aveage cell delay of a 6x6 switch unde unifom busty taffic with bust length = 6 cells Figue 6 compaes the aveage cell delay of an EDRRM switch and a DRRM switch with switch size 6 6 unde unifom and busty taffic with diffeent bust lengths. It shows that the aveage delay of a DRRM switch inceases appoximately linealy with bust length, which is simila to the behavio of

5 5 an EDRRM switch unde light. Significantly, unde heavy the aveage delay of an EDRRM switch does not change much with diffeent bust lengths and is much smalle than that of a DRRM switch fo long bust lengths. mean cell delay (time slots) EDRRM, bust=0 cells EDRRM, bust=6 cells EDRRM, bust= cells DRRM, bust=0 cells DRRM, bust=6 cells DRRM, bust= cells Fig. 6. The aveage cell delay unde unifom and busty taffic with diffeent bust lengths Figue 7 compaes the aveage cell delays of EDRRM and DRRM switches with diffeent switch sizes when the bust length is 6. We can see that as the switch size inceases the aveage cell delay of a DRRM switch gows apidly, while the aveage cell delay of an EDRRM switch gows moe slowly. This indicates that cell delay fo EDRRM is less sensitive to switch size than DRRM fo busty taffic. mean cell delay (time slots) EDRRM x EDRRM 8x8 EDRRM 6x6 EDRRM x DRRM x DRRM 8x8 DRRM 6x6 DRRM x Fig. 7. The aveage cell delay unde unifom and busty taffic fo diffeent switch sizes The eason why EDRRM is not sensitive to busty taffic is that all the cells aive within the same bust will be seved continuously so that little futhe delay will be suffeed because of the bustiness. In DRRM o islip, the sevice of cells in a bust is inteleaved with sevice to othe VOQ s, which may incu additional ovehead due to unsuccessful equests. Fo cells belonging to a bust at a VOQ, when one cell is seved, the next one cannot get sevice befoe all othe nonempty VOQs at the same input have been seved once. C. Aveage packet delay DRRM and EDRRM ae fixed-length switching algoithms. Vaiable-length IP packets ae segmented into fixed-length cells at the inputs, and the cells will be placed in the coesponding VOQ one by one. When a cell is tansfeed to its destination output, it will stay in a buffe and wait fo the othe cells in the same packet. Afte the complete eception of all the cells coming fom the same packet, these cells will be eassembled into a packet. The delay a cell suffeed befoe it is eassembled into a packet and deliveed to its destination includes the cell delay discussed in the last subsection and the waiting time at the output eassembly buffe. So the cell delay pefomance is not sufficient to evaluate the packet delay pefomance of a fixedlength switch. In this subsection, we conside aveage packet delay pefomance fo the DRRM and EDRRM switches. Afte a packet is segmented into cells, one cell will be put into the VOQ in each time slot. As in [], the packet delay of a packet is measued fom the time when the last cell of the packet gets into the VOQ until the time when the same last cell is tansfeed to its destined output EDRRM DRRM islip Fig. 8. The aveage packet delay when the packet size is 0 cells Figue 8 compaes the aveage packet delays of EDRRM, DRRM and islip when the switch size is 6x6 and the packet size is 0 cells. It shows that the packet delays of DRRM and islip ae simila to each othe and lage than that of EDRRM. Figue 9 shows the aveage packet delay of EDRRM and DRRM fo diffeent switch sizes unde unifom taffic with packet size 0. We can see that the aveage packet delay of EDRRM is always compaable with o smalle than that of DRRM when the switch size is lage than, even when the aveage cell delay of DRRM is smalle than that of EDRRM. The eason is that in DRRM, when one cell in a VOQ is seved, the next cell in the same VOQ needs to wait fo its next tun. Fo

6 EDRRM, x EDRRM, 8x8 EDRRM, 6x6 EDRRM, x DRRM, x DRRM, 8x8 DRRM, 6x6 DRRM, x Fig. 9. The aveage packet delay of EDRRM and DRRM unde unifom taffic with diffeent switch sizes example, unde heavy when all the VOQs ae nonempty, afte a cell is tansfeed the next cell in the same VOQ needs to wait at least time slots to get a sevice. Fo the cells in one packet, each cell needs to wait some time in the output eassembly buffe fo the next cell except the last one. On the othe hand, in EDRRM all the cells in the same packet will be seved continuously, and the numbe of time slots that the packet needs fo eassemble in an output buffe is the packet size in cells. Theefoe the packet delay of an EDRRM switch is the cell delay fo the fist cell of the packet plus the packet size in cell slot times. Indeed, an EDRRM switch is eally a packet switch and not a cell switch emulating a packet switch since packets ae sent contiguously though the switch fabic. As a esult, EDRRM does not need a complex eassembly buffe at each output pot EDRRM, packet size=5 EDRRM, packet size=0 EDRRM, packet size=0 DRRM, packet size=5 DRRM, packet size=0 DRRM, packet size= Fig. 0. The aveage packet delay when the packet size is 0 cells Figue 0 shows the aveage packet delays of a 6x6 EDRRM switch and a DRRM switch with diffeent packet sizes. We can see that fo an EDRRM switch, unde light, longe packets suffe longe packet delay, while unde heavy the aveage packet delays fo packets with diffeent size ae simila. On the othe hand, in a DRRM switch the aveage packet delay inceases linealy with the packet size. Though we do not pesent it hee, delay pefomance fo pioity taffic (e.g. eal-time taffic) can be enhanced by intoducing a high and low pioity queue in each VOQ. V. COCLUSIOS The EDRRM algoithm is a vaiation of the DRRM scheduling algoithm. The implementation complexity of EDRRM s switching fabic is the same as that of DRRM, while packet eassembly is simple than most othe popula matching schemes. In an EDRRM switch when an input is matched with an output all the cells in the coesponding VOQ ae seved continuously befoe any othe VOQ of the same input can be seved. The aveage cell delay of an EDRRM switch can be analyzed by using an exhaustive andom polling system model []. The pefomance of an EDRRM switch is compaable to o bette than a DRRM switch o an islip switch fo most taffic scenaios. The only exception is the maximum thoughput unde unifom taffic. Unde unifom i.i.d. taffic, an EDRRM switch has a lage aveage cell delay than a DRRM switch, but its aveage packet delay is lowe and not sensitive to eithe switch size o packet size. Futhemoe, EDRRM is not sensitive to taffic bustiness. Unde nonunifom taffic the thoughputs of a DRRM switch and an islip switch dop well below 00%, while the thoughput of an EDRRM switch is close to 00%. REFERECES [] M. J. Kaol, M. Hluchyj, and S. Mogan, Input vs. output queuing on a space-division packet switch, Poc. GLOBECOM 986, pp [] M. J. Kaol, M. Hluchyj, and S. Mogan, Input vesus output queuing on a space-division packet switch, IEEE Tans. on Communications, vol.5, pp. 7-56, 987. []. McKeown, V. Ananthaam, and J. Waland, Achieving 00% thoughput in an input-queued switch, IEEE IFOCOM 96, pp []. McKeown, A. Mekkittikul, V. Ananthaam and J. Waland, Achieving 00% thoughput in an Input-Queued switch, IEEE Tans. Communications, vol. 7, o. 8, pp , Aug [5]. McKeown, Scheduling algoithms fo input-queued cell switches, Ph.D. Thesis, UC Bekeley, May 995. [6] A. Chany, P. Kishna,. Patel and R. Simcoe, Algoithms fo poviding bandwidth and delay guaantees in Input-Buffeed cossbas with speedup, IWQOS 98, May 998. [7] P. Kishna,. S. Patel, A.Chany and R. Simcoe, On the speedup equied fo wok-conseving cossba switches, IWQOS 98, May 998. [8] A. Mekkittikul and. McKeown, A pactical scheduling algoithm to achieve 00% thoughput in input-queued switches, IEEE IFOCOM 98, Vol, pp , Apil 998. [9] T. E. Andeson, S. S. Owicki, J. B. Saxe and C. P. Thacke, High speed switch scheduling fo local aea netwoks, ACM Tans. on Compute Systems, vol., o., pp. 9-5, ov. 99. [0]. McKeown, The islip scheduling algoithm fo Input-Queued switches, IEEE/ACM Tans. etwoking, vol. 7, pp. 88-0, Apil 999. [] H. J. Chao, Satun: a teabit packet switch using Dual Round-Robin, IEEE Communication Magazine, vol. 8, pp. 78-8, Dec [] Y. Li, S. Panwa, H. J. Chao, On the pefomance of a Dual Round-Robin switch, IEEE IFOCOM 00, vol., pp , Apil 00. [] Y. Li, S. Panwa, H. J. Chao, Pefomance analysis of an Exhaustive Sevice Dual Round-Robin scheduling slgoithm, CATT Technical Repot, ov. 00. [] Y. A. Masan, A. Bianco, P. Giaccone, E. Leonadi, F. ei, Packet Scheduling in Input-Queued Cell-Based Switches, IEEE IFOCOM 00, vol., pp , Apil 00. [5] H. Takagi, Queueing anallysis of polling models: an update, Stochastic Analysis of Compute and Communication Systems, ew Yok: Elsevie Science and B. V. oth Holland, pp