COEN-4730 Computer Architecture Lecture 2 Review of Instruction Sets and Pipelines

Transcription

1 1 COEN-4730 Compute Achitectue Lectue 2 Review of nstuction Sets and Pipelines Cistinel Ababei Dept. of Electical and Compute Engineeing Maquette Univesity Cedits: Slides adapted fom pesentations of Sudeep Pasicha and othes: Kubiatowicz, Patteson, Mutlu, Elsevie Outline nstuction Set Pinciples (Appendix A) Pipelining (Appendix C) 2

2 2 Aival to cuent state-of-the at says that fo a new nstuction Set Vitually evey new achitectue designed afte 1980 uses a loadstoe egiste achitectue We should expect the use of geneal pupose egistes Memoy addessing modes have the ability to significantly educe instuction counts. We should expect the suppot of at least these addessing modes: displacement, immediate, and egiste indiect Should suppot these data sizes and types: 8-, 16-, 32, and 64-bit integes and 64-bit EEE 754 floating-point numbes Suppot these simple instuctions (they will dominate the numbe of instuctions executed): load, stoe, add, subtact, move egiste, and shift Suppot these instuctions fo Contol Flow: compae equal, compae not equal, compae less, banch (with a PC-elative addess at least 8 bits long), jump, call, and etun 3 Aival to cuent state-of-the at says that fo a new nstuction Set We should use fixed instuction encoding if inteested in pefomance, and use vaiable instuction encoding if inteested in code size Should povide at least 16 geneal-pupose egistes, be sue all addessing modes apply to all data tansfe instuctions, and aim fo a minimalist instuction set. This will educe the complexity of witing a coect compile (which is a majo limitation on the amount of optimization that can be done). Befoe suggesting new instuction set featues, look at optimized code fist as a compile might completely emove the instuctions the achitect ties to impove 4

3 3 Example: MPS follows those ecommendations MPS64 has bit geneal pupose egistes (GPR) Data types: 8-, 16-, 32-, and 64-bit fo integes and 32-bit single pecision and 64-bit double pecision fo floating point Addessing modes: immediate and displacement, both with 16-bit fields Thee types of instuction fomat:, R, and J Suppots the list of simple instuctions ecommended plus a few othes Contol handled though a set of jumps and a set of banches 5 MPS nstuction Encoding Micopocesso without ntelocked Pipeline Stages 3 instuction fomats: R,, and J types R J op s t d shamt funct op s t 16 bit addess op 26 bit addess 6

4 WB Data 4 Outline nstuction Set Pinciples (Appendix A) Pipelining (Appendix C) 7 MPS Datapath: 5 Stages o Steps nstuction Fetch nst. Decode. Fetch Execute Add. Calc Memoy Access Wite Back Next PC 4 Adde Next SEQ PC RS1 Next SEQ PC Zeo? MUX Addess Memoy R <= mem[pc]; PC <= PC + 4 A <= [R s ]; B <= [R t ] F/D RS2 mm File Sign Extend D/EX MUX MUX EX/MEM RD RD RD Data Memoy MEM/WB MUX slt <= A op Rop B WB <= slt [R d ] <= WB 8

5 5 Visualizing Pipelining Time (clock cycles) Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 n s t. O d e 9 Pipelining is not quite that easy! Limits to pipelining: hazads pevent next instuction fom executing duing its designated clock cycle 1. Stuctual hazads: HW cannot suppot this combination of instuctions (single peson to fold and put clothes away) 2. Data hazads: nstuction depends on esult of pio instuction still in the pipeline (missing sock) 3. Contol hazads: Caused by delay between the fetching of instuctions and decisions about changes in contol flow (banches and jumps). 10

6 6 1. One Memoy Pot/Stuctual Hazads nstuction and Data memoies ae the same memoy unit Time (clock cycles) Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 n s t. O d e Load nst 1 nst 2 nst 3 nst 4 11 One Memoy Pot/Stuctual Hazads Time (clock cycles) Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 n s t. O d e Load nst 1 nst 2 Stall nst 3 Bubble Bubble Bubble Bubble Bubble How do you bubble the pipe? Deasset all contol lines in appopiate pipe stages. 12

7 7 2. Data Hazad on R1 Time (clock cycles) F D/RF EX MEM WB n s t. add 1,2,3 sub 4,1,3 O d e and 6,1,7 o 8,1,9 xo 10,1,11 13 Thee Geneic Data Hazads Read Afte Wite (RAW) nst J ties to ead opeand befoe nst wites it: : add 1,2,3 J: sub 4,1,3 Caused by a dependence (in compile nomenclatue). This hazad esults fom an actual need fo communication. 14

8 8 Thee Geneic Data Hazads Wite Afte Read (WAR) nst J wites opeand befoe nst eads it: : sub 4,1,3 J: add 1,2,3 K: mul 6,1,7 Called an anti-dependence by compile wites. This esults fom euse of the name 1 Can t happen in MPS 5 stage pipeline because: All instuctions take 5 stages, and Reads ae always in stage 2, and Wites ae always in stage 5 15 Thee Geneic Data Hazads Wite Afte Wite (WAW) nst J wites opeand befoe nst wites it: : sub 1,4,3 J: add 1,2,3 K: mul 6,1,7 Called an output dependence by compile wites This also esults fom the euse of name 1. Can t happen in MPS 5 stage pipeline because: All instuctions take 5 stages, and Wites ae always in stage 5 Will see WAR and WAW in moe complicated pipes 16

9 9 Fowading to Avoid Data Hazad Time (clock cycles) n s t. add 1,2,3 sub 4,1,3 O d e and 6,1,7 o 8,1,9 xo 10,1,11 Take esult fom whee it s 1 st time available and move it to whee it s/could-be needed 17 Hadwae changes to suppot Fowading (a.k.a. Bypassing o Shot-cicuiting) NextPC istes D/EX mux mux EX/MEM Data Memoy MEM/WR mmediate mux 18

10 10 Fowading to Avoid LW-SW Data Hazad Time (clock cycles) n s t. O d e add 1,2,3 lw 4, 0(1) sw 4,12(1) o 8,6,9 Result of lw (to be placed into 4) is fowaded fom Mem out to the input of Mem, in ode to be stoed, sw xo 10,9,11 19 Data Hazad Even with Fowading (1/2) Time (clock cycles) n s t. lw 1, 0(2) sub 4,1,6 O d e and 6,1,7 o 8,1,9 20

11 11 Data Hazad Even with Fowading (2/2) Time (clock cycles) n s t. lw 1, 0(2) sub 4,1,6 Bubble O d e and 6,1,7 o 8,1,9 Bubble Bubble 21 How to Stall the Pipeline Foce contol values in D/EX egiste to 0 EX, MEM and WB do nop (no-opeation) Pevent update of PC and F/D egiste Using instuction is decoded again Following instuction is fetched again 1-cycle stall allows MEM to ead data fo lw Can subsequently fowad to EX stage Fowading and stalling ae fully inte-opeable; a fowad will opeate coectly even acoss a stalled-stage in the pipeline. 22

12 12 Softwae Scheduling to Avoid Load Hazads Ty poducing fast code fo a = b + c; d = e f; assuming a, b, c, d,e, and f in memoy. Slow code: 1 LW Rb,b 2 LW Rc,c 3 ADD Ra,Rb,Rc 4 SW a,ra 5 LW Re,e 6 LW Rf,f 7 SUB Rd,Re,Rf 8 SW d,rd Fast code: LW Rb,b LW Rc,c LW Re,e ADD Ra,Rb,Rc LW Rf,f SW a,ra SUB Rd,Re,Rf SW d,rd Contol Hazad on Banches - Thee Stage Stall 10: beq 1,3,22 14: and 2,3,5 18: o 6,1,7 22: add 8,1,9 36: xo 10,1,11 f we had to wait until the end of EX state to find out if banch is taken o not taken (untaken). Let s assume it s taken. What do you do with the 3 instuctions in between? We need to stall the pipeline 3 stages. This is not the case of MPS (see late slides) 24

13 WB Data 13 Banch Stall mpact f CP = 1, 30% banch, Stall 3 cycles new CP = 1.9! Two pat solution: Detemine banch taken o not soone, AND Compute taken banch addess ealie MPS banch tests if egiste = 0 o 0 MPS Solution: Move Zeo test to D/RF stage Adde to calculate new PC in D/RF stage 1 clock cycle penalty fo banch vesus 3 25 Pipelined MPS Datapath nstuction Fetch nst. Decode. Fetch Execute Add. Calc Memoy Access Wite Back Next PC 4 Adde Next SEQ PC RS1 Adde MUX Zeo? Addess Memoy F/D RS2 File D/EX MUX EX/MEM Data Memoy MEM/WB MUX mm Sign Extend RD RD RD 26

14 14 Fou Compile Time Schemes to Reduce Banch Hazad Penalties due to One-Delay Stalls #1: Stall until banch diection is clea #2: Pedict (o Teat) Banch as Not Taken Execute successo instuctions in sequence as if the banch wee a nomal instuction Squash instuctions in pipeline if banch actually taken Advantage of late pipeline state update 47% MPS banches not taken on aveage PC+4 aleady calculated, so use it to get next instuction #3: Pedict Banch as Taken 53% MPS banches taken on aveage But haven t calculated banch taget addess in MPS» MPS still incus 1 cycle banch penalty» Othe machines: banch taget known befoe outcome 27 Fou Compile Time Schemes to Reduce Banch Hazad Penalties due to One-Delay Stalls #4: Delayed Banch ntoduce the sequential successo instuction, which is executed whethe o not the banch is taken MPS uses this The job of the Compile is to make the successo instuctions valid and useful banch instuction sequential successo 1 banch delay slot banch taget if taken 28

15 15 Scheduling nstuctions into the Banch Delay Slots A. Fom befoe banch B. Fom banch taget C. Fom fall though add $1,$2,$3 if $2=0 then delay slot A is the best choice, fills delay slot & educes instuction count (C) n B, the sub instuction may need to be copied (bcoz it could be eached by anothe path), inceasing C n B and C, must be okay to execute sub when banch fails B and C ae used when A is not possible sub $4,$5,$6 add $1,$2,$3 if $1=0 then delay slot add $1,$2,$3 if $1=0 then delay slot sub $4,$5,$6 becomes becomes becomes add $1,$2,$3 if $2=0 then if $1=0 then add $1,$2,$3 add $1,$2,$3 if $1=0 then sub $4,$5,$6 sub $4,$5,$6 29 Delayed Banch Compile effectiveness fo single banch delay slot: Fills about 60% of banch delay slots About 80% of instuctions executed in banch delay slots useful in computation About 50% (60% x 80%) of slots usefully filled Delayed Banch downside: as pocessos go to deepe pipelines and multiple issue, the banch delay gows and need moe than one delay slot Delayed banching has lost populaity compaed to moe expensive but moe flexible dynamic appoaches Gowth in available tansistos has made dynamic appoaches elatively cheape 30

16 16 Moe Poblems with Pipelining Exception: An unusual event happens to an instuction duing its execution Examples: divide by zeo, undefined opcode nteupt: Hadwae signal to switch the pocesso to a new instuction steam Example: a sound cad inteupts when it needs moe audio output samples Poblem: t must appea that the exception o inteupt must appea between 2 instuctions ( i and i+1 ) The effect of all instuctions up to and including i is totaling complete No effect of any instuction afte i can take place The inteupt (exception) handle eithe abots pogam o estats at instuction i+1 31