Teaching Network Systems Design With Network Processors: Challenges And Fun With Networking

Transcription

1 Teaching Network Systems Design With Network Processors: Challenges And Fun With Networking Douglas Comer Computer Science Department Purdue University 250 N. University Street West Lafayette, IN Copyright All rights reserved. This document may not be reproduced by any means without written consent of the author.

2 PART I Introduction Teach Net. Sys. Design -- PART I 1 October, 2003

3 Topic And Scope Network processors in academia: graduate and undergraduate curricula, lab facilities, and projects Teach Net. Sys. Design -- PART I 2 October, 2003

4 Plan For The Talk Introduction and overview An example graduate course An example undergraduate course Example lab facilities Discussion Teach Net. Sys. Design -- PART I 3 October, 2003

5 Why Should Your Institution Teach Network Processors? Exciting new topic Popular among students Access to state-of-the-art technologies High teaching evaluations Just plain fun Teach Net. Sys. Design -- PART I 4 October, 2003

6 Why Should Your Institution Teach Network Processors? (continued) Gain familiarity with emerging technology Expose students to new hardware and programming paradigms Force students to think about design of network systems Allow students to experiment with embedded systems Prepare students for research Teach Net. Sys. Design -- PART I 5 October, 2003

7 Possible NP Course Emphasis Hardware engineering Internal structure of network processor chip(s) Design of external interfaces Engineering tradeoffs Software design Programming models and paradigms Special-purpose programming languages Approaches to parallelism Teach Net. Sys. Design -- PART I 6 October, 2003

8 Networking Possible NP Course Emphasis (continued) Analysis of protocols Implementation of a stack Monitoring and control of traffic Network systems design Overall design of switch, router, firewall, etc. High-speed protocol implementation Integration of hardware and software Teach Net. Sys. Design -- PART I 7 October, 2003

9 Networking Possible NP Course Emphasis (continued) Analysis of protocols Implementation of a stack Monitoring and control of traffic Network systems design Overall design of switch, router, firewall, etc. High-speed protocol implementation Integration of hardware and software Teach Net. Sys. Design -- PART I 8 October, 2003

10 What Should You Tell Students? There is a huge opportunity for Learning a new technology Research in a new field Teach Net. Sys. Design -- PART I 8 October, 2003

11 The Challenge Discover ways to improve the design and manufacture of complex networking systems. Teach Net. Sys. Design -- PART I 9 October, 2003

12 The Big Questions What systems? Everything we have now plus new What physical communication mechanisms? Existing and emerging communication technologies What speeds? Two orders of magnitude beyond those in use What protocols? Traditional and new Teach Net. Sys. Design -- PART I 10 October, 2003

13 What applications? The Big Questions (continued) New applications not yet designed / standardized Teach Net. Sys. Design -- PART I 11 October, 2003

14 The Challenge (restated) Discover flexible, general technologies that enable rapid, low-cost design and manufacture of scalable, robust, efficient network systems that run existing and new protocols, perform existing and new functions for higher-speed networks to support a variety of applications. Teach Net. Sys. Design -- PART I 12 October, 2003

15 Special Difficulties Ambitious goal Vague problem statement Problem is evolving with the solution Pressure from Changing infrastructure (e.g., wireless) Changing applications (e.g., VoIP) Teach Net. Sys. Design -- PART I 13 October, 2003

16 Statement Of Hope (1990 version) If there is hope, it lies in faster CPUs. Teach Net. Sys. Design -- PART I 14 October, 2003

17 Statement Of Hope (1995 version) If there is hope, it lies in ASIC designers. Teach Net. Sys. Design -- PART I 15 October, 2003

18 Statement Of Hope (1999 version)??? If there is hope, it lies in ASIC designers. Teach Net. Sys. Design -- PART I 16 October, 2003

19 Network Processors To The Rescue Devise new hardware building blocks Make them programmable Include support for protocol processing and I/O Embedded processor(s) for control tasks Special-purpose processor(s) for packet processing tasks Provide hardware for specialized tasks such as table lookup Integrate as much as possible onto one chip Call the result a network processor Teach Net. Sys. Design -- PART I 17 October, 2003

20 Definition A network processor is a special-purpose, programmable hardware device that combines the low cost and flexibility of a RISC processor with the speed and scalability of custom silicon (i.e., ASIC chips). Network processors are building blocks used to construct network systems. Teach Net. Sys. Design -- PART I 18 October, 2003

21 Statement Of Hope (2003 version) programmers! If there is hope, it lies in ASIC designers. Teach Net. Sys. Design -- PART I 19 October, 2003

22 Disclaimer In the field of network processors, I am a tyro. Teach Net. Sys. Design -- PART I 20 October, 2003

23 Definition Tyro \Ty ro\, n.; pl. Tyros. A beginner in learning; one who is in the rudiments of any branch of study; a person imperfectly acquainted with a subject; a novice. Teach Net. Sys. Design -- PART I 21 October, 2003

24 By Definition In the field of network processors, you are all tyros. Teach Net. Sys. Design -- PART I 22 October, 2003

25 In Our Defense When it comes to network processors, everyone is a tyro. Teach Net. Sys. Design -- PART I 23 October, 2003

26 Questions?

27 PART II An Example Graduate Course On Network Processors Teach Net. Sys. Design -- PART II 1 October, 2003

28 Goals Become familiar with a variety of network processor architectures Be able to assess and discuss design tradeoffs and limitations of each approach Learn the details of at least one NP Gain experience implementing protocol processing functions in software Understand the issues of scaling a network system Teach Net. Sys. Design -- PART II 2 October, 2003

29 Organization Seminar Professor Gives a few introductory lectures Leads discussion Asks questions Students Read about network processors Design and implement a project Report on their project Teach Net. Sys. Design -- PART II 3 October, 2003

30 Topics Hardware architectures for protocol processing Classification Switching fabrics Traffic management Network processors Design tradeoffs and consequences Details of one example network processor Programming model and program optimization Cross-development environment Teach Net. Sys. Design -- PART II 4 October, 2003

31 Topics Hardware architectures for protocol processing Classification Switching fabrics Traffic management Design tradeoffs and consequences Details of one example network processor Programming model and program optimization Cross-development environment Teach Net. Sys. Design -- PART II 5 October, 2003

32 What Students Do Not Learn EE details VLSI technology and design rules Chip interfaces: ICs and pin-outs Waveforms, timing, or voltage How to wire wrap or solder Economic details Comprehensive list of vendors and commercial products Price points Teach Net. Sys. Design -- PART II 5 October, 2003

33 Example Grading Scheme Preliminary project presentations given in class 30% Written project report on final project 10% Final project presentation and demo 60% Teach Net. Sys. Design -- PART II 6 October, 2003

34 Many possibilities Student Projects Focus on hardware (e.g., measure bus or instruction times) Design and implement traffic management / policing Find the limits of a particular NP Compare NP architectures Implement application-layer functionality Other (e.g., measure the effect of security on speed) Students choose their topic (subject to approval) Teach Net. Sys. Design -- PART II 7 October, 2003

35 Project Teams Possibilities Work alone Work in a group of two Work in a group of three or more Students choose group composition and size Note: project only approved if commensurate with group size Teach Net. Sys. Design -- PART II 8 October, 2003

36 Project Administration Register group (week 2) Submit a topic for approval (week 4) Give a preliminary proposal (week 5) Report on status (week 9 10) Demonstrate project and turn in report (weeks 13 15) Teach Net. Sys. Design -- PART II 9 October, 2003

37 Example Student Projects Network Address Translator (NAT box) Web load balancer IPsec implementation Configurable Internet firewall Traffic monitor (collect per-flow statistics) Virtual Private Network router Intrusion detection system TCP terminator IPv6 forwarder Teach Net. Sys. Design -- PART II 10 October, 2003

38 Recommended Textbook Comer, D., Network Systems Design Using Network Processors, Intel IXP Version, Prentice Hall, ISBN Teach Net. Sys. Design -- PART II 11 October, 2003

39 Enthusiastic response Excellent course Student Reaction One of the most interesting and fun courses I have taken at Purdue Projects that go beyond the minimum High course evaluations Teach Net. Sys. Design -- PART II 12 October, 2003

40 Questions?

41 PART III An Example Undergraduate Course On Network Processors Teach Net. Sys. Design -- PART III 1 October, 2003

42 Goals Become familiar with concept of network processor Appreciate that the field is new and evolving Gain experience programming one network processor Implement basic protocol processing Layer 2 bridging Packet header parsing Be able to characterize and describe features of network processors Teach Net. Sys. Design -- PART III 2 October, 2003

43 Organization Lecture course plus lab Professor Lectures throughout semester Covers concepts and big picture Students Learn from a textbook and lectures Program in lab sections under supervision of TA Begin with simplified API Write small pieces of code Teach Net. Sys. Design -- PART III 3 October, 2003

44 Topics Network systems and protocol processing History of network systems implementation Classification and classification languages Switching fabric concepts Motivation for network processors Survey of network processor architectures Teach Net. Sys. Design -- PART III 4 October, 2003

45 Topics (continued) Detailed example of one network processor Architecture of each piece I/O and internal memory interfaces Programming model and structure of software Cross-development environment Examples of code Teach Net. Sys. Design -- PART III 5 October, 2003

46 What Students Do Not Learn Engineering details How to create large, complex network systems All possible optimizations All architectural details How to make design tradeoffs Products and associated economic costs Teach Net. Sys. Design -- PART III 6 October, 2003

47 Example Grading Scheme In-class quizzes 5% Midterm and final exams 35% Programming projects in lab 60% Teach Net. Sys. Design -- PART III 7 October, 2003

48 The Lab Scheduling Problem Undergrads have little background First half of course covers general material Network systems Alternative implementations Architectures Second half of course presents details of one NP Hardware Programming model Question: what lab projects can students do during the first half of the course? Teach Net. Sys. Design -- PART III 8 October, 2003

49 Our Solution Present students with a higher-level programming system Provide a simplified API that hides details Make it easy to transmit or receive packets Have students use embedded processor Bridge IP fragmenter Defer microengine programming to second half of course Teach Net. Sys. Design -- PART III 9 October, 2003

50 Simplified API Handles all I/O details Supports protocols that use retransmission Introduces students to asynchronous input Functions Function onstartup() onshutdown() newfbuf() recvframe() sendframe() periodic_call() delayed_call() cancel_call() Purpose Called once at initialization Called once at termination Allocate a frame buffer Called when frame arrives Used to transmit an outgoing frame Start a periodic timer Invoke a function after a delay Cancel a timer Teach Net. Sys. Design -- PART III 10 October, 2003

51 Student Lab Projects (Intel) Using simplified API on embedded processor Compile, download, and run code Packet analyzer (IP/TCP/ARP) Layer 2 bridge IP fragmenter Traffic classifier (i.e., packet analyzer) Teach Net. Sys. Design -- PART III 11 October, 2003

52 Student Lab Projects (Intel) (continued) Using microcode on packet engine Compile, download, and run a program Classifier microblock Frame forwarding microblock, where destination depends on classification Teach Net. Sys. Design -- PART III 12 October, 2003

53 Textbooks Main text Comer, D., Network Systems Design Using Network Processors, Intel IXP Version, Prentice Hall, ISBN Lab Manual Comer, D., Hands-On Networking With Internet Applications, 2nd Edition, Prentice Hall, Teach Net. Sys. Design -- PART III 13 October, 2003

54 Student Reaction Enthusiastic response Awesome class Best class I have ever taken at Purdue Enjoyed working with real hardware High course evaluations Teach Net. Sys. Design -- PART III 14 October, 2003

55 Questions?

56 PART IV Laboratory Facilities For Hands-on Work With Network Processors Teach Net. Sys. Design -- PART IV 1 October, 2003

57 Why A Laboratory? Absolutely essential: students learn by doing Reinforces concepts presented in class Exposes students to new (unusual) hardware Gives students concrete understanding of details Keeps courses tied to reality Teach Net. Sys. Design -- PART IV 2 October, 2003

58 Equipment Needed For A Lab Two types Front-end facilities Conventional workstations Connected to production network Run standard OS Used to prepare software Back-end facilities Used for experimentation Students download/configure Teach Net. Sys. Design -- PART IV 3 October, 2003

59 Comer s Xinu Lab Established in 1984 Provides hands-on access to hardware Used for research and education Operating systems Networking and Internetworking Teach Net. Sys. Design -- PART IV 4 October, 2003

60 Facilities In The Xinu Lab Front-end systems 24 workstations running Linux Connected via gigabit Ethernet Back-end systems 85 PCs Miscellaneous routers, load balancer, etc. Networks Gigabit Ethernet (production) Various 10/100/1000 Ethernets (experimental) Thanks to: Intel, IBM, Cisco, Agere, AT&T, and others. Teach Net. Sys. Design -- PART IV 5 October, 2003

61 Front-end Systems In Comer s Lab Teach Net. Sys. Design -- PART IV 6 October, 2003

62 Normal View Of Xinu Lab Teach Net. Sys. Design -- PART IV 7 October, 2003

63 Back-end Systems In Comer s Lab... Teach Net. Sys. Design -- PART IV 8 October, 2003

64 Lab Infrastructure Allows remote access to all facilities Software designed and built at Purdue Provides Automated allocation of back-ends Image download Communication with back-end console Control (reboot) Teach Net. Sys. Design -- PART IV 9 October, 2003

65 Conceptual Interconnections Lab Network lab management computer reset wires back-end computers front-end computers reset controller SCSI bus console serial connections console multiplexor Commercial terminal multiplexor Custom reboot hardware Teach Net. Sys. Design -- PART IV 10 October, 2003

66 Introduced in 2002 Uses VLAN switch Automated Reconfigurable Testbed System (ART) Provides automated connection of back-ends to networks Allows user to define and store configuration Offers GUI interface Teach Net. Sys. Design -- PART IV 11 October, 2003

67 Network Processors In The Xinu Lab Added in 2001 Currently have 22 Intel IXP1200 systems 2400s 2 Agere Payload Plus 2.5 systems APP550s 2 IBM NP4GS3 systems??? Other lab equipment used with network processors Hubs Switches Cables Teach Net. Sys. Design -- PART IV 12 October, 2003

68 Reference Platform Provided by vendor Targeted at potential customers Usually includes Hardware testbed Simulator / emulator Cross-development software Download and bootstrap software Reference implementations Teach Net. Sys. Design -- PART IV 13 October, 2003

69 Two Types Of Reference Platforms Stand-alone Separate chassis and power supply Contains control processor plus NP system Single-board testbed Plugs into control system (usually a PC) Controlled via bus Teach Net. Sys. Design -- PART IV 14 October, 2003

70 Example Reference Hardware (Intel) Single-board network processor testbed Plugs into PCI bus on a PC Code name Bridal Veil Manufactured by Radisys Teach Net. Sys. Design -- PART IV 15 October, 2003

71 Items On The Intel Bridal Veil Reference System Quantity or Size Item 1 IXP1200 network processor (232MHz) 8 Mbytes of SRAM memory 256 Mbytes of SDRAM memory 8 Mbytes of Flash ROM memory 4 10/100 Ethernet ports 1 Serial interface (console) 1 PCI bus interface 1 PMC expansion site Teach Net. Sys. Design -- PART IV 16 October, 2003

72 Intel Reference Software Known as Software Development Kit (SDK) Runs on PC Includes: Software C compiler MicroC compiler Assembler Downloader Monitor Bootstrap Reference Code Purpose Compile programs for the StrongARM Compile programs for the microengines Assemble programs for the microengines Load software into the network processor Communicate with the network processor and interact with running software Start the network processor running Example programs for the IXP1200 that show how to implement basic functions Teach Net. Sys. Design -- PART IV 17 October, 2003

73 External Access SDRAM accessed via SDRAM bus SRAM and Flash accessed via SRAM bus Ethernet ports accessed via IX bus Code and data downloaded via PCI bus NFS accessed via PCI bus StrongARM accessed via Serial line (console) Telnet Teach Net. Sys. Design -- PART IV 18 October, 2003

74 Basic Paradigm Build software on conventional computer Load into reference system Test / measure results Teach Net. Sys. Design -- PART IV 19 October, 2003

75 Our Requirements Intel SDK designed to use Windows system (compile) Unix downloader Our requirement No Windows Solution Windows emulator when needed (Wine) Teach Net. Sys. Design -- PART IV 20 October, 2003

76 Questions?

77 STOP