HARDWARE IN REAL-TIME SYSTEMS HERMANN HÄRTIG, WITH MARCUS VÖLP

Transcription

1 Faculty of Computer Science Institute of Systems Architecture, Operating Systems Group HARDWARE IN REAL-TIME SYSTEMS HERMANN HÄRTIG, WITH MARCUS VÖLP

2 A SIMPLE PROBLEM event PC how to create a precise timestamp for the event? 2

3 LECTURE Hardware-Sources of Unpredictability Interrupt Latency Memory System: Caches, VM, Pipeline System Management Mode => Special-Purpose Hardware => Use of Unpredictable HW: Cache Partitioning Real-Time Communication: separate lecture in this class 3

4 INTERRUPT LATENCY Sources of Delay disabled/enabled interrupts Device await instruction boundary kernel entry select handler code in OS Interrupt Controller CPU cache state Some of them not predictable Software 4

5 SYSTEM MANAGEMENT MODE PC platforms sits underneath operating system Invoked using non-maskable interrupt Used for platform specifics, correction of design errors, thermal management Can be switched off, but better do not try Adds unpredictable delays 5

6 SPECIAL PURPOSE RT-HW Special Purpose Hardware for Embedded Real-Time Low Latency Interrupt Mode Interrupt Handlers consisting of a single instruction Capture Compare Units Scratchpad Memories Real-Time Clocks 6

7 CAPTURE/COMPARE UNITS Problem: precise time stamp of event trigger event at precise time interrupt handler: jitter to high example: SAB 80C166 7

8 SINGLE INSTRUCTION HANDLER Objective: zero overhead execute just 1 instruction per signal Programmer Interface: counter decrement on signal, trigger CPU interrupt on counter==0 byte / word select direction source / dest select width of transfer (byte or word) either source or dest to update address Example: Peripheral Event Controller (PEC), SAB 80C166 8

9 SINGLE INSTRUCTION HANDLER PEC-Semantic expressed as Signal-Handler: signal () { if (counter--) *dest++ = *src; => minimal response time (~3 cycles) => PEC can execute at external clock rate } else trigger_interrupt(); Example: Peripheral Event Controller (PEC), SAB 80C166 9

10 LOW-LATENCY INTERRUPT Extra Interrupt Modi, e.g. ARM IRQ + FIQ FIQ interrupts IRQ FIQ: no need to save registers in handler 5 registers immediately available Worst case FIQ (PL190 VIC, if some rules are followed): Interrupt Synch: 3 cycles worst case of current instruction: 7 cycles sum: 12 cycles Entry of first instruction: 2 cycles see technical manual for details (last slide) 10

11 MEMORY SYSTEM HW core core CPU/Devices Virtual Addr. L1 Cache Network/Bus Page TLB L2 Cache Memory C. tables Physical Addr. L3 Cache DRAM 11

12 SCRATCH PAD MEMORY core (S)RAM 12

13 THE PROBLEM competing accesses to addresses that share cache lines especially critical sharing among address spaces (context switches) 13

14 CACHE PARTITIONING Goal partition cache to minimize interference between RT/RT or RT/NRT code pieces/applications General method: address regions map to cache sets Control allocation to address regions Approaches Compiler/Linker/Operating System/Hardware 14

15 APPLICATION ISOLATION Legacy Linux App RT App RT App Cache 15

16 HOW CACHES WORK core Address cache line 16

17 CACHES: THE INDEX Address 17

18 CACHES: THE TAG Address = TRUE: use cache line FALSE: write out and reload cache line 18

19 CACHES: THE LAST FEW BITS within-cache line address Address 19

20 MULTI WAY CACHES way 0 way 1 way 2 way n-1 index Address = = = = 20

21 MULTI-WAY CACHE FOR RT Hardware support to Lock complete ways OR Attach ways to cores/tasks advane: transparent to applications relatively simple for the operating system disadvane: corse granularity (in multiples of ways), there may be not enough ways 21

22 CACHE COLORING index Address = 22

23 CACHE COLORING use addresses with same index-value index for isolation Address - assign indices to code/ pieces - use programmer skills, compilers, operating systems - can we do it transparent for (legacy) applications? 23

24 EXAMPLE 4 bit index: disadvanes: gaps + waste : 4 bit XC index C: 8 bit Address 00C0..F 01C0..F 02C0..F simple example: 2 way cache 16 bit address machine 16 Byte cache lines, FFC0..F 4 bit index, 8 bit 24

25 DISADVANTAGES gaps: address space is fragmented into many small pieces compiler/programmer must make sure that only these pieces are used not useful for legacy applications waste: these pieces can be used by one code/ piece we remove these limitation in two steps 25

26 MEMORY SYSTEM HW core core CPU/Devices Virtual Addr. L1 Cache Network/Bus Page TLB L2 Cache Memory C. tables Physical Addr. L3 Cache DRAM 26

27 INDEX Address 27

28 VIRT OR PHYS CACHE???? index? discussion virtual caches: - slightly faster Virtual Address - context switch? TLB TLB - sharing most architectures: Physical Address - physical s - L1: (virt = phys) indices L2/L3: phys indices 28

29 PAGE COLORING Virtual VPN Address - physical indices!!! TLB TLB - Mapping of VPN to PPN is under control of OS Physical PPN Address - PPN.index under control of OS PN Virtual Page Number PN Physical Page Number 29

30 PAGE COLORING VPN { PPN { - the index part in the PPN defines a set of cache lines referred to as colors - OS can control cache usage by assigning colors to address spaces - no gaps in virtual address space 30

31 PAGE COLORING VPN waste of main memory { PPN main memory 31

32 PAGE COLORING VPN loss of phys. address space { so far never implemented PPN BPN main memory 32

33 MATERIAL ARM PrimeCell Vectored Interrupt Controller (PL190) Technical Reference Manual Siemens SAB 80C166 Handbook More on (results in) Cache Partitioning: Liedtke, Härtig, Hohmuth (RTAS '97): Operating system control cache predictability for real-time applications 33