588 IEEE/ACM TRANSACTIONS ON NETWORKING, VOL. 7, NO. 4, AUGUST 1999

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1 588 IEEE/ACM TRANSACTIONS ON NETWORKING, VOL 7, NO 4, AUGUST 1999 The Deflection Self-Routing Banyan Network: A Large-Scale ATM Switch Using the Fully Adaptive Self-Routing its Performance Analyses Jae-Hyun Park, Member, IEEE, Hyunsoo Yoon, Heung-Kyu Lee Abstract Because the Internet traffic that will be major traffic of broadb integrated services digital networks is bursty when cells are being switched within the multistage switching network, it has a higher possibility that multiple cells arriving simultaneously at a switching element through dferent incoming links may have to be forwarded along the same outgoing link In this paper, we propose a high-performance large-scale ATM switch dealing with such link contention problem It is a new unbuffered augmented Banyan network using fully adaptive selfrouting control: the deflection self-routing Banyan network To utilize all the links of the network as alternate paths, we employ the deflection-routing algorithm in each switching element, such that cells failing to get selected for the intended link are sent along dferent links, in the willing that they later return, or detour the contended link continue their journey to the destination Cells are never dropped within the switching network, whereas the switch has no multiple cell buffers The proposed routing is as simple as that of the generic Banyan network, all the switch elements (SE s) have a unorm structure To design proposed the network its self-routing, we use topological properties that all the SE s of the Banyan network are arranged in a regular pattern topologically We formulate prove these properties through an algebraic formalism We also ran a performance analysis to provide quantitative comparison against the Banyan network the replicated Banyan networks As a result, we show that the new network has a far better performance scalability than the other networks Index Terms Algebraic formalism, ATM switch, deflection self-routing Banyan network, performance evaluation, topological properties, unbuffered Banyan network I INTRODUCTION MULTISTAGE switching networks have been widely used as efficient interconnection structures for parallel computer systems the switching nodes in high-speed communication networks In the future, multistage switching networks are also expected to be used in broadb integrated services digital networks (B-ISDN s) transport systems based on the asynchronous transfer mode (ATM) [1] The reasons lie in their suitability to VLSI implementation their Manuscript received February 27, 1998; revised December 11, 1998; approved by IEEE/ACM TRANSACTIONS ON NETWORKING Editor H J Chao J-H Park is with the System Architecture Laboratory, Samsung Electronics Company, Bundang-ku, Sungnam , Korea ( jaehyunpark@ieeeorg) H Yoon H-K Lee are with the Department of Computer Science, Korea Advanced Institute of Science Technology, Yusung-Ku, Taejon , Korea ( hyoon@camarskaistackr; hklee@camarskaistackr) Publisher Item Identier S (99)06954-X self-routing capability [2] This class of networks is usually known as a Banyan network The multistage switching network is built up of smaller switch elements (SE s), which are connected, through their links, to other SE s or terminal devices Because the Internet data traffic that will be majority of the traffic in a future B-ISDN is bursty, there is a higher possibility that there are multiple cells arriving simultaneously at an SE through dferent incoming links that may have to forward along the same outgoing link Furthermore, the larger the network is, the more unbalanced traffic patterns the network has, the higher possibility of such output contention There are many ways to deal with the output contention: adding a distribution network in front of a routing network, using several networks in parallel, recirculating cells, adding one or more extra stages to a network, deflecting cells, augmenting extra internal links modying self-routing, increasing the bwidth of internal links relative to the ports, providing internal buffers [3] However, most of them have shortcomings: they require much more hardware or complicated routing scheme or both Although increasing the bwidth of internal links providing internal buffers have been widely used to implement commercialized ATM switching systems [4], the hardware cost of these schemes is so expensive, because the majority of data traffic is bursty has unbalanced traffic patterns [5], [6] Deflection routing is a good alternative to treat the output contention: cells failing to get selected for the destined link are sent along dferent links, in the willing that they later return, or detour the contended link continue their journey to the destination Deflection routing is used in high-speed multihop networks, since it gives a good performance [7] is easy to implement [8] As a kind of deflection routing, some methods of augmenting extra internal links to the Banyan network modying its self-routing have been proposed in [9] [11] They have succeeded in improving the performance imparting the fault tolerance However, they use partially adaptive selfrouting; they place their main stress upon supplement links, partially use already existing links As a result, they did not consider all links of the Banyan network as alternate links/paths We propose a high-performance large-scale ATM switch that use all links of the Banyan network as alternate links/paths We name this new augmented Banyan network the cyclic /99$ IEEE

2 PARK et al: DEFLECTION SELF-ROUTING BANYAN NETORK 589 Banyan network This switching network is a class of the deflection self-routing Banyan network, of which the fully adaptive self-routing scheme exploits all links of SE s as alternate links/paths While the proposed network has no internal buffer, it never loses cells within the switching network No memory buffer means that it is easy to speed up, can even be used for fiber-optic switching This approach also eliminates the need for backward status links in order to implement flow control These characteristics imply the implementation using gate-array technology that offer greater flexibility in the cost, performance, other design parameters than dedicated VLSI solution By adding extra links between SE s within the same stage extending the self-routing scheme, we could use all links as alternate links/paths Therefore, the proposed network under a balanced traffic pattern an unbalanced one has a far better performance scalability than other networks To design the proposed network its self-routing, we use the topological properties that all SE s of the Banyan network are arranged in a regular pattern in terms of topology In other words, each stage of the Banyan network is composed of sequence of the cyclic group, realized with SE s also stages connected symmetrically through the links between them We prove such properties of the Banyan networks through an algebraic formalism in this paper The proposed self-routing is as simple as that of the Banyan network, all SE s of the proposed network have a unorm structure We also present a simple cell-resequencing buffer providing a hardware-sliding window mechanism so that the proposed network preserves the integrity of cell sequence This paper is organized as follows In Section II, we investigate the topological properties of the Banyan network to derive the cyclic Banyan network its self-routing scheme through an algebraic formalism In Section III, we present the definition of the proposed network its routing scheme In Section IV, we analyze the performance of the network under unorm traffic via an analytic model simulation, evaluate it under nonunorm traffic via simulation Finally, concluding remarks are given in Section V II TOPOLOGICAL PROPERTIES OF THE BANYAN NETWORK The Banyan network as so defined by Goke Lipovski provides unique paths between source port to destination port More particularly, the set of paths destined for an SE in the network form a spanning tree, the set of paths from an SE also form a spanning tree [12] However, only a certain class of spanning trees, from among all such spanning trees, is important because all SE s belonging to the same spanning tree can deliver a cell through the same destination port by using the basic self-routing algorithm As depicted by thick continuous lines in Fig 1, spanning trees such as this consist of the links, from each SE of the last stage (as the root of the tree) to all SE s of the first stage (as the leaves of the tree), together with the SE s connected with the links as its nodes In related works [9] [11], such spanning trees had been used to make the Banyan network fault-tolerable by providing alternate paths In [11], they gained the alternate paths by chaining the SE s in the same level within the trees with augmented links When a fault occurs in the selected output link, the cell can be delivered to an SE of the same level within the tree, as depicted with arrow A in Fig 1, then routed correctly again from that SE to the destination port using the basic routing algorithm of the Banyan network In other works [9], [10], they also made alternate paths by connecting the additional backward (forward) link to the child (parent) SE When the fault occurs, the cell can be delivered to a child (parent) SE of a step lower (higher) level within the tree through the additional link as depicted with arrow B ( C ) in Fig 1 In order to impart the fault-tolerance to the Banyan network, or to improve the performance, or both, these schemes place their main stress upon the supplemental link The reason that once the cell routed through the output link that is not destined, not through the augmented link, there is no path leading the cell to the destination port Thus, these schemes use just only the augmented link to detour faulty/congested link [13] There is, however, always a vacant link within the very same SE at the competition moment, so far as all input cells do not destine distinct links, respectively Our objective is to provide an augmented Banyan network an appropriate fully adaptive self-routing algorithm thereof, wherein the routing algorithm use all links of the basic Banyan network as alternate links/paths, in addition to the supplemental links In this section, we investigate the topological properties of the Banyan network to derive the cyclic Banyan network the fully adaptive self-routing algorithm corresponding to the network Since it is widely known that many multistage interconnection networks (MIN) are topologically equivalent with each other [14], we will cite the delta network [15] for the sake of simplicity clarity of illustration in the following discussion Also, we will refer to SE s links through a numbering convention of the same type as that proposed in [14] This convention will be used to both describe the configuration of the delta network the cyclic Banyan network, to prove the validity of the routing scheme For the switching network, the stages are numbered consecutively from to beginning with the left-most stage as stage 1 For each of the stages, each link (input or output) associated with the stage has a relative position, with respect to the top of the stage, that will be identied by a binary numeral having digits, link In each stage, each SE has a relative position, with respect to the top of the stage, that will be identied by a binary numeral with digits, in a manner similar to the representation of a link, that will be termed the level The destination address of an input cell is represented by an expression First of all, let us define the delta network as the following topological definition Definition 1: For each SE at a stage of the delta network, each output link of the SE is connected with an input link of stage

3 590 IEEE/ACM TRANSACTIONS ON NETWORKING, VOL 7, NO 4, AUGUST 1999 Fig 1 The spanning trees, the equivalence class of SE s, the alternate paths in the delta network (N =16) in accordance with connected with link connected with link where The function s describe the interconnections by mapping an SE in stage to two SE s in stage one SE per output link out of the SE in stage The will be used to describe an SE that is reachable via the lower output link of the SE, for the upper output link The s is useful for deriving of the topological relationships between the SE s Now, we define an abbreviation to indicate an SE by its stage level Definition 2: The symbol is the SE located at level of stage where 1 We will now show that an equivalence relation exists between the SE s of a stage as follows Definition 3: For the self-routing control function implemented in the delta network, denotes the set of output links in the last stage (ie, stage ) attainable from the SE, that is, is the set of output links reached when is applied to all possible addresses A, where connected with link When a cell arrives at any input link of an SE in stage, the function is applied the address associated with the cell in order to transfer the cell through an output link to an SE in stage Let us define the relation on the set of all SE s of a stage The symbol is defined to represent the set of all SE s of a stage Definition 4: is the set that is composed of all SE s of stage Definition 5: A relation on the set is a subset of the Cartesian product with the following property: Lemma 1: The relation on the set is an equivalence relation The fact that the relation is an equivalence relation facilitates the proof of certain properties of the delta network that are useful for deriving an adaptive self-routing algorithm Definition 6: Given the relation an SE of, the equivalence class as follows: is a subset determined by Let us define the notation / to indicate a partition induced by an equivalence relation Definition 7: At stage in the Banyan network, the set of equivalence classes induced by the relation is given by the notation / defined by Now we will present useful properties to derive the fully adaptive self-routing scheme Theorem 1: Each of all SE s belong to the same equivalence class in stage (ie, all ) have such an identier that terminate with the same ( )-digit binary sequence,

4 PARK et al: DEFLECTION SELF-ROUTING BANYAN NETORK 591 (where ) When, ie, in the first stage, all SE s are in the same equivalence class, so there is not the same bit in the identiers for all SE s of the first stage [16] From Theorem 1, the following holds Corollary 1: For a cell, it starts from any SE within an equivalence class, it will be deliver to the same output port by the routing function Theorem 1 provides a basis for the following definitions results, which establish a topological characterization of the Banyan network Let us define the function to consolidate relationship among the SE s within the same stage Definition 8: At stage in the Banyan network, the SE that is levels away relatively from an SE is given by the function defined by the SE that is levels away relatively from an SE is given by the function defined by where The following corollary shows that the relative topological distance between two adjacent SE s belong to the same equivalence class is same Corollary 2: The topological distance between two SE s chosen romly from all SE s belong to an equivalence class in stage is levels where Proof: According to Definitions 7 8, Theorem 1, proven According to Corollary 2, we can show that there are dferent kinds of SE s in stage Corollary 3: The order of the equivalence classes in stage is From Corollaries 2 3, we can show that the SE s of the dferent classes in a stage are set in regular array that is generated by applying the function consecutively Theorem 2: Let be the group of the set under the operation where the SE s are distinguished by the logical identity, relation Then, the is the cyclic group such that a any element SE of set is the generator of As a result, Corollary 2 shows the key property of the general cyclic group, also Theorem 2 Corollaries 2 3 show that each stage of the Banyan network is composed of the sequences of the cyclic group of SE s, such that the order is In Theorem 3 hereinafter, we can show the equivalence relation exists between SE s, then the SE s given by applying the function or the function or both also have the equivalence relation with each other In addition, it is worth noting that the cyclic group is the subgroup of the cyclic group of the next stage Theorem 3: The relation is a congruence, that satisfies the following requirements: 1) the relation is an equivalence relation 2) for function function we have, for all in the set of all SE s in the network, the following implication: Proof: According to Definitions 1 5, Lemma 1, Theorem 2, proven The theorems corollaries provide a basis to derive the following theorem corollaries, which constitute the basis of the cyclic Banyan network the fully adaptive self-routing scheme thereof Corollary 4: The path starting from an output link can be replaced with another path starting from an output link of the equivalence SE thereof where Proof: By applying Definition 8, Theorem 1, Corollary 2 above, proven Also, the following theorem shows that there exists a path that can transfer cells within a stage, then the path starting from an output link of the SE that is certain levels away from an initial SE can be replaced with another path starting from an output link of the initial SE then going to the SE that is two times the original levels away, in the next stage Using this characteristic, we can defer the congestion which occurred in a stage to that in the next stages Theorem 4: If there is the path that can transfer the cell within a stage, which is represented by the function the path starting from an output link of the SE that is levels away from an initial SE can be replaced with another path starting from an output link of the initial SE then going to the SE that is levels away, in the next stage where, Proof: When, (by Definitions 1 8) Let s assume when When, as follows: (by Definition 8) by case (by case (by Definition 8) By the mathematical induction, proven This proves the equality for The case for follows in a similar manner, mutatis mutis Also, the case for follows in a similar manner, mutatis mutis

5 592 IEEE/ACM TRANSACTIONS ON NETWORKING, VOL 7, NO 4, AUGUST 1999 It is worth to note that the function is a homomorphism The following corollary shows that a path starting from an output link can be substituted with another path starting from another output link within the same SE Corollary 5: (by Definitions 1 8) (by the above equation) (by Definition 8, Corollary 2, Theorem 4) (by Definitions 1 8) (by the above equation) (by Definitions 8, Corollary 2, Theorem 4) where As we have shown in the foregoing discussion, the Banyan networks have topological properties that make them attractive starting points from which to derive a new multipath unbuffered augmented Banyan network nonminimal fully adaptive self-routing control algorithm for those network If we make interconnections among the SE s within a stage (ie, from a SE to another SE ), then all the existing links, as well as all the additional links, can be used for fully adaptive self-routing control Fig 2 illustrates conceptually how cell is transferred through the switching network in accordance with the fully adaptive self-routing control algorithm Each circle sts for a stage, the solid line belong to a circle sts for the cyclic group within the stage The unidirectional arrows from a cyclic group to its supergroup in the next stage illustrates the interstage routing The bidirectional arrow over cyclic groups illustrates possible intrastage routing The number over each circle means the order of the cyclic group of each stage in Banyan network Since there can be various kinds of interconnections to provide paths from an SE to another SE we can make several augmented Banyan networks for which we can provide fully adaptive self-routing algorithms The cyclic Banyan architecture species a particular type of intrastage connection among the SE s This architecture provides a network with efficiency cost advantages relative to other extensions III CYCLIC BANYAN NETWORK AND ITS SELF-ROUTING In this section, we present a cost-effective extension of the Banyan network, the cyclic Banyan network, the fully adaptive self-routing scheme for the network A Network Configuration The cyclic Banyan network can be obtained from the delta network, such as that depicted in Fig 1, by the Fig 2 The cyclic groups, the homomorphism j, the fully adaptive self-routing addition of links chaining all SE s of a stage Implementation of these additional links requires the network to comprise augmented SE s, each having chain-in links chain-out links as well as the input links output links appropriate for the delta network Fig 3 illustrates an SE having the additional links appropriate for the use in the cyclic Banyan network The configuration of SE derives from a 2 2 configuration having only two input links two output links, such as would be used in the delta network Two chain-in links two chain-out links have been added to the configuration of a 2 2 switch SE is thus a 4 4 crossbar switch that operates in accordance with a fully adaptive self-routing control algorithm to be described below Definition 1 the following Definition 9 provide a precise topological characterization of the cyclic Banyan network Definition 9: For each SE of the cyclic Banyan network, chain-out links of the SE s are connected, respectively, with the chain-in link of the SE the SE given by Fig 4 shows an example of a cyclic Banyan network configured from the general delta network The function the function map a given SE to another SE within the same stage B The Fully Adaptive Self-Routing Scheme As in many other MIN s, the routing of the cyclic Banyan network is controlled by means of destination tag In addition to the general destination tag, it also uses, for each cell, a deviation tag having a fixed size of binary digits The deviation tag is updated at each stage to represent the value of the topological distance between the SE that actually receives the cell the originally intended SE (or an SE equivalent to the originally intended SE) Here, the originally intended SE is that SE an a given stage that would have received the cell in accordance with the basic self-

6 PARK et al: DEFLECTION SELF-ROUTING BANYAN NETORK 593 Fig 3 The organization of the augmented switching element Fig 4 The cyclic Banyan network the fully adaptive self-routing scheme thereof (N =16) routing of the underlying Banyan network The value of is calculated with the current value of the selected link, the originally intended link Thus, the destination address of a cell in transit across the cyclic Banyan network comprises a pair ( ) When a cell arrives at the input link of stage 1, the value of is set to zero; ie, the cell have the destination address ( ) The fully adaptive self-routing algorithm set forth in Definition 10 determines thereafter how each of successive SE s transfers the cell updates the value of Definition 10: Let ( ) denotes the destination address for an input cell to be transferred across a cyclic Banyan network, let denote the routing control function for the Banyan network from which the cyclic Banyan network is configured Let denotes the binary complement of A fully adaptive self-routing control algorithm for the SE, in the cyclic Banyan network is defined by a link allocation procedure the updating rules as follows: I) Link-Allocation Procedure: For each input cell: 1) If then: a) send the cell to b) it fails, send the cell to c) it fails, send the cell to d) it fails, send the cell to

7 594 IEEE/ACM TRANSACTIONS ON NETWORKING, VOL 7, NO 4, AUGUST ) If then: a) send the cell to ; b) it fails, send the cell to ; c) it fails, send the cell to ; d) it fails, send the cell to II) The Updating Rules for : 1) When a) is selected, then set b) is selected, then set c) is selected, then set d) is selected, then set 2) When a) is selected, then set b) is selected, then set c) is selected, then set d) is selected, then set e) is selected, then set where mod otherwise otherwise The following, Theorem 5, shows that the routing scheme proposed is fully adaptive: for all SE s in the cyclic Banyan network, except for the SE s in the last stage, a cell can be routed to either the output links, or to the chain-out links, still be deliverable to a designated output port of the network Theorem 5: Let For each port of connected with or a valid path exists, in accordance with the selfrouting method of Definition 10, through the port from to a designated output port of the network Proof: From Corollary 5, it follows when a valid alternative path exists through the link connected with (where denotes the binary complement of ) Therefore, instead of the intended output link, another output link can be utilized as an alternate path to deliver input cell to the destined output port correctly Similarly, by Corollary 4, a valid alternative path exists through the chain-out links connected with or Conversely, a valid path exists through the chain-out link, the Theorem 4 provides that a valid path exists through We can now prove the correctness of our fully adaptive self-routing scheme for the cyclic Banyan network Theorem 6: The routing control procedure of Definition 10, as applied in the cyclic Banyan network, correctly delivers an input cell with an arbitrary destination tag to the indicated destination port Proof: The method first allocates an available link in accordance with the procedure of Part I Theorem 5 provides the existence of a valid path from that link to the destination port Second, the method updates the deviation tag in accordance with the rules of Part II The following shows that this updating rules actually causes the cell to proceed along a path to the destination port 1) The updating rules 1(a) 1(b) are proven by applying Corollary 5 The updating rules 1(c) 1(d) are proven by applying Corollary 4 2) The updating rules 2(a) 2(b) are proven by applying Corollary 5 Theorem 4 The updating rule 2(c) is proven by applying Theorem 4 3) represents the required number of additional adjustment routing steps through successive levels of the current stage, by means of the chain-out link(s), for the cell to proceed to the next stage on a path to the destination port Thus, the updating rule 2(d) is proven With this Corollary 2, the rule 2(e) is also proven Fig 4 illustrates fully adaptive routing control in the cyclic Banyan network in accordance with the method of Definition 10, where a cell collision or a fault is represented by the symbol X In one case, a cell tries to move from the input port (0000) to the output port (0000) As indicated in Fig 4, collisions/faults occur, the SE redirects the cell from the intended output link, now blocked by the collision or the fault, to another output link The cell then travels through the cyclic Banyan network along an alternate path in accordance with the routing control method of Definition 10 The second case is that a cell enters the network at the input port (1011) has the output port (1011) as its designated output port While the cell travels the network, it is faced with two congested/faulty links In response to these collisions/faults, each of the SE s redirects the cell in accordance to the routing control method as shown in Fig 4 The third case is that a cell enters the network at the input port (1110) has the output port (1110), is faced with three congested/faulty links IV PERFORMANCE ANALYSIS OF THE CYCLIC BANYAN NETWORK The performance enhancement of the cyclic Banyan network is accomplished by using the fully adaptive, deflection self-routing control utilizing all the links to make alternate paths In this section, we will analyze this performance enhancement of the cyclic Banyan network over several kinds of networks We will use a common queuing network model to investigate the performance of the cyclic Banyan network A The Cyclic Banyan Network Under Unorm Traffic We analyze the network under the unorm traffic model, thus we employ the following assumptions as usually done

8 PARK et al: DEFLECTION SELF-ROUTING BANYAN NETORK 595 Assumption 1: New cells arrive at input ports according to Poisson process with rate where Input cells are unormly distributed over all output ports Also, the probability that a cell arrives at network is the same for all input ports Each cell has equal probability to win the conflict These assumptions imply that, for each switching stage of the network, the pattern of cell distribution is identical statistically independent for all the SE s Therefore, each switching stage can be characterized by a single SE, this fact makes the analysis of the network very simple In many works [17], [18], for the performance analysis of the multipath switching network, the contention at the destination was ignored Such assumption was justied by using a fast output queue which could accept multiple requests per cycle, by employing the multiplexer in front of the queue For examples, to avoid the contention at the destination, the multiplexer operating at two times the speed of the networks the fast queue accepting two cells per cycle is generally used for the replication-2 Banyan, the 4 1 multiplexer operating at four times the speed of the networks the fast queue accepting four cells per cycle is used for the replication-4 Banyan For the replication-8 Banyan, the 8 1 multiplexer operating at eight times the speed of the networks the fast queue accepting eight cells per cycle is also used For the proposed switching network, we need the 4 1 multiplexer operating at four times the speed of the networks the fast queue accepting four cells per cycle Additionally we also need the 1 2 demultiplexer operating at the same speed of the networks for each output port the 1 3 demultiplexer operating at the same speed Therefore, we can also apply the following assumption for the performance analyses of the various kinds of the networks compared in this section Assumption 2: There is no contention at the output port of the network The cyclic Banyan network, using the deflection self-routing control proposed, does not utilizes the buffering mechanism the backpressure mechanism to deal with the output link contention within SE s Therefore, the cell arriving at the last stage having the value of deviation tag as nonzero is lost, unless there is available chain-out link Thus, we assume the following Assumption 3: The SE s in the last stage drop input cell, the value of deviation tag of the cell is nonzero chain-out link is not available For the performance analysis of the cyclic Banyan network, we will use a model that is similar to the queuing model of [19], which was used for analysis of the multicomputer network In this model, each packet was associated with a class or a type By associating a cell with a class as the case of the model, we will model the deflection self-routing in the cyclic Banyan network in terms of the performance We classy the cell as a class in accordance with the topological distance between the SE at which the cell actually arrives the originally intended SE (or an SE equivalent to the originally intended SE) Thus, we classy the cell in stage as one of classes, classy the cell of which such topological distance is zero as the class 0 The class associated with cell is being changed into other classes in accordance with the transfer of the cell from a SE to another SE in the same stage or the next stage The probability that the cell of a class changes into the cell of another class only depends on the probability that cell win competition against other cells within the SE We first define the following variables in the same manner as in [19], derive a set of state equations relating these variables The symbol is defined to represent the number of cells which were transferred from an SE of a certain stage to an SE of a certain stage at the same time become the cells of a new class Definition 11: The symbol is defined to represent the number of cells which transferred from the stage to the stage become the class We also define to present the total number of all cells in stage, which were in stage previously Definition 12: The total number of cells in stage, which were in stage previously, is denoted as the symbol defined by: Now let us define some abbreviations to simply the expression of the state equations presented later Definition 13: The symbol denotes the number of all input links of an SE, the symbol denotes the number of all chain-in links of an SE The total number of all the cells departing from SE s of the stage arriving at the input links of an SE of the stage except for the cells of class 0, is denoted by the symbol defined by The number of all cells departing from SE s of the stage arriving at the chain-in links of an SE of the same stage except for the cells of class 0, is denoted by the symbol defined by The symbol is defined to represent the transition probability with which the cell of a class changes into the cell of another class Definition 14: The symbol is defined to denote the transition probability that the cell of the class of the stage is changed into the class while delivered to an SE of the stage Using the symbol, we can easily illustrate the state transition diagram used in the proposed performance model as shown in Fig 5, where it is for the case of the cyclic Banyan network Each state is labeled with the pair of the stage number the topological distance between the SE at which the cell actually arrives the originally intended SE (or an SE equivalent to the originally intended SE) We can obtain the throughput of the cyclic Banyan network in steady state by using this kind of state diagram the state-transition probability which will be presented in the following Theorem 7: When the state transition is in steady state, the state transition probability that the cell of the class 0 of the first stage is changed into the class while it is delivered

9 596 IEEE/ACM TRANSACTIONS ON NETWORKING, VOL 7, NO 4, AUGUST 1999 Fig 5 The state transitions of cell switched through the cyclic Banyan network (N =16) to an SE of the second stage is given by class while it is delivered to an SE of the stage is given by The probability that the total cells arrive at input links from among input links of an SE in the first stage at given cell time is a binomial probability function The probability that at least one of cells of the class 0 within an SE of the first stage is changed into the class while it is delivered through the output link under consideration to SE s of the second stage, is given by the function that will be derived later Then the transition probability is the sum over all possible numbers of cells arriving the input links, of the product of these two probabilities For the stage ( 2), the state transition probability that the cell of the class of the stage is changed into the

10 PARK et al: DEFLECTION SELF-ROUTING BANYAN NETORK 597 where The joint probability that, from the stage cells of the class 0, cells of class cells of class arrive at input links from among input links of an SE in the stage at given cell time is a multinomial probability function consideration, to an SE of the same stage the function defined by is given by The joint probability that cells of the class 0, cells of class cells of class arrive at chain-in links from among chain-in links of an SE in the stage is a multinomial probability function Second, let us define the probability function for the case that the degree of the deflection is reduced by one level through the intrastage routing within the same stage We obtained these formulas based on [15] To simply the mathematical expressions for the probability function, we introduce the matrices in Definition 15 hereinafter Definition 15: Each of the matrix the matrix is defined, respectively, by where The probability that at least one from among cells of the class within an SE of the stage is changed into the class while it is delivered through the output link under consideration to SE of the stage is given by the function that will be also derived later Then the transition probability is the sum over all possible numbers of cells arriving the input links the chain-in links, of the product of these three probabilities Now let us derive the probability function To model the transformation of the class of input cell switched within SE s in accordance with the deflection self-routing control, we derive the formulas hereinafter based on [15] First let me define the probability function for the case that all the cells arriving at an SE is of class 0, ie, the case that in the following Lemma 2 Lemma 2: The probability that at least one from among all the input cells of the class 0 which are in an SE of the stage is still those of the class 0, while it is delivered through the output link under consideration, to an SE of the next stage is given by the function defined by Additionally, let us define three operation symbols for matrices as the following First the symbol denotes a multiplication of two matrices analogous to the scalar product of vectors Also, the symbol denotes a multiplication of two matrices analogous to the Cartesian product of vectors The probability that at least one from among all the input cells of the class 0 within an SE of the stage become of the class 1, while it is delivered through the output link under consideration, to an SE of the next stage is given by the function defined by The probability that at least one from among all the input cells of the class 0 within an SE of the stage become of the class 1, while it is delivered through the chain-out link under Lastly, the symbols denotes an evaluation of a matrix analogous to the summation of the components of vector as

11 598 IEEE/ACM TRANSACTIONS ON NETWORKING, VOL 7, NO 4, AUGUST 1999 the following: link under consideration, to an SE of the same stage given by the function defined by is Using two matrices three operators defined above, we can simply define the transition probability function as Lemma 3 Lemma 3: The probability function that at least one from among all the input cells of the class within an SE of the stage become of the class while it is delivered through the chain-out link under consideration is defined by The probability that at least one from among all the input cells of the class within an SE of the stage become of the class while it is delivered through the output link under consideration, to an SE of the next stage is given by the function defined by where The probability that at least one from among all the input cells of the class within an SE of the stage become of the class while it is delivered through the output link under consideration, to an SE of the next stage is given by the function defined by Algorithm: Due to the complexity of the state transitions, we measure the performance of the network by iterative calculations Each step of the iteration starts from the first stage ends at the last stage These steps are repeated until the steady state is reached The normalized throughput is obtained by dividing the number of accepted cells by the maximum number of possible arrivals where Finally, we present the probability functions of the case that the degree of the deflection is increased by losing the competition for the routing Lemma 4: The probability that at least one from among all the input cells of the class within an SE of the stage become of the class while it is delivered through the chain-out The normalized delay is obtained by dividing the summation of the total number of the delays for the interstage routings the total number of the expected delays for the intrastage routings by the number of the stages of the network Simulation: In order to validate the analysis presented in the previous section, we did some simulations of the cyclic Banyan networks The basic assumptions for the analysis were implemented in the simulator as follows The sources generate cells according to Poisson process with rate where The destination of each cell generated by sources is set romly by a rom number generator (one out of zero to ) to simulate unorm traffic

12 PARK et al: DEFLECTION SELF-ROUTING BANYAN NETORK 599 Fig 6 Normalized throughput versus network size for the cyclic Banyan network Fig 7 Normalized delay versus network size for the cyclic Banyan network If there is a conflict among cells for a link, one cell selected romly is transferred to the link, other cells are deflected to other links The throughput the delay are measured at each output port of the network, averaged over the network size simulation time span to get the normalized throughput the normalized delay of the network The sample simulation results the analytic results are shown in Figs 6 7 Fig 6 shows normalized throughput versus network size for the cyclic Banyan network with the input load of 10 The notable fact found out from Fig 6 is that the normalized throughput starts to degrade when the size reaches It is because the number of the crosspoints ( ) of the cyclic Banyan network starts to be less than that ( ) of the crossbar, ie, the complete connection, from the size Fig 7 plots normalized delay versus network size for the same network with the input load of 10 There are dferences between the analytic results simulation results, since the analytic analysis is approximated based on several unormity independence assumptions These approximations assumptions make the analysis simple, easy to underst, easy to compute the results Comparing the performance of the cyclic Banyan network with that of the generic Banyan network the replicated Banyan networks, we now investigate the performance improvement of the cyclic Banyan network as the following For fair comparison among the networks, first let us investigate the hardware cost of the networks We assume the hardware cost is proportional to the number of gates involved Hence, the hardware cost of the generic Banyan network is ( SE s) (number of gates per SE), that of the Replicated-2 Banyan network is ( SE s) (number of gates per SE) (2 Replication), that of the cyclic Banyan network is ( SE s) (number of gates per SE), that of the B-network is ( SE s) (number of gates per SE), that of the Replicated-4 Banyan network is ( SE s) (number of gates per SE) (4 Replication) that of the Replicated-8 Banyan network is ( SE s) (number of gates per SE) (8 Replication) So we can normalize these expressions for the hardware costs of the networks through dividing each of these expressions by ( ) that is the number of all the SE s of the generic Banyan network These normalized hardware cost means the number of the gates that are needed to construct the function corresponding to one SE of the generic Banyan network The normalized hardware costs for the generic Banyan network, the Replicated-2 Banyan network, the cyclic Banyan network, the B-network, the Replicated-4 Banyan network, the Replicated-8 Banyan network are (number of gates per SE), (number of gates per SE 2), (number of gates per SE), (number of gates per SE) 2, (number of gates per SE 4), (number of gates per SE 8), respectively The detail values of the normalized hardware cost for the networks, of which the size are shown in Table I To evaluate the number of the gates for one switching unit, we use the following assumptions We assume that we need one gates for a NAND logic, three gates for an exclusive-or logic, seven gates for a flip-flop We also assume that each switching unit is composed of input cell buffers, output cell latches, a complete interconnection by which we can transfer cells from the input cell buffers to the output cell latches, which is composed of flip-flop s, an input selection function, an output selection function, typical contention control function The input cell buffer is composed of 512 flip-flop s for storing 64 bytes The output cell latch is composed of 16 flipflop s for storing 2 bytes The number of the flip-flop s for the complete interconnection is evaluated by the expression: (the number of the input cell buffers) (the number of the output cell latches) (2-bytes bwidth) It is notable that we need a few additional gates for processing updating of the deviation tag controlling of the contention in accordance with the routing scheme defined in Definition 10, the number of the additional gates for the deviation

13 600 IEEE/ACM TRANSACTIONS ON NETWORKING, VOL 7, NO 4, AUGUST 1999 TABLE I NORMALIZED HARDWARE COMPLEXITY (NUMBER OF GATES) FOR THE BANYAN, REPLICATED BANYANS, B-NETWORK, AND CYCLIC BANYAN (N = 1024) Fig 8 Normalized throughput versus network size for Banyan, replicated Banyans, B-network, cyclic Banyan tag is proportional to scale for the case of the network Being irrelative to the size of the network, the number of the gates for the switching unit is almost invariable Therefore all the normalized hardware costs of the networks of various sizes are almost same with that of the network According to Table I, to construct the cyclic Banyan network, we need about 20% more gates than the case of the replicated-2 Banyan network The hardware cost of the cyclic Banyan is 12 times that of the replicated-2 Banyan network, 08 times that of the B-network, 06 times that of the replicated- 4 Banyan network, 03 times that of the replicated-8 Banyan network As shown in Fig 8, the throughput of cyclic Banyan network is 351 times that of the regular Banyan network, 215 times that of the replicated-2 Banyan network, 151 times that of the replicated-4 Banyan network, even 120 times that of the replicated-8 Banyan network The normalized delays for the proposed networks of all sizes are only about 17 times that of the generic Banyan networks of all sizes, respectively, as shown in Fig 7 Furthermore, as shown in Fig 9, we reduce load, or speed up the proposed network, we can get the network of which throughput is almost 10 As the size of networks is larger, the performance of the cyclic Banyan network is better than the replicated Banyan networks The throughput of cyclic Banyan Fig 9 Normalized throughput versus network size for the cyclic Banyan network under several load factors network is 476 times that of the regular Banyan network, 269 times that of the replicated-2 Banyan network, 170 times that of the replicated-4 Banyan network, even 122 times that of the replicated-8 Banyan network We can see that an extreme large-sized proposed network has far better performance than the replicated Banyan networks So the cyclic Banyan network has far better scalability so that it can be used for large-scale ATM systems in which the replicated network cannot be employed B The Cyclic Banyan Network Under Nonunorm Traffic We analyze the cyclic Banyan network under nonunorm traffic For the performance analyses, we did simulations We employ the same assumptions of analysis under unorm traffic except Assumption 1 We can represent a nonunorm traffic as a load matrix where element means the given probability that a cell arriving at input port would be destined for output port Thus, the sum of row of the matrix represents the total load on input port the sum of column represents the total load offered to output port There can be infinitely many nonunorm traffic patterns Of these patterns we are interested in a nonunorm traffic pattern, hot-group model [2], which may represent a realistic traffic patterns We assume that input cells are nonunormly distributed over all output ports in such a way that the output

14 PARK et al: DEFLECTION SELF-ROUTING BANYAN NETORK 601 Fig 10 Normalized throughput versus congested stage of cyclic Banyan network under nonunorm traffic ports can be divided into two groups named hot outlet group cold outlet group The load matrix is partitioned as The row sum of is while the row sum of is such that In other words, there are two equal-sized outlets groups, the probability of a cell originating at a source going to destination group is, while going to destination group is Let is hot ratio, then, Using this model under various input loads s hot ratios s, we did simulation hereinafter The notable fact that we found out from the results of simulation is that the performance of the Cyclic Banyan network under nonunorm traffic is independent of the location of congested stage From Fig 10, we can very this fact If the size of two outlet groups is equal, whatever nonunorm traffic pattern we apply, the result of simulation to estimate throughput is the same for an input condition So we can estimate the whole performance under nonunorm traffic pattern with only two factors: input load hot ratio Now we investigate the performance of the cyclic Banyan network under nonunorm traffic As shown in Fig 11, when we put load into the cyclic Banyan network, the hot ratio is 06, the throughput of network is degraded by only 0022% If the hot ratio is 07, the throughput of the network is degraded by 2871% Even the hot ratio is 08, the throughput of the network is degraded by 12321% When we put load into the cyclic Banyan network, the hot ratio is 06, the throughput of network is degraded by 1668% If the hot ratio is 07, the throughput of the network is degraded by 11230% When we put load into the cyclic Banyan network, the hot ratio is 06, the throughput of network is degraded by 6840% If the hot ratio is 07, the throughput of the network is degraded by 17502% We also could see the throughput of proposed network is 099 even when we applied load hot ratio to the network as shown in Fig 11 In this case, the throughput is only 0666% less than that under unorm traffic Fig 11 Normalized throughput versus network size for the cyclic Banyan network under nonunorm traffic Fig 12 Logical structure of the cell resequencing buffer C Cell Sequence Integrity The cells having the identical source the identical destination with each others can reach the same output port out of sequence since they can be transferred through dferent paths in the cyclic Banyan network The cells transferred through dferent paths may have various delay time corresponding to the paths Through the equalization of the network delay encountered by cells, we can eliminate the cell sequence integrity problem We introduce a cell resequencing buffer with which each output port of the network is equipped Radically, this cell resequencing buffer is a memory buffer with rom read write, in which the cells are held before delivery, as shown in Fig 12 The detail design of the cell resequencing buffer will be presented in the Appendix From the simulation results shown in Fig 13, we can see that the delay time of the cells transferring through the cyclic Banyan network is less than 100 cell time for almost all proper combinations of the input loads rates the hot rates Furthermore Fig 14 shows that the delay time encountered by the cell traveling through the switching networks of various sizes, of which the size are less than , is also less than 100 cell times, even under the heavy load hot rate pairs As a result, for the case of employing the cyclic Banyan network as the multipath switching network, we can provide an effective cell resequencing buffer using small size resequencing window, whereas the resequencing window is the number of the equalization slots, ie, the minimum number of

15 602 IEEE/ACM TRANSACTIONS ON NETWORKING, VOL 7, NO 4, AUGUST 1999 Fig 13 Fig 14 Delay distribution for various input load hot ratio Delay distribution for various network size time slots that a cell must wait before leaving the network So we can construct the cell resequencing buffer with such small quantities of hardware as shown in Fig 15 presented in the Appendix It is notable that the total delay time of the cells transferred through the cyclic Banyan network then through the resequencing buffer is 100 cell time, the delay variation of the cells is 0 cell time V CONCLUDING REMARKS In this paper, we have designed evaluated a new high-performance, large-scale ATM switch, ie, the cyclic Banyan network that is a class of the deflection self-routing Banyan network It is a new augmented Banyan network using fully adaptive self-routing control that exploits all links as alternate paths By adding extra links between SE s within the same stage extending the self-routing scheme, we present the network using all links as alternate paths Although the proposed network has no internal buffer, it never loses cell within the switching network To design the proposed network its self-routing, we use the topological properties: all SE s of the Banyan network are arranged in a regular pattern in terms of topology In other words, each stage of the Banyan network is composed of sequence of the cyclic group realized with SE s, stages also connected symmetrically through the links between them We proved such properties of the Banyan networks through an algebraic formalism in this paper The proposed routing scheme is a fully distributed routing scheme that requires a little additional computation in each SE The computation is increment/decrement function sht function for a fixed sized oper ( bits) The proposed self-routing is as simple as that of the Banyan network, all SE s of proposed network have a unorm structure We also provide performance analyses under unorm traffic pattern nonunorm one for a quantitative comparison As a result of the analysis of the networks under unorm traffic, we have found that the throughput of cyclic Banyan network is 351 times that of the regular Banyan network, 215 times that of the replicated-2 Banyan network, 151 times that of the replicated-4 Banyan network, even 120 times that of the replicated-8 Banyan network, whereas the hardware complexity of the network is 12 times that of the replicated-2 Banyan network All the normalized delays of the proposed networks of all sizes are only about 17 times that of the generic Banyan network of all sizes, respectively As the size of networks is larger, the performance of the cyclic Banyan network is very better than the replicated Banyan networks As a result of analysis of the networks under nonunorm traffic, we provided quantitative comparison among the proposed network under unorm traffic that under nonunorm traffic having several load hot ratio pairs as parameters When we put load 07 into the cyclic Banyan network, the hot ratio is 06, the throughput of network is degraded by only 0022% If the hot ratio is 07, the throughput of the network is degraded by 2871% Even the hot ratio is 08, the throughput of the network is degraded by 12321% When we put load 08 into the cyclic Banyan network, the hot ratio is 06, the throughput of network is degraded by 1668% If the hot ratio is 07, the throughput of the network is degraded by 11230% When we put load 09 into the cyclic Banyan network, the hot ratio is 06, the throughput of network is degraded by 6840% If the hot ratio is 07, the throughput of the network is degraded by 17502% We also present a simple cell resequencing buffer providing a hardware sliding window mechanism so that the proposed network can preserve the sequence integrity of cells that tour various paths then arrive at a output port The simple control mechanism is possible because the cell delay variation of the proposed network is bound by the limit of 100 cell time, as shown in the results of the simulations As a result, we presented the switching network of which the cell delay time is 100 cell time the cell delay variation is 0 cell time We introduced only a new network, using the topological properties found, we can, of course, provide many extensions of the Banyan network using the deflection self-routing We

16 PARK et al: DEFLECTION SELF-ROUTING BANYAN NETORK 603 Fig 15 The detail design of the cell resequencing buffer have also consider only the Banyan network built out of 4 4 SE s; however, this scheme can also be applied to networks composed of lager SE s, eg, 8 8 SE s APPENDIX DETAIL DESIGN OF THE CELL RESEQUENCING BUFFER In this appendix, we present a cell resequencing buffer, as shown in Fig 15 The cell resequencing buffer is composed of the cell buffer memory, in which the real cells are stored, the set of the buckets which is used to maintain the linked lists of the addresses of the cells stored in the cell buffer memory, the waiting pool of idle addresses of the cell buffer memory, the cell input functions, which calculate the number of the time slots by which a cell must wait before leaving the network select an input bucket, then link the address obtained from the waiting pool to the linked list of the bucket store the cell, the cell output functions, which select the bucket from which the address of output cell is fetched, then fetch the address deliver the cell Now we investigate the function of the cell resequencing buffer by reviewing the behavior of the resequencing buffer For the operation, first the maximum delay register is initialized with the value of maximum delay estimated, the base bucket address increment register the output bucket address increment register is initialized with zeros, respectively On the other h, according to the cell time clock, input cell is stored in the cell buffer memory at rising edge, output cell is fetched from the cell buffer memory is given to output at falling edge By the way to use this cell resequencing buffer, we need to extend internal cell format for seven bits In this field, the total delay time of the cell transited the network will be stored The total delay time of the cell passing the network is calculated by increasing by one for each time when the cell transit a link between SE s, then is updated in the header of the cell before transiting When the cell arrive at the cell resequencing buffer out of the SE of the final stage, the select input bucket calculates the address of the bucket to which the cell belong as the following: the value of the maximum delay register minus the value of the delay time of the cell header plus the value of the base bucket address increment register The result value is the address of the bucket in which the linked list of the addresses of the cells for the bucket is maintained By the way, the address where the real cell arrived will be stored is obtained from the idle addresses pool Then the cell is stored in the cell buffer memory, the address is linked to the list that is maintained by the selected bucket On the output side, at each cell time, a cell is delivered to output as the following The address of the bucket maintaining the linked list, to which the address of the appropriate output cell belong, is obtained from the output bucket address increment register At the falling edge of the cell time clock, the address fetched from the linked list is sent to the memory address register, then the cell stored in this location within the cell buffer memory is sent to output As a result, the delay times of all the cells are equalized to a certain delay time, so we can guarantee the integrity of cell sequence REFERENCES [1] CCITT, Broadb aspects of ISDN, CCITT Recommendation I121, Blue Book, Geneva, Switzerl, 1989, vol III7 [2] S Gianatti A Pattavina, Performance analysis of shared-buffered Banyan networks under arbitrary traffic patterns, in Proc INFO- COM 93, pp

17 604 IEEE/ACM TRANSACTIONS ON NETWORKING, VOL 7, NO 4, AUGUST 1999 [3] R Rooholamini M Garver, Finding the right ATM switch for the market, IEEE Comput, vol 27, pp 16 28, Apr 1994 [4] E P Pathgeb, W Fischer, C Hinterberger, E Wallmeier, R Wille- Fier, The main street Xpress core services node A versatile ATM switch architecture for the full service network, IEEE J Select Areas Commun, vol 15, pp , June 1997 [5] W Willinger, M S Taqqu, R Sherman, D V Wilson, Selfsimilarity through high-variability: Statistical analysis of ethernet LAN traffic at the source level, IEEE/ACM Trans Networking, vol 5, pp 71 86, Feb 1997 [6] B Tsybakov N D Georganas, On self-similar traffic in ATM queues: Definitions, overflow probability bound, cell delay distribution, IEEE/ACM Trans Networking, vol 5, pp , June 1997 [7] P T Gaughan S Yalamanchili, Adaptive routing protocols for hypercube interconnection networks, IEEE Comput, vol 26, pp 12 24, May 1993 [8] E Ayanoǧlu, Signal flow graphs for path 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Comput, vol C-30, pp , Oct 1981 [16] J-H Park, H Yoon, H-K Lee, The cyclic Banyan network: A fault-tolerant multistage interconnection network with the fullyadaptive self-routing, in Proc 7th IEEE Symp Parallel Distributed Processing, TX, Oct 1995, pp [17] R Venkatesan H T Mouftah, Balanced gamma network A new cidate for broadb packet switch architectures, in Proc IEEE INFOCOM 92, pp [18] T D Morris E F Gehringer, A cost-effective reliable multipath interconnection network, ACM Comput Architecture News, pp 45 65, June 1991 [19] M Harchol P E Black, Queuing theory analysis of greedy routing on arrays tori, Dept Elect Eng Comput Sci, Univ Calornia, Berkeley, CA 94720, Tech Rep UCB/CSD 93/756, June 1993 Hyunsoo Yoon received the BS degree in electronics engineering from the Seoul National University, Seoul, Korea, in 1979, the MS degree in computer science from Korea Advanced Institute of Science Technology, Taejon, in 1981, the PhD degree in computer information science from The Ohio State University, Columbus, in 1988 During , he was with the Tongyang Broadcasting Company, Korea, then Samsung Electronics Company, Seoul, Korea, during From 1988 to 1989, he was a Member of the Technical Staff with AT&T Bell Labs, Indial Hill, IL Since 1989, he has been a Professor with the Department of Computer Science, Korea Advanced Institute of Science Technology His main research interests include parallel computer architectures, parallel computing, interconnection networks, high speed communication networks Heung-Kyu Lee received the BS degree in electronics engineering from the Seoul National University, Seoul, Korea, in 1978, the MS PhD degrees in computer science from the Korea Advanced Institute of Science Technology, Taejon, Korea, in , respectively From 1984 to 1985, he was a a Post-Doctoral Fellow at the University of Michigan, Ann Arbor Since 1986, he has been a Professor in the Department of Computer Science, Korea Adanced Institute of Science Technology Since 1990, he has also been a Research Staff Member at the Satellite Technology Research Center, Korea Advanced Institute of Science Technology His major interests are real-time fault-tolerant computing, multimedia systems, satellite remote sensing Jae-Hyun Park (S 91 M 96) received the BS degree in computer science from Chung-Ang University, Korea, in 1988, the MS PhD degrees in computer science from the Korea Advanced Institute of Science Technology, Taejon, in , respectively Since 1995, he has been a Senior Engineer with Samsung Electronics Company, Korea His main research interests include interconnection networks, ATM switching architectures, multiprotocol label switching, parallel computing, distributed/parallel operating system, hard real-time operating systems He received the 1996 Best Research Paper Award-Golden Prize in 1997, the 1997 Best Research Paper Award-Bronze Prize in 1998, the 1997 Award of Excellence in Research Development-Silver Prize in 1998, all from Samsung Electronics Company His biographical profile was included in the 1998 Who s Who in the World (New Providence, NJ: Marquis Who s Who, 1998)