Introduction to ATM Technology

Transcription

1 Introduction to ATM Technology ATM Switch Design Switching network (N x N) Switching network (N x N) SP CP SP CP

2 Presentation Outline Generic Switch Architecture Specific examples Shared Buffer Switch Shared Medium Switch Space Division Switches Sunshine Switch Knockout Switch Conclusions Semester Advanced Telecommunications Slide 2

3 Objectives To demonstrate the factors influencing the design of high speed switching systems. To develop an understanding of the various advantages and disadvantages associated with modern ATM switch design. Semester Advanced Telecommunications Slide 3

4 Generic ATM Switch Architecture - 1 The basic components of an ATM switch are: Line interfaces () Call processor (CP) Signal processor (SP) A switching network Performs optical to electrical conversion and cell synchronisation CP and SP Perform functions concerned with ATM setup and release. The CP and SP can be connected in two different ways. (See next slide.) In front signal processing, signalling packets are transferred through a separate bus to the CP and SP. In rear signal processing, the signalling and control is handled in a unified manner with the user traffic. Hardware is thus simplified compared with front signal processing. Switching network Handles the packets after processing. Semester Advanced Telecommunications Slide 4

5 Generic ATM Switch Architecture - 2 Switching network (N x N) Switching network (N x N) SP CP SP CP Front signal processing Rear signal processing ATM Switch ATM Switch Semester Advanced Telecommunications Slide 5

6 Classification of ATM Switches Designers have developed a large number of different ATM switches. Broadly speaking, they can be classified according to work done by Tobagi in 1990 as: Shared Buffer Switch Shared Medium Switch Space Division Switch Each of the above types will be briefly reviewed in subsequent slides. Semester Advanced Telecommunications Slide 6

7 Shared Buffer Switch - 1 Main features are: Single buffer memory is shared by all input and output lines - as shown in the next slide. Packets arriving at the input lines are multiplexed into a single stream and sent to the shared memory according to their destination addresses. The output stream is created by retrieving packets in the output queues in a sequential manner. Output stream is then demultiplexed to distribute the packets to the individual output lines. High speed controllers and memories. Semester Advanced Telecommunications Slide 7

8 Shared Buffer Switch MUX Shared Buffer Memory DMUX 1 N N Memory Controller Basic structure of a shared buffer switch Semester Advanced Telecommunications Slide 8

9 Shared Buffer Switch - 3 Advantages: Efficient buffer utilisation Easy accommodation of point-to-multipoint services Priority control based buffer management Disadvantages: Switch size will be limited by speed of the controllers and memory. Difficulties in extending to large network switches. Semester Advanced Telecommunications Slide 9

10 Shared Medium Switch - 1 Main features: All packets arriving at the input lines are synchronously multiplexed onto a common high speed medium of bandwidth equal to N times the rate of a single input line. Each output line is connected to the bus via an interface that consists of an address filter (AF) and an output queue that operates as First-In-First-Out (FIFO). The Afs determine whether or not the packet observed in the bus is to be written to the FIFO queue. Advantage: Point to multipoint services easily accommodated. Disadvantage: Since independent queues are used at the output lines, we see that buffer utilisation is not efficient. Semester Advanced Telecommunications Slide 10

11 Shared Medium Switch - 2 S/P AF FIFO P/S Time division bus S/P AF FIFO P/S S/P AF FIFO P/S Basic structure of a shared medium switch Semester Advanced Telecommunications Slide 11

12 Space Division Switches - 1 These switches provide a path from the input line to the output line in a space division fashion in a similar manner to that performed by conventional circuit switched networks. Advantage: In this type of switch, we find that it is possible to set up several different paths simultaneously. Contrast this with the previous two approaches where paths are set up sequentially in a time division fashion. This difference means that these switches can operate at lower speeds than the others mentioned above. Disadvantage: It is conceivable that not all packets can be transmitted to their desired destination due to conflicts caused by resource limitations. (Analogously to their circuit switched counterparts!) The designs that have been developed set out to overcome this important limitation. Semester Advanced Telecommunications Slide 12

13 Space Division Switches - 2 Space Division Switches can be classified into at least four different categories depending upon how the buffers are arranged, viz: Input Buffer Switch Output Buffer Switch Input/Output Buffer Switch Internal Buffer Switch In addition, we can further subdivide these switches into two categories: Blocking Non-blocking As expected, non blocking switches are better but harder and more expensive to design. Semester Advanced Telecommunications Slide 13

14 Multistage Interconnection Network Multistage networks are commonplace in circuit switched networks. Their objective is to minimise internal congestion and provide internal path diversity. In space division ATM switches the same objective is valid. The Multistage Interconnection Network (MIN) structure consists of multiple stages of simple 2 x 2 switching elements that perform specified permutation function patterns. The names of the MIN structures differ according to the interconnection pattern between the stages. Examples of such MIN structures are known as: Banyan networks Baseline networks Shuffle-exchange networks Flip networks Note that although there are differences in the patterns for interconnection, they don t necessarily lead to differences in performance. Semester Advanced Telecommunications Slide 14

15 Example Space Division Switches - 1 Interconnection pattern for a Banyan Network Semester Advanced Telecommunications Slide 15

16 Example Space Division Switches - 2 Interconnection pattern for a Baseline Network Semester Advanced Telecommunications Slide 16

17 Example Space Division Switches - 3 Interconnection pattern for a Shuffle Exchange (OMEGA) Network Semester Advanced Telecommunications Slide 17

18 Example Space Division Switches - 4 Interconnection pattern for a Flip Network Semester Advanced Telecommunications Slide 18

19 Routing in a Space Division Switch ATM cell You try! ATM cell Routing in an 8x8 Baseline network Semester Advanced Telecommunications Slide 19

20 Batcher-Banyan Network - 1 The Batcher-Banyan network is an example of a nonblocking network that retains the capability of selfrouting whilst overcoming the internal blocking drawback of a simple Banyan network. This network can avoid internal blocking by sorting the incoming packets based on their destination addresses first, and then routing them through the Banyan network. This network requires N 2 log 1 N 2 ( 1+ log ) N network elements Semester Advanced Telecommunications Slide 20

21 Batcher-Banyan Network - 2 2x2 Sorter 4x4 Sorter 8x8 Sorter Batcher sorting network Banyan network Key: a b Min(a,b) Max(a,b) a b Max(a,b) Min(a,b) Semester Advanced Telecommunications Slide 21

22 Input Buffer Switch In these switches, a nonblocking switching network is used as the switching network and a dedicated buffer is allocated for each input port. The switching network can only transfer one packet to each output port in each time slot, so an arbitrator is required to avoid packet conflicts that can occur in the switching network. As a result of so called Head of Line blocking throughput can be limited under certain conditions. A method for overcoming HOL blocking is to use a ring reservation scheme - this is actually a token ring scheme. Semester Advanced Telecommunications Slide 22

23 Structure of Input Buffer Switch Token generator Controller Controller Non-blocking switching network Controller Controller Non-blocking switching network Controller Arbitrator Controller Input buffer switch with an arbitrator Ring reservation scheme Semester Advanced Telecommunications Slide 23

24 Output Buffer Switch If incoming packets are uniform with input load rate p and if each output port can have L packets simultaneously, then the loss probability for packets is given by [Hluchyj88]: If P Loss = 10-6, then the required value of L=8. This allows us to construct an ATM switch with L=8 with dedicated buffers on each output port. The following slide shows the basic structure of this switch. Specific examples of output buffer switches include Sunshine switch Knockout switch N 1 p p PLoss = ( k L) 1 p k= L+ 1 N N Semester Advanced Telecommunications Slide 24 k N k

25 Structure of Output Buffer Switch Interface module Interconnection Interconnection fabric fabric Interface module Semester Advanced Telecommunications Slide 25

26 Knockout Switch - 1 In this network, N inputs form N buses that are directly connected to each of the N interface modules. Advantages: Good modularity Broadcast and multicast capabilities The interface module: Packet filter Examines addresses of each packet on each bus and filters them, removing any addressed to itself. Concentrator Concentrates packets down to L output lines Shared buffer Secures FIFO buffers equivalent to a single queue of L inputs and one output for each interface module to store the concentrator output packets. Disadvantage: Difficult to implement large size knockout switches due to large fan outs with each bus. Semester Advanced Telecommunications Slide 26

27 Knockout Switch N Interface Module Interface Module Interface Module 1 2 N Semester Advanced Telecommunications Slide 27

28 Sunshine Switch - 1 A Batcher network and L Banyan networks are used as the interconnection fabric. All incoming packets are first sorted by the front-end Batcher network according to their destination addresses. They are then transferred to their output port via L parallel Banyan networks simultaneously. Disadvantage: If more than L packets are destined for the same output port then the number of packets exceeding this total are transferred to a delay circuit to rejoin the sorting operation at the next time slot. Semester Advanced Telecommunications Slide 28

29 Sunshine Switch - 2 T Delay Circuit T Banyan 1 OPC 1 IPC 1 IPC 2 Batcher sorting network N+T Trap network N+T Concentrator N+T Selector Banyan 2 OPC 2 IPC N Key: IPC - Input Port Controller Banyan L OPC N OPC - Output Port Controller Semester Advanced Telecommunications Slide 29

30 Point to Multipoint Services Copy network TNT TNT TNT Point to point switching network TNT = Trunk number translator To provide these services, it is necessary to take into account the architecture of the switch. Some switches can easily accommodate the requirement, while others require modification. The switches based on banyan networks require a packet replication capability as illustrated above. Semester Advanced Telecommunications Slide 30

31 Conclusions ATM switches will be required to handle many tens of thousands of high speed ports in future networks. Most of the architectures discussed in this presentation are not easily scaled up to cope with this size. New switches are under development. In the meantime, a popular method for designing a large scale system has been to interconnect many small switch modules so that the overall system can meet the switching requirements. Semester Advanced Telecommunications Slide 31