A Proposal for a High Speed Multicast Switch Fabric Design

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1 A Proposal for a High Speed Multicast Switch Fabric Design Cheng Li, R.Venkatesan and H.M.Heys Faculty of Engineering and Applied Science Memorial University of Newfoundland St. John s, NF, Canada AB X {licheng, venky, ABSTRACT Multicasting is the ability to provide point-to-multipoint connections. Driven by the Internet and its applications, multicasting is becoming an important feature for any switching networks designed to support broadband integrated service digital networks (B-ISDN). High-speed packet switches (also known as broadband packet switches) are the core network components for transporting and switching users traffic in B-ISDN. In this paper, we discuss the feasibility of building a broadband multicast packet switch based on the packet switch category. Two different ways to build a multicast switch based on a multistage interconnection network (MIN) design are studied and compared. Design proposals to turn a high-performance unicast packet switch based on the Balanced Gamma network into a multicast switch are provided. Some design features like a distributed routing and cell splitting algorithm and a dynamic-length backpressure algorithm are discussed and analyzed in detail. Key words: Broadband packet switch, Multicasting, Copy network, Routing network, Multistage Interconnection Network. INTRODUCTION Multicasting is the ability to provide point-to-multipoint connections. Driven by the Internet and its applications, such as video on demand (VOD), music on demand (MOD), teleconferencing, videoconferencing and distributed data processing, more and more communication services and applications will require that information from a source be delivered to multiple destinations. Multicasting will become an important feature for any switching network designed to support broadband integrated service digital networks (B-ISDN). Generally speaking, packet switch architectures can be divided into three major categories []: the shared memory packet switch, the shared medium packet switch and the space division packet switch. Theoretically, each of these three architecture types can be modified to support multicast. However, in shared memory and shared medium architectures, there is a scalability problem as the need for a high-speed memory or bus greatly limits their use when the switch size grows large. Space division based switch architectures can usually be built using small building blocks known as switch elements (SEs). Interconnection of these small SEs will form a larger switch. Space division architectures can be further divided into two sub-classes: single stage interconnection network (SIN) and multistage interconnection network (MIN). Scalability is easier to achieve using this kind of design. The benefits of easy system design and simple hardware fabrication make the space division switch architecture a strong candidate for the B-ISDN switch fabric design. In this paper, we focus on the design of a multicast switch fabric based on a MIN architecture called the Balanced Gamma network. The remaining paper is organized as follows. In Section, we will briefly discuss and compare the two common approaches to turn an existing unicast switch fabric into a multicast switch. Section will present a design proposal for a Balanced Gamma multicast switch fabric. In particular, we will concentrate on the cell routing and splitting algorithm and dynamic-length backpressure algorithm when discussing the design. Finally, we summarize the paper in Section.. MULTICAST SWITCH FABRIC BASED ON MIN DESIGN We can build a multicast switch fabric using MIN design by either placing a copy network at the front of the routing network or integrating the cell replication function into the switch element. The intuitively obvious approach is to employ a copy network in tandem with a point-to-point routing network [,,,,]. The copy network replicates the incoming cell according to the fanout number specified in the header. The routing network uses the output of the copy network as its input and routes each of the copies to its destination. Many of proposed multicast networks follow this approach, including Lee s multicast switch [] and Turner s broadcast packet switch []. Lee s multicast switch is the most commonly referred to design in this

2 approach. However, it suffers from two problems. One is overflow, i.e., the total requested number of copies exceeds the available number of output ports of the copy network. In this situation, any cell whose fanout is larger than the remaining free output ports will be dropped []. This will eventually decrease system performance and throughput. The other is the output port conflict problem in the routing network when multiple packets request the same output port concurrently. Besides these two problems, the memory size of the TNT (Trunk Number Translation) tables will increase significantly as the fan-out and the switch size increase. Though some modifications are proposed to improve the design [,], they only mitigate the situation. At the same time, they increased the design complexity. The other solution is to build a multicast switch without a dedicated copy network. For this solution, the cell replication function is integrated into the switch elements, which are performing only the routing function in an unicast switch. Therefore, the function of a switch element should be enhanced to accommodate both the routing decision and cell replicating decision. This kind of design will inherit most of the important features of the MIN design and can efficiently turn a high performance unicast packet switch, such as the Balanced Gamma network, into a multicast switch fabric.. DESIGN OF BALANCED GAMMA MULTICAST SWITCH FABRIC. BALANCED GAMMA NETWORK The Balanced Gamma (BG) network is a multi-path MIN that has a similar structure to the Kappa network [,8]. For the BG network, the to concentrator in each output port of the Kappa network is replaced by a buffer which is capable of receiving up to cells in one clock cycle. An N N BG network consists of n+ stages, where n = log N. The first stage has N SEs. Each of the following n- stages has N SEs. The last stage is the buffer stage [,8]. All previous work has proved that the performance of BG network is superior to that of other networks of the same or comparable hardware complexity [,8]. Hence, it is reasonable to think that with the integration of the multicast function into the BG network, it will achieve a good performance.. DISTRIBUTED ROUTING AND CELL SPLITTING ALGORITHM In a multicast switch, an incoming master cell may have several output port requests. Therefore, a switch element, besides the routing decision, also needs to make the cell splitting decision. Generally speaking, the optimum way to do cell duplication is to do the splitting work only when necessary, i.e., splitting the cell as far from the input port as possible. How to design an appropriate and efficient routing and splitting algorithm is a big challenge for the multicast switch design. An important reason for the unicast Balanced Gamma switch fabric to achieve high performance is its distributed space-division architecture design. When considering the design of a multicast BG network, besides the distributed self-routing, we prefer that cell splitting can be implemented in a distributed manner and can fit well with the Balanced Gamma network architecture. Moreover, it is desirable that the switch element can complete the routing and splitting simultaneously instead of performing the routing and splitting job separately. In order to do the splitting, more tag information must be included in the cell header. In our research, we found that two methods can both meet the requirement and complete the routing and splitting tasks well: the fixedlength method and the dynamic-length method. In the fixed-length routing and splitting algorithm, each SE always passes a fixed-length information of N bits, where N is the size of the switch fabric, to the SE in the following stage. The N-bit information is actually the bitmap format of the port requests of the cell. Thus this N- bit information will carry enough information for all the SEs to complete the routing and splitting tasks. The problem of this approach is its lack of efficiency and a higher hardware complexity of implementation. SEs along the path may only care about a few output ports, but it receives all the port request information. Therefore, much redundant information is included when using this approach. A better solution is to combine the routing and splitting together using a -bit tag field for each SE in the switch fabric. The -bit field can generate four different combinations. Each SE can use the tag information to make both the routing decision and splitting decision at the same time. The four combinations can be interpreted as in following table.

3 Bit Bit Routing action Splitting action idle (no action) idle (no action) down link no splitting upper-link no splitting both links splitting Table : Self-routing / Splitting Tag Information Considering the multicast environment: after cell splitting is done, each of the two copies should carry enough routing and cell splitting information for the following stages. Therefore, the tag length of the arrival cell is equal to the tag pair ( bits) for that stage plus the tag field of each of the departure copies. Using a backward approach, the tag field for the last stage is bits. Then for the last second stage, the tag length of an incoming cell will be + bits, and for the last third stage it will be + (+ ) bits and so on. The tag of an incoming cell to the first stage will have the maximum length, which is n- + n = N- (n=log N). Hence, the maximum tag length is O(N).The tag generation circuit can be made up of some simple gates. In the SEs, the scheme is very easy and can handle the routing and splitting quite well. The SEs only need part of the information that the tag carries. For efficient design, the SEs will take the tag field for the current stage out and split the tag into two and then pass each half to the SEs in the next stage. Passing on only the portion of the tag required to the next stage improves the efficiency of the system and makes SE design simple. Figure shows an example of a multicast cell from input which will be sent to output,,,. At the Input Port Controller (IPC), destination information will be translated into a routing/splitting tag. Tag pairs will be used by different stages to make the routing and cell splitting decision. At any stage, the SE will always detect the first tag pair, take its tag pair out and divide the remaining tag pairs into two groups. The first group will be used as the tag for a cell destined to the upper link and second half will be used as the tag for a cell destined to the lower link. Stage Stage Stage Output Stage (,)(,)(,) (,) (,)(,)(,)(,)(,)(,)(,) (,)(,)(,) (,) (,) Figure : Dynamic-length Routing/Splitting Algorithm for an 8 8 Switch

4 . DYNAMIC-LENGTH BACKPRESSURE ALGORITHM In the design of a Balanced Gamma multicast switch fabric, an acknowledgement mechanism is needed to report the internal blocking and the output blocking information. Blocking information will be passed by the backpressure units located at each switch element to the IPC. The IPC will then know when copies of a cell are blocked and will keep it in the input buffer until all copies of the cell are successfully sent. In a multicast environment, the design of a backpressure mechanism will be more complex. Unlike in unicast design, the input should get the acknowledgement from perhaps several output ports to which its cell is destined before it deletes the master cell from its input buffer. Two possible candidates for a backpressure mechanism for the BG multicast switch fabric are the fixed-length algorithm and the dynamic-length algorithm. In the fixed-length backpressure algorithm, the length of information passed between stages is fixed to N, which is the size of the switch fabric. If the routing algorithm used in the switch fabric is also the fixed-length algorithm, then at any SE, simple ANDing or ORing will be enough to generate the backpressure information for each stage. This arrangement can be used for all the SEs of the switch fabric. The advantage of this method is that it is straightforward and simple to implement. However, too much redundant information will be carried all through the switch fabric. Thus the efficiency of this algorithm is relatively low. At the same time, each SE needs to know its position in the switch fabric. Therefore, some computation needs to be performed by the switch element and thus the switch fabric does not scale very well. In the dynamic-length algorithm, each stage only sends the necessary information to its previous stage. At the output stage (last stage), the only needed information is whether the cell can be placed in the output buffer or not. One bit information is enough. One stage before that, each SE will be connected to two SEs in the output stage for a particular cell in one switching cycle. Therefore, if we use the bitmap format, we need two bits to represent the output ports that this SE relates to. Thus, two bits will be used as the backpressure information for any SE of this stage. A similar approach applies to all the SEs of different stages. For the first stage (stage ), the SE will receive the acknowledgement of N/ bits from its downstream stages. It will generate the corresponding backpressure information of its stage, which is of size N, based on those messages. The N-bit bitmap information represents the blocking information of the cell across the network. It will then be sent to the IPC. The IPC will make the final decision on whether each copy of the cell can be successfully received at the output. If yes, it will remove the cell from the input buffer and try the next cell in the next switching cycle. Otherwise, it will retain and retry this cell in the next switching cycle. Using a work conserving method, for any multicast or broadcast cell, only those failed copies will be re-sent. In this algorithm, the length of backpressure information is increased as the acknowledgement moves back through network. The Balanced Gamma network architecture enabled us to achieve a more efficient and easier way to implement the dynamic-length backpressure algorithm. The backpressure functional unit inside a SE decides the backpressure information using two steps. The first step is to decide whether the cell will be blocked at this stage. If such blocking happens, the SE can make the decision right at the moment and does not need to wait for the backpressure information from the following stages. For a multicast cell, when part of the link is blocked, the control will be a bit more complex. The acknowledgement bits for the SEs in latter stages associated with the blocked link will be marked with all s. Otherwise it will wait for the backpressure information of the non-blocked copy to come back to this stage and then pass this backpressure information back to the previous stage. The second step is a processing and passing step. If the cell successfully passes this stage, then the SE only needs to wait for the blocking information from the following stages and then send this to its previous stage after some simple processing. The only thing a SE needs to know is its stage number so that it can decide the length of its backpressure information. Given an N N switch fabric, for any switch element at stage i ( i n-, n = log N), the incoming backpressure information length is n-i- bits and the outgoing backpressure information to the previous stage is of length n-i. The backpressure algorithm is used in Figure to decide the blocking information in an 8 8 switch. In this example, blocking happened at SE (,) where part of a multicast cell from input is blocked, given that the cells from input and have a higher priority. When the backpressure information arrives at the IPC at input, the IPC can easily find that copies to outlet and are received while copies to outlet and are blocked. So, it will try only the blocked copies in the next switching cycle.

5 . CONCLUSION AND FUTURE WORK Communication network applications are changing at an enormous speed. This change makes the deployment of the next generation of high-speed networks become more and more necessary and urgent. In this paper, we discuss two different ways to build a multicast switch based on MIN design. We present detailed design proposal for the multicast Balanced Gamma switch fabric with emphasis on the routing and splitting algorithm and the dynamic-length backpressure algorithm. Input ( ) Stage Stage Stage Output Stage Output Input Output Input (,,,,,, ) Output Input ( ) Output Input (,,, ) Output Input ( ) Output Input (,,, ) Output Input ( ) Output Figure : Dynamic-length Backpressure Scheme for an 8 8 Switch REFERENCES. F.A. Tobagi, Fast Packet Switch Architectures For Broadband Integrated Service Digital Networks, Proceedings of the IEEE, Vol.8, No., p.p. 9-, January, 99. M. Guo and R. Chang, Multicast ATM Switch: Survey and Performance Evaluation, ACM/SIGCOMM Computer Communication Review, p.p. 98-, April, 998. T.T. Lee, Nonblocking Copy Networks for Multicast Packet Switching, IEEE J. Select. Areas Commun., Vol., p.p. -, Dec., 988. J. Turner, Design of a Broadcast Packet Network, IEEE INFOCOM 98, p.p. -. P.U. Tagle and N.K.Sharma, Multicast Packet Switch Based on Dilated Network, IEICE Trans. Commun., Vol. E8-B, No. February 998. J. Turner, A Practical Version of Lee s Multicast Architectur, IEEE Trans. Commun., Vol., No.8, p.p.-9, August 99. Y. El-Sayed, Performance Analysis, Design and Reliability of the Balanced Gamma Network, Ph.D. Thesis, Memorial University of Newfoundland, 8. H. Sivakumar, Performance, Fault Tolerance and Reliability Networks for Broadband Packet Switch Architecture, M.Sc. Thesis, Memorial University of Newfoundland, December 99